From nobody Mon Dec 23 18:28:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1515975854755169.38168010728361; Sun, 14 Jan 2018 16:24:14 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CD62A222DDBF0; Sun, 14 Jan 2018 16:18:49 -0800 (PST) Received: from mail.paulo.ac (mail.paulo.ac [34.238.86.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A9ADE222DDBE5 for ; Sun, 14 Jan 2018 16:18:47 -0800 (PST) Received: from localhost (localhost [127.0.0.1]) by mail.paulo.ac (Postfix) with ESMTP id C7E98C08892; Mon, 15 Jan 2018 00:24:04 +0000 (UTC) Received: from mail.paulo.ac ([127.0.0.1]) by localhost (mail.paulo.ac [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uE_2-nIa9KYa; Mon, 15 Jan 2018 00:24:01 +0000 (UTC) Received: from thor.domain.name (177.204.15.215.dynamic.adsl.gvt.net.br [177.204.15.215]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.paulo.ac (Postfix) with ESMTPSA id 10E6BC78F41; Mon, 15 Jan 2018 00:23:57 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=34.238.86.106; helo=mail.paulo.ac; envelope-from=paulo@paulo.ac; receiver=edk2-devel@lists.01.org X-Virus-Scanned: amavisd-new at paulo.ac X-Spam-Flag: NO X-Spam-Score: -1.099 X-Spam-Level: X-Spam-Status: No, score=-1.099 tagged_above=-999 required=6.31 tests=[ALL_TRUSTED=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, URIBL_BLOCKED=0.001] autolearn=ham autolearn_force=no Authentication-Results: mail.paulo.ac (amavisd-new); dkim=pass (1024-bit key) header.d=paulo.ac DKIM-Filter: OpenDKIM Filter v2.11.0 mail.paulo.ac 10E6BC78F41 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=paulo.ac; s=default; t=1515975839; bh=a9oWZ3avU/247GCQuP9NxA+XNjLpw7wrTq3e62HJK7M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:In-Reply-To: References:From; b=hDQDmvjCY4PyfNRd1Za+ztr43Ur8sPyE0OW43yY5Dg+ANpTvvbBmZ09KoO6jlKleB ti9cmy64Rn0JXophOd85XiteAv5/WdlkdI/yXoiu7dYzG9njfK+Cg20f34d8PS3Z5m oW0PtUxrBxNmBNNjmnP8IU3BKcm92bKNwa8Gfae8= From: Paulo Alcantara To: edk2-devel@lists.01.org Date: Sun, 14 Jan 2018 22:23:32 -0200 Message-Id: <10dcd403b44f50ba71007b2eb7f719c47777d51e.1515974582.git.paulo@paulo.ac> X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: Subject: [edk2] [RFC v5 4/8] UefiCpuPkg/CpuExceptionHandlerLib: Add helper to validate memory addresses X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce IsLinearAddressValid() function that will be used for validating memory addresses that would get dereferenced during stack traces in IA32 and X64 CPU exceptions. Contributed-under: TianoCore Contribution Agreement 1.1 Cc: Eric Dong Cc: Laszlo Ersek Requested-by: Brian Johnson Requested-by: Jiewen Yao Signed-off-by: Paulo Alcantara --- UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c | 395 +++++= +++++++++++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h | 16 + 2 files changed, 411 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c index 66892320c8..7ac13640de 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c @@ -14,6 +14,8 @@ =20 #include "CpuExceptionCommon.h" =20 +#include + // // Error code flag indicating whether or not an error code will be // pushed on the stack if an exception occurs. @@ -59,6 +61,24 @@ CONST CHAR8 *mExceptionNameStr[] =3D { // GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mUnknownPdbFileName =3D "????"; =20 +// +// IA32 virtual memory bit definitions +// +#define IA32_PG_P BIT0 +#define IA32_PG_PS BIT7 + +// +// IA32 control register bit definitions +// +#define IA32_CR0_PG BIT31 +#define IA32_CR4_PAE BIT5 +#define IA32_CR0_PE BIT0 + +// +// IA32 CPUID 01h EDX bit definitions +// +#define IA32_CPUID1_EDX_PAE BIT6 + /** Get ASCII format string exception name by exception type. =20 @@ -194,3 +214,378 @@ GetPdbFileName ( } } } + +/** + Check if a linear address is valid by walking the page tables in 4-level + paging mode. + + @param[in] Cr3 CR3 control register. + @param[in] MaxPhyAddrBits MAXPHYADDR bits. + @param[in] LinearAddress Linear address to be checked. +**/ +STATIC +BOOLEAN +Do4LevelPagingModeCheck ( + IN UINTN Cr3, + IN UINT8 MaxPhyAddrBits, + IN UINTN LinearAddress + ) +{ + UINT64 PhysicalAddressMask; + UINTN IndexMask; + UINTN Index; + UINT64 *Pml4Table; + UINT64 *TableEntry; + UINT64 *PageDirPtrTable; + UINT64 *PageDirTable; + UINT64 *PageTable; + + // + // In 4-level paging mode, linear addresses are 48 bits wide + // + if ((UINT64)LinearAddress > 0xFFFFFFFFFFFFULL) { + return FALSE; + } + + // + // Calculate physical address mask (bits M-1:12) + // + PhysicalAddressMask =3D (LShiftU64 (1, MaxPhyAddrBits) - 1) & ~0xFFF; + // + // 9 bits for masking page table indexes out of linear addresses + // + IndexMask =3D 0x1FF; + + // + // Calculate physical address of PML4 table and index of PML4E + // + Pml4Table =3D (UINT64 *)(UINTN)((UINT64)Cr3 & PhysicalAddressMask); + Index =3D (UINTN)(RShiftU64 ((UINT64)LinearAddress, 39) & IndexMask); + + // + // Select PML4E + // + TableEntry =3D &Pml4Table[Index]; + + // + // Check if a PDPTE is present + // + if ((*TableEntry & IA32_PG_P) =3D=3D 0) { + return FALSE; + } + + // + // Calculate physical address of page-directory-pointer table and index = of + // PDPTE. + // + PageDirPtrTable =3D (UINT64 *)(UINTN)(*TableEntry & PhysicalAddressMask); + Index =3D (UINTN)(RShiftU64 ((UINT64)LinearAddress, 30) & IndexMask); + + // + // Select PDPTE + // + TableEntry =3D &PageDirPtrTable[Index]; + + // + // Check whether a PDPTE or 1GiB page entry is present + // + if ((*TableEntry & IA32_PG_P) =3D=3D 0) { + return FALSE; + } + + // + // Check if PDPTE maps an 1GiB page + // + if ((*TableEntry & IA32_PG_PS) !=3D 0) { + return TRUE; + } + + // + // Calculate physical address of page directory table and index of PDE + // + PageDirTable =3D (UINT64 *)(UINTN)(*TableEntry & PhysicalAddressMask); + Index =3D (UINTN)(RShiftU64 ((UINT64)LinearAddress, 21) & IndexMask); + + // + // Select PDE + // + TableEntry =3D &PageDirTable[Index]; + + // + // Check whether a PDE or a 2MiB page entry is present + // + if ((*TableEntry & IA32_PG_P) =3D=3D 0) { + return FALSE; + } + + // + // Check if PDE maps a 2MiB page + // + if ((*TableEntry & IA32_PG_PS) !=3D 0) { + return TRUE; + } + + // + // Calculate physical address of page table and index of PTE + // + PageTable =3D (UINT64 *)(UINTN)(*TableEntry & PhysicalAddressMask); + Index =3D (UINTN)(RShiftU64 ((UINT64)LinearAddress, 12) & IndexMask); + + // + // Select PTE + // + TableEntry =3D &PageTable[Index]; + + // + // Check if PTE maps a 4KiB page + // + if ((*TableEntry & IA32_PG_P) =3D=3D 0) { + return FALSE; + } + + return TRUE; +} + +/** + Check if a linear address is valid by walking the page tables in 32-bit = paging + mode. + + NOTE: Current UEFI implementations do not support IA32 non-PAE paging mo= de. + + @param[in] Cr3 CR3 control register. + @param[in] Cr4 CR4 control register. + @param[in] LinearAddress Linear address to be checked. +**/ +STATIC +BOOLEAN +Do32BitPagingModeCheck ( + IN UINTN Cr3, + IN UINTN Cr4, + IN UINTN LinearAddress + ) +{ + InternalPrintMessage ("!!!! Unsupported IA32 non-PAE paging mode !!!!\n"= ); + return FALSE; +} + +/** + Check if a linear address is valid by walking the page tables in PAE pag= ing + mode. + + @param[in] Cr3 CR3 control register. + @param[in] MaxPhyAddrBits MAXPHYADDR bits. + @param[in] LinearAddress Linear address to be checked. +**/ +STATIC +BOOLEAN +DoPAEPagingModeCheck ( + IN UINTN Cr3, + IN UINT8 MaxPhyAddrBits, + IN UINTN LinearAddress + ) +{ + UINT64 *PageDirPtrTable; + UINTN Index; + UINT64 *PageDirTable; + UINT64 PhysicalAddressMask; + UINTN IndexMask; + UINT64 *TableEntry; + UINT64 *PageTable; + + // + // In 32-bit PAE paging mode, linear addresses are 32 bits wide + // + if (LinearAddress > 0xFFFFFFFF) { + return FALSE; + } + + // + // Calculate physical address of page-directory-pointer table and index = of + // PDPTE register. + // + PageDirPtrTable =3D (UINT64 *)(UINTN)(Cr3 & ~0x1F); + Index =3D (UINTN)((UINT32)LinearAddress >> 30); + + // + // Select PDPTE register + // + TableEntry =3D &PageDirPtrTable[Index]; + + // + // Check if PDE is present + // + if ((*TableEntry & IA32_PG_P) =3D=3D 0) { + return FALSE; + } + + // + // Calculate physical address mask (bits M-1:12) + // + PhysicalAddressMask =3D (LShiftU64 (1, MaxPhyAddrBits) - 1) & ~0xFFF; + // + // 9 bits for masking page table indexes out of linear addresses + // + IndexMask =3D 0x1FF; + + // + // Calculate physical address of page directory table and index of PDE + // + PageDirTable =3D (UINT64 *)(UINTN)(*TableEntry & PhysicalAddressMask); + Index =3D (UINTN)(RShiftU64 ((UINT64)LinearAddress, 21) & IndexMask); + + // + // Select PDE + // + TableEntry =3D &PageDirTable[Index]; + + // + // Check whether a PTE or a 2MiB page is present + // + if ((*TableEntry & IA32_PG_P) =3D=3D 0) { + return FALSE; + } + + // + // Check if PDE maps a 2MiB page + // + if ((*TableEntry & IA32_PG_PS) !=3D 0) { + return TRUE; + } + + // + // Calculate physical address of page table and index of PTE + // + PageTable =3D (UINT64 *)(UINTN)(*TableEntry & PhysicalAddressMask); + Index =3D (UINTN)(RShiftU64 ((UINT64)LinearAddress, 12) & IndexMask); + + // + // Select PTE + // + TableEntry =3D &PageTable[Index]; + + // + // Check if PTE maps a 4KiB page + // + if ((*TableEntry & IA32_PG_P) =3D=3D 0) { + return FALSE; + } + + return TRUE; +} + +/** + Check if a linear address is valid. + + @param[in] Cr0 CR0 control register. + @param[in] Cr3 CR3 control register. + @param[in] Cr4 CR4 control register. + @param[in] LinearAddress Linear address to be checked. +**/ +BOOLEAN +IsLinearAddressValid ( + IN UINTN Cr0, + IN UINTN Cr3, + IN UINTN Cr4, + IN UINTN LinearAddress + ) +{ + UINT32 Eax; + UINT32 Edx; + UINT8 MaxPhyAddrBits; + MSR_IA32_EFER_REGISTER Msr; + BOOLEAN AddressValid; + + // + // Check for valid input parameters + // + if (Cr0 =3D=3D 0 || Cr4 =3D=3D 0 || LinearAddress =3D=3D 0) { + return FALSE; + } + + // + // Check if paging is disabled + // + if ((Cr0 & IA32_CR0_PG) =3D=3D 0) { + // + // If CR4.PAE bit is set, then the linear (or physical) address suppor= ts + // only up to 36 bits. + // + if ((UINT64)LinearAddress > 0xFFFFFFFFFULL || + ((Cr4 & IA32_CR4_PAE) =3D=3D 0 && LinearAddress > 0xFFFFFFFF)) { + return FALSE; + } + + return TRUE; + } + + // + // Paging can be enabled only if CR0.PE bit is set + // + if ((Cr0 & IA32_CR0_PE) =3D=3D 0) { + return FALSE; + } + + // + // CR3 register cannot be zero if paging is enabled + // + if (Cr3 =3D=3D 0) { + return FALSE; + } + + // + // Get MAXPHYADDR bits + // + AsmCpuid (0x80000000, &Eax, NULL, NULL, NULL); + if (Eax >=3D 0x80000008) { + AsmCpuid (0x80000008, &Eax, NULL, NULL, NULL); + MaxPhyAddrBits =3D (UINT8)Eax; + } else { + AsmCpuid (1, NULL, NULL, NULL, &Edx); + if ((Edx & IA32_CPUID1_EDX_PAE) !=3D 0) { + MaxPhyAddrBits =3D 36; + } else { + MaxPhyAddrBits =3D 32; + } + } + + // + // Check if CR4.PAE bit is not set + // + if ((Cr4 & IA32_CR4_PAE) =3D=3D 0) { + // + // Check if linear address is valid in 32-bit paging mode + // + AddressValid =3D Do32BitPagingModeCheck (Cr3, Cr4, LinearAddress); + } else { + // + // In either PAE or 4-level paging mode, physical addresses can hold o= nly + // up to 52 bits. + // + if (MaxPhyAddrBits > 52) { + return FALSE; + } + + // + // Read IA32_EFER MSR register + // + Msr.Uint64 =3D AsmReadMsr64 (MSR_IA32_EFER); + + // + // Check if IA32_EFER.LME bit is not set (e.g. PAE paging mode) + // + if (Msr.Bits.LME =3D=3D 0) { + // + // Check if linear address is valid in PAE paging mode + // + AddressValid =3D DoPAEPagingModeCheck (Cr3, MaxPhyAddrBits, LinearAd= dress); + } else { + // + // Check if linear address is valid in 4-level paging mode + // + AddressValid =3D Do4LevelPagingModeCheck (Cr3, MaxPhyAddrBits, + LinearAddress); + } + } + + return AddressValid; +} diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index ec46c2d9d3..1b51034c25 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -330,5 +330,21 @@ GetPdbFileName ( OUT CHAR8 **PdbFileName ); =20 +/** + Check if a linear address is valid. + + @param[in] Cr0 CR0 control register. + @param[in] Cr3 CR3 control register. + @param[in] Cr4 CR4 control register. + @param[in] LinearAddress Linear address to be checked. +**/ +BOOLEAN +IsLinearAddressValid ( + IN UINTN Cr0, + IN UINTN Cr3, + IN UINTN Cr4, + IN UINTN LinearAddress + ); + #endif =20 --=20 2.14.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel