From nobody Thu May 2 21:09:53 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487178736633629.4319768634317; Wed, 15 Feb 2017 09:12:16 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 783D3820DD; Wed, 15 Feb 2017 09:12:14 -0800 (PST) Received: from mail-wm0-x236.google.com (mail-wm0-x236.google.com [IPv6:2a00:1450:400c:c09::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 96BF982090 for ; Wed, 15 Feb 2017 09:12:11 -0800 (PST) Received: by mail-wm0-x236.google.com with SMTP id c85so47347266wmi.1 for ; Wed, 15 Feb 2017 09:12:11 -0800 (PST) Received: from localhost.localdomain ([196.80.229.213]) by smtp.gmail.com with ESMTPSA id n13sm5606276wrn.40.2017.02.15.09.12.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 09:12:09 -0800 (PST) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m4Y8WM4JDyEPDYX3z9h9l9eAl6ffcxatKdYSTNyImPQ=; b=K1hfaqruHe5PB1z4k4LNghyDGPFDvem1MWgfos5XdEenpwhpQmRxt+QlBFMwSmQquD oKPgCq41QV58uGS4H5TepUjlaB4CXbN5ulnW9XS4vMWzLgF7mBYPCvUJ7HQdcQPAlTcU Y+eqg5nxPp14IGWr3v3unUN3HHd0J4EmZxwQQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m4Y8WM4JDyEPDYX3z9h9l9eAl6ffcxatKdYSTNyImPQ=; b=MjSi2hQe615KlZDzOYqtWNQy+mAtlR6wy/qyKSAOf+rr1UGgAXpIOiTBT3NlnDc2Ld elhoiz9eNyz6/CFa3Xkr8VzWZp2H0oDnEqTMW05wKzmKJtH0pQgTHUfwYYXkY08CYdAQ CWNoqPBXYbyEoz6uf7GWR0+tccK3BBbrJP/CuSSsyzV+DhkhnIuuvcRwAMYJ1zRdnldU r5IuVJVZeLFV5k5yoVDldPOlk/+6Gw6IIf+GbMxaVYTaRpCwTLizCz9WnHQ5PQVBpNai h1UcYox1XJq1XLha1ttarTwpQcaDuf5uY7AbupEW7SQ2MlAgvI5SX51gEzFK/QC4QClZ gbLQ== X-Gm-Message-State: AMke39lqJ5I66hV9OdfCqdfF1if0/caJ6rz17mUolsSNOG0Oo/C6IQt9Bjaq3p/GreJAhwBg X-Received: by 10.28.167.68 with SMTP id q65mr9369445wme.126.1487178729856; Wed, 15 Feb 2017 09:12:09 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Wed, 15 Feb 2017 17:11:53 +0000 Message-Id: <1487178716-24569-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 1/4] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jiewen.yao@intel.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Jiewen Yao Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection, according to UEFI spec, we should use EFI_MEMORY_RO for write protection. The EFI_MEMORY_WP is the cache attribute instead of memory attribute. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 3 ++- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 14 ++++++-------- ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 5 +++-- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 3 ++- 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AA= rch64/Mmu.c index d8bb41978066..15d5a8173233 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -3,6 +3,7 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -224,7 +225,7 @@ EfiAttributeToArmAttribute ( ArmAttributes |=3D TT_AF; =20 // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { + if (EfiAttributes & EFI_MEMORY_RO) { ArmAttributes |=3D TT_AP_RO_RO; } =20 diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mm= u.c index 14fc22d7a59f..6dcfba69e879 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -3,6 +3,7 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
Portions copyright (c) 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -62,7 +63,7 @@ SectionToGcdAttributes ( // determine protection attributes switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) { case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write - //*GcdAttributes |=3D EFI_MEMORY_WP | EFI_MEMORY_RP; + //*GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP; break; =20 case TT_DESCRIPTOR_SECTION_AP_RW_NO: @@ -73,7 +74,7 @@ SectionToGcdAttributes ( // read only cases map to write-protect case TT_DESCRIPTOR_SECTION_AP_RO_NO: case TT_DESCRIPTOR_SECTION_AP_RO_RO: - *GcdAttributes |=3D EFI_MEMORY_WP; + *GcdAttributes |=3D EFI_MEMORY_RO; break; =20 default: @@ -126,7 +127,7 @@ PageToGcdAttributes ( // determine protection attributes switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) { case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write - //*GcdAttributes |=3D EFI_MEMORY_WP | EFI_MEMORY_RP; + //*GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP; break; =20 case TT_DESCRIPTOR_PAGE_AP_RW_NO: @@ -137,7 +138,7 @@ PageToGcdAttributes ( // read only cases map to write-protect case TT_DESCRIPTOR_PAGE_AP_RO_NO: case TT_DESCRIPTOR_PAGE_AP_RO_RO: - *GcdAttributes |=3D EFI_MEMORY_WP; + *GcdAttributes |=3D EFI_MEMORY_RO; break; =20 default: @@ -730,9 +731,6 @@ EfiAttributeToArmAttribute ( ArmAttributes =3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLO= C; // TEX [2:0] =3D 001, C=3D1, B=3D1 break; =20 - case EFI_MEMORY_WP: - case EFI_MEMORY_XP: - case EFI_MEMORY_RP: case EFI_MEMORY_UCE: default: // Cannot be implemented UEFI definition unclear for ARM @@ -743,7 +741,7 @@ EfiAttributeToArmAttribute ( } =20 // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { + if (EfiAttributes & EFI_MEMORY_RO) { ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AP_RO_RO; } else { ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AP_RW_RW; diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/C= puMmuCommon.c index 723604d1df96..54d9b0163331 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -1,6 +1,7 @@ /** @file * * Copyright (c) 2013, ARM Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
* * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -236,7 +237,7 @@ CpuConvertPagesToUncachedVirtualAddress ( // be the PCI address. Code should always use the CPU address, and we wi= ll or in VirtualMask // to that address. // - Status =3D SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0); + Status =3D SetMemoryAttributes (Address, Length, EFI_MEMORY_RO, 0); if (!EFI_ERROR (Status)) { Status =3D SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEM= ORY_UC, VirtualMask); } @@ -264,7 +265,7 @@ CpuReconvertPages ( // // Unmap the aliased Address // - Status =3D SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMOR= Y_WP, 0); + Status =3D SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMOR= Y_RO, 0); if (!EFI_ERROR (Status)) { // // Restore atttributes diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 540069a59b2e..6aa970bc0514 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -3,6 +3,7 @@ * * Copyright (c) 2011-2014, ARM Limited. All rights reserved. * Copyright (c) 2016, Linaro Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
* * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -89,7 +90,7 @@ PageAttributeToGcdAttribute ( // Determine protection attributes if (((PageAttributes & TT_AP_MASK) =3D=3D TT_AP_NO_RO) || ((PageAttribut= es & TT_AP_MASK) =3D=3D TT_AP_RO_RO)) { // Read only cases map to write-protect - GcdAttributes |=3D EFI_MEMORY_WP; + GcdAttributes |=3D EFI_MEMORY_RO; } =20 // Process eXecute Never attribute --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 21:09:53 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 148717873799519.709955381117084; Wed, 15 Feb 2017 09:12:17 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AA000820E7; Wed, 15 Feb 2017 09:12:14 -0800 (PST) Received: from mail-wm0-x235.google.com (mail-wm0-x235.google.com [IPv6:2a00:1450:400c:c09::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 079B382098 for ; Wed, 15 Feb 2017 09:12:13 -0800 (PST) Received: by mail-wm0-x235.google.com with SMTP id v186so47364577wmd.0 for ; Wed, 15 Feb 2017 09:12:12 -0800 (PST) Received: from localhost.localdomain ([196.80.229.213]) by smtp.gmail.com with ESMTPSA id n13sm5606276wrn.40.2017.02.15.09.12.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 09:12:10 -0800 (PST) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W9mBkPQBZ2xJecjpowmoGf0x4J/DKjvrZJwQv85vuXU=; b=jNh90TplLQ46u3TSaBrs0qOT1IajHASBo4z6CWWoKV90Rbu+vePIjwvGPaFVoeDUyX kYlhVj17AdqA+yD0XqXW5EaRL1YxIJdm36FXtxNJbSGCKulkFLryHI03jZp6F+1v0bRi hv60QCI6dR3NGiRvMWAR7V/qo+oVklHTxRcd4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W9mBkPQBZ2xJecjpowmoGf0x4J/DKjvrZJwQv85vuXU=; b=fJgCv6GP4/TocgqHJsFR/ehbeTkf+4G29GPk99yM4v0gVZWwqbnW7gOjtaoL+Oo7Qw sQXzYzlcb/+NQEJvWfh0fYmHG39vo1g6/q7kZyNtqjZ82vG9/D6K+ZQfrLRipaMVrP+0 hbGMXtm8moY5Vob5OYJ9OYVbua9HKkov4yqC0dZNKM9KqiAk9PlrtZU9M1GZzHy+89Xm I5Q8Os1c4m3VceJVLEMkCQivMmdWbVzWhK5rZAcZ1K3tUK8rSe0NczE2681P9urfAebS oaW5bgJ+rJyE7DbS0dfqwaIGDhsgCfUSJJ7LlvuJ0q/F+jq4tsGw1EBGtEP5J1AOoNN0 N4kg== X-Gm-Message-State: AMke39kjhlBDXlAZQXAEEhsBKqSWZ9xkumJvhbidbCBhZHiRKy0n09zlM3CisJIpNX54WV+L X-Received: by 10.28.109.27 with SMTP id i27mr8745753wmc.54.1487178731473; Wed, 15 Feb 2017 09:12:11 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Wed, 15 Feb 2017 17:11:54 +0000 Message-Id: <1487178716-24569-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 2/4] ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttribute X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jiewen.yao@intel.com, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The single user of EfiAttributeToArmAttribute () is the protocol method EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), which uses the return value to compare against the ARM attributes of an existing mapping, to infer whether it is actually necessary to change anything, or whether the requested update is redundant. This saves some cache and TLB maintenance on 32-bit ARM systems that use uncached translation tables. However, EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() may be invoked with only permission bits set, in which case the implied requested action is to update the permissions of the region without modifying the cacheability attributes. This is currently not possible, because EfiAttributeToArmAttribute () ASSERT()s [on AArch64] on Attributes arguments that lack a cacheability bit. So let's simply return TT_ATTR_INDX_MASK (AArch64) or TT_DESCRIPTOR_SECTION_TYPE_FAULT (ARM) in these cases (or'ed with the appropriate permission bits). This way, the return value is equally suitable for checking whether the attributes need to be modified, but in a way that accommodates the use without a cacheability bit set. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 4 +--- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 3 --- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AA= rch64/Mmu.c index 15d5a8173233..7688846e70cb 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -216,9 +216,7 @@ EfiAttributeToArmAttribute ( ArmAttributes =3D TT_ATTR_INDX_MEMORY_WRITE_BACK; break; default: - DEBUG ((EFI_D_ERROR, "EfiAttributeToArmAttribute: 0x%lX attributes is = not supported.\n", EfiAttributes)); - ASSERT (0); - ArmAttributes =3D TT_ATTR_INDX_DEVICE_MEMORY; + ArmAttributes =3D TT_ATTR_INDX_MASK; } =20 // Set the access flag to match the block attributes diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mm= u.c index 6dcfba69e879..b6ba975b353a 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -733,10 +733,7 @@ EfiAttributeToArmAttribute ( =20 case EFI_MEMORY_UCE: default: - // Cannot be implemented UEFI definition unclear for ARM - // Cause a page fault if these ranges are accessed. ArmAttributes =3D TT_DESCRIPTOR_SECTION_TYPE_FAULT; - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): Unsupported attribute %x= will page fault on access\n", EfiAttributes)); break; } =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 21:09:53 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487178741281968.3297700913719; Wed, 15 Feb 2017 09:12:21 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E777B82099; Wed, 15 Feb 2017 09:12:16 -0800 (PST) Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com [IPv6:2a00:1450:400c:c09::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 603B982098 for ; Wed, 15 Feb 2017 09:12:14 -0800 (PST) Received: by mail-wm0-x232.google.com with SMTP id r141so45887471wmg.1 for ; Wed, 15 Feb 2017 09:12:14 -0800 (PST) Received: from localhost.localdomain ([196.80.229.213]) by smtp.gmail.com with ESMTPSA id n13sm5606276wrn.40.2017.02.15.09.12.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 09:12:12 -0800 (PST) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/6G7fvFSTF0PF+7NmXcLXKQcm+tAQmeeDvuefLvTFYw=; b=gMvvA32B9fm00gmZVEpmOrvoh/B5yNnv2UcNlTg5nucABJkj1uObxp0z5O5/OCTPee AP25iQaadto9H9hS4E6mtUm2ZSIQjepDXVASRo6Ki9LthuJ8L5cDOyUTB6B0JvwOGdvx 2bso324rpKAZwVmkrwxg+0sR8mB6Xc6/JC+4s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/6G7fvFSTF0PF+7NmXcLXKQcm+tAQmeeDvuefLvTFYw=; b=XgxJwv6I/sGhrXymg3em4Ls5uvOzK8I1Lze5f7ijpe+dKknkKoHLS6ay3lxQY4gA8h fjyRbhkAPrgxkgRRhSKzW1VIfWouN1zap8jhNdlb6BahDx/k/Oi2pXOR4VfkNt/3zPKE ARov8QOs+5L5D4WPvEFSHutYr4dvOmybmS7Y71kr6oPtOTUYUHz4DemW94LWptkU1A4Z xSALlpq1NoJ8GPmq2mU4koVVt8QpOw0BtTCuKUSnG9ltMTr+JjUgBF1Hwbopz64jbxLk /myTQwgjX4g0/o/ikuDsQ4kJD9fHd1/IyfmrQ+4v0cYNKudgbYvvE6hkrrUzXxKGuVAl 1EVw== X-Gm-Message-State: AMke39nYTNl6VpAbzyoxbRC9vIrnL9RhucE4NmvciX0B9Lda4uAF1IyMQ8ps2MDrLeEIS5v+ X-Received: by 10.28.210.65 with SMTP id j62mr8952875wmg.9.1487178732949; Wed, 15 Feb 2017 09:12:12 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Wed, 15 Feb 2017 17:11:55 +0000 Message-Id: <1487178716-24569-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 3/4] ArmPkg/CpuDxe: ARM: ignore page table updates that only change permissions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jiewen.yao@intel.com, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Currently, we have not implemented support on 32-bit ARM for managing permission bits in the page tables. Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, let's simply ignore those for now. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mm= u.c index b6ba975b353a..89e429925ba9 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -680,6 +680,13 @@ SetMemoryAttributes ( { EFI_STATUS Status; =20 + // + // Ignore invocations that only modify permission bits + // + if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) =3D=3D 0) { + return EFI_SUCCESS; + } + if(((BaseAddress & 0xFFFFF) =3D=3D 0) && ((Length & 0xFFFFF) =3D=3D 0)) { // Is the base and length a multiple of 1 MB? DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x= %x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes)); --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 21:09:53 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487178743692314.06176702472146; Wed, 15 Feb 2017 09:12:23 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 234B5820F0; Wed, 15 Feb 2017 09:12:18 -0800 (PST) Received: from mail-wr0-x235.google.com (mail-wr0-x235.google.com [IPv6:2a00:1450:400c:c0c::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3F3C482090 for ; Wed, 15 Feb 2017 09:12:16 -0800 (PST) Received: by mail-wr0-x235.google.com with SMTP id c4so37600921wrd.2 for ; Wed, 15 Feb 2017 09:12:16 -0800 (PST) Received: from localhost.localdomain ([196.80.229.213]) by smtp.gmail.com with ESMTPSA id n13sm5606276wrn.40.2017.02.15.09.12.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 09:12:13 -0800 (PST) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ApY7PI37whBifL85OS0d5SqTQ98eo2ofcxBtWw2+Yq8=; b=ES0ZNDAImnKj4A1RJlzWc+U+vsI1eL8UbsKF+kmkOR+/zZVetQOdUI6jGx09Zn+VX3 5yOD+EddJolnC/eHz4MSGdimmdsJStUIF/l3XVUGvSXuKiWzRW850e1G8Io4ZGZiAddX f3ASwupTlG2APZpuFiEOhhC3cuZtE5Ay14pbo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ApY7PI37whBifL85OS0d5SqTQ98eo2ofcxBtWw2+Yq8=; b=oN9FHKn7bz3kY7RByqjUVhv6m48pA1QDk+701qh9RciQWZj5/z9fIIo9w4kvgvFLr1 nClWYXd+4ZzL+SUM7iRiMpQbju8MrqT54HUjNro6FY+l0Iy+RcbBkxcIPJsyqOX3wELL HpIPdFI+l6SQhkZujjiuIC5hUSr9bQ60wF0z2BHViKIHBPVleFuDtPHApFj3cwRs6v8D 9BB4ePkDdWxPE2rXEux3SGX4O3JERRea7B6hseu33qmcjN+4PY3A9BDO1AYsTrDl/2Fx Eox6QYi0r3J1liHF/1CX/kYScVCVmEi/5c5Uv0fmifUDA/PLePChnAOHzfZkhvvkOEjf smpA== X-Gm-Message-State: AMke39k6S+RrW6ebyHRyrrZ0oaqCjns1TBcJnH/e9ls8n0nc7QHSUrL8ZM8BajxrxgKiAVkg X-Received: by 10.223.163.75 with SMTP id d11mr30622319wrb.87.1487178734601; Wed, 15 Feb 2017 09:12:14 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Wed, 15 Feb 2017 17:11:56 +0000 Message-Id: <1487178716-24569-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 4/4] ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jiewen.yao@intel.com, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, add support for this in the AARCH64 MMU code. Move the EFI_MEMORY_CACHETYPE_MASK macro to a shared location between CpuDxe and ArmMmuLib so we don't have to introduce yet another definition. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Drivers/CpuDxe/CpuDxe.h | 8 -- ArmPkg/Include/Library/ArmLib.h | 4 + ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 91 ++++++++++++++------ 3 files changed, 67 insertions(+), 36 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h index d16abe400ef3..80c305d53dd1 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -39,14 +39,6 @@ #include =20 =20 -#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \ - EFI_MEMORY_WC | \ - EFI_MEMORY_WT | \ - EFI_MEMORY_WB | \ - EFI_MEMORY_UCE \ - ) - - /** This function registers and enables the handler specified by InterruptHa= ndler for a processor interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index 19501efa991f..24ffe9f1aaa7 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -26,6 +26,10 @@ #error "Unknown chipset." #endif =20 +#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \ + EFI_MEMORY_WT | EFI_MEMORY_WB | \ + EFI_MEMORY_UCE) + /** * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECUR= E_* attributes. * diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 6aa970bc0514..9e0593ce598b 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -101,27 +101,6 @@ PageAttributeToGcdAttribute ( return GcdAttributes; } =20 -ARM_MEMORY_REGION_ATTRIBUTES -GcdAttributeToArmAttribute ( - IN UINT64 GcdAttributes - ) -{ - switch (GcdAttributes & 0xFF) { - case EFI_MEMORY_UC: - return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - case EFI_MEMORY_WC: - return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; - case EFI_MEMORY_WT: - return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH; - case EFI_MEMORY_WB: - return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; - default: - DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is = not supported.\n", GcdAttributes)); - ASSERT (0); - return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - } -} - #define MIN_T0SZ 16 #define BITS_PER_LEVEL 9 =20 @@ -425,6 +404,48 @@ FillTranslationTable ( ); } =20 +STATIC +UINT64 +GcdAttributeToPageAttribute ( + IN UINT64 GcdAttributes + ) +{ + UINT64 PageAttributes; + + switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) { + case EFI_MEMORY_UC: + PageAttributes =3D TT_ATTR_INDX_DEVICE_MEMORY; + break; + case EFI_MEMORY_WC: + PageAttributes =3D TT_ATTR_INDX_MEMORY_NON_CACHEABLE; + break; + case EFI_MEMORY_WT: + PageAttributes =3D TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHA= REABLE; + break; + case EFI_MEMORY_WB: + PageAttributes =3D TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREA= BLE; + break; + default: + PageAttributes =3D TT_ATTR_INDX_MASK; + break; + } + + if ((GcdAttributes & EFI_MEMORY_XP) !=3D 0 || + (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) =3D=3D EFI_MEMORY_UC) { + if (ArmReadCurrentEL () =3D=3D AARCH64_EL2) { + PageAttributes |=3D TT_XN_MASK; + } else { + PageAttributes |=3D TT_UXN_MASK | TT_PXN_MASK; + } + } + + if ((GcdAttributes & EFI_MEMORY_RO) !=3D 0) { + PageAttributes |=3D TT_AP_RO_RO; + } + + return PageAttributes | TT_AF; +} + RETURN_STATUS SetMemoryAttributes ( IN EFI_PHYSICAL_ADDRESS BaseAddress, @@ -434,17 +455,31 @@ SetMemoryAttributes ( ) { RETURN_STATUS Status; - ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion; UINT64 *TranslationTable; - - MemoryRegion.PhysicalBase =3D BaseAddress; - MemoryRegion.VirtualBase =3D BaseAddress; - MemoryRegion.Length =3D Length; - MemoryRegion.Attributes =3D GcdAttributeToArmAttribute (Attributes); + UINT64 PageAttributes; + UINT64 PageAttributeMask; + + PageAttributes =3D GcdAttributeToPageAttribute (Attributes); + PageAttributeMask =3D 0; + + if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) =3D=3D 0) { + // + // No memory type was set in Attributes, so we are going to update the + // permissions only. + // + PageAttributes &=3D TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK; + PageAttributeMask =3D ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK | + TT_PXN_MASK | TT_XN_MASK); + } =20 TranslationTable =3D ArmGetTTBR0BaseAddress (); =20 - Status =3D FillTranslationTable (TranslationTable, &MemoryRegion); + Status =3D UpdateRegionMapping ( + TranslationTable, + BaseAddress, + Length, + PageAttributes, + PageAttributeMask); if (RETURN_ERROR (Status)) { return Status; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel