From nobody Sat Dec 28 12:43:38 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1493915662080483.6477305616387; Thu, 4 May 2017 09:34:22 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 46B1D21A134BB; Thu, 4 May 2017 09:34:18 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0B1F221A13489 for ; Thu, 4 May 2017 09:34:17 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 May 2017 09:34:14 -0700 Received: from rhe-mobl1.ccr.corp.intel.com (HELO jyao1-MOBL.ccr.corp.intel.com) ([10.254.211.48]) by fmsmga005.fm.intel.com with ESMTP; 04 May 2017 09:34:13 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,287,1491289200"; d="scan'208";a="97285346" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 5 May 2017 00:32:39 +0800 Message-Id: <1493915561-8500-2-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1493915561-8500-1-git-send-email-jiewen.yao@intel.com> References: <1493915561-8500-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH V5 1/3] MdeModulePkg/Include: Add IOMMU protocol definition. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Leo Duran , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This protocol is to abstract DMA access from IOMMU. 1) Intel "DMAR" ACPI table. 2) AMD "IVRS" ACPI table 3) ARM "IORT" ACPI table. There might be multiple IOMMU engines on one platform. For example, one for graphic and one for rest PCI devices (such as ATA/USB). All IOMMU engines are reported by one ACPI table. All IOMMU protocol provider should be based upon ACPI table. This single IOMMU protocol can handle multiple IOMMU engines on one system. This IOMMU protocol provider can use UEFI device path to distinguish if the device is graphic or ATA/USB, and find out corresponding IOMMU engine. The IOMMU protocol provides 2 capabilities: A) Set DMA access attribute - such as write/read control. B) Remap DMA memory - such as remap above 4GiB system memory address to below 4GiB device address. It provides AllocateBuffer/FreeBuffer/Map/Unmap for DMA memory. The remapping can be static (fixed at build time) or dynamic (allocate at runtime). 4) AMD "SEV" feature. We can have an AMD SEV specific IOMMU driver to produce IOMMU protocol, and manage SEV bit. Cc: Ruiyu Ni Cc: Leo Duran Cc: Brijesh Singh Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Leo Duran Reviewed-by: Ruiyu Ni Tested-by: Ard Biesheuvel Tested-by: Brijesh Singh --- MdeModulePkg/Include/Protocol/IoMmu.h | 259 ++++++++++++++++++++ MdeModulePkg/MdeModulePkg.dec | 3 + 2 files changed, 262 insertions(+) diff --git a/MdeModulePkg/Include/Protocol/IoMmu.h b/MdeModulePkg/Include/P= rotocol/IoMmu.h new file mode 100644 index 0000000..9d25c17 --- /dev/null +++ b/MdeModulePkg/Include/Protocol/IoMmu.h @@ -0,0 +1,259 @@ +/** @file + EFI IOMMU Protocol. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made availabl= e under +the terms and conditions of the BSD License that accompanies this distribu= tion. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + +**/ + + +#ifndef __IOMMU_H__ +#define __IOMMU_H__ + +// +// IOMMU Protocol GUID value +// +#define EDKII_IOMMU_PROTOCOL_GUID \ + { \ + 0x4e939de9, 0xd948, 0x4b0f, { 0x88, 0xed, 0xe6, 0xe1, 0xce, 0x51, 0x= 7c, 0x1e } \ + } + +// +// Forward reference for pure ANSI compatability +// +typedef struct _EDKII_IOMMU_PROTOCOL EDKII_IOMMU_PROTOCOL; + +// +// Revision The revision to which the IOMMU interface adheres. +// All future revisions must be backwards compatible. +// If a future version is not back wards compatible it is not the= same GUID. +// +#define EDKII_IOMMU_PROTOCOL_REVISION 0x00010000 + +// +// IOMMU Access for SetAttribute +// +// These types can be "ORed" together as needed. +// Any undefined bits are reserved and must be zero. +// +#define EDKII_IOMMU_ACCESS_READ 0x1 +#define EDKII_IOMMU_ACCESS_WRITE 0x2 + +// +// IOMMU Operation for Map +// +typedef enum { + /// + /// A read operation from system memory by a bus master that is not capa= ble of producing + /// PCI dual address cycles. + /// + EdkiiIoMmuOperationBusMasterRead, + /// + /// A write operation from system memory by a bus master that is not cap= able of producing + /// PCI dual address cycles. + /// + EdkiiIoMmuOperationBusMasterWrite, + /// + /// Provides both read and write access to system memory by both the pro= cessor and a bus + /// master that is not capable of producing PCI dual address cycles. + /// + EdkiiIoMmuOperationBusMasterCommonBuffer, + /// + /// A read operation from system memory by a bus master that is capable = of producing PCI + /// dual address cycles. + /// + EdkiiIoMmuOperationBusMasterRead64, + /// + /// A write operation to system memory by a bus master that is capable o= f producing PCI + /// dual address cycles. + /// + EdkiiIoMmuOperationBusMasterWrite64, + /// + /// Provides both read and write access to system memory by both the pro= cessor and a bus + /// master that is capable of producing PCI dual address cycles. + /// + EdkiiIoMmuOperationBusMasterCommonBuffer64, + EdkiiIoMmuOperationMaximum +} EDKII_IOMMU_OPERATION; + +// +// IOMMU attribute for AllocateBuffer +// Any undefined bits are reserved and must be zero. +// +#define EDKII_IOMMU_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 +#define EDKII_IOMMU_ATTRIBUTE_MEMORY_CACHED 0x0800 +#define EDKII_IOMMU_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 + +#define EDKII_IOMMU_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER (EDKII_IOMMU_ATT= RIBUTE_MEMORY_WRITE_COMBINE | EDKII_IOMMU_ATTRIBUTE_MEMORY_CACHED | EDKII_I= OMMU_ATTRIBUTE_DUAL_ADDRESS_CYCLE) + +#define EDKII_IOMMU_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EDKII_IOMMU_AT= TRIBUTE_VALID_FOR_ALLOCATE_BUFFER) + +/** + Set IOMMU attribute for a system memory. + + If the IOMMU protocol exists, the system memory cannot be used + for DMA by default. + + When a device requests a DMA access for a system memory, + the device driver need use SetAttribute() to update the IOMMU + attribute to request DMA access (read and/or write). + + The DeviceHandle is used to identify which device submits the request. + The IOMMU implementation need translate the device path to an IOMMU devi= ce ID, + and set IOMMU hardware register accordingly. + 1) DeviceHandle can be a standard PCI device. + The memory for BusMasterRead need set EDKII_IOMMU_ACCESS_READ. + The memory for BusMasterWrite need set EDKII_IOMMU_ACCESS_WRITE. + The memory for BusMasterCommonBuffer need set EDKII_IOMMU_ACCESS_READ= |EDKII_IOMMU_ACCESS_WRITE. + After the memory is used, the memory need set 0 to keep it being prot= ected. + 2) DeviceHandle can be an ACPI device (ISA, I2C, SPI, etc). + The memory for DMA access need set EDKII_IOMMU_ACCESS_READ and/or EDK= II_IOMMU_ACCESS_WRITE. + + @param[in] This The protocol instance pointer. + @param[in] DeviceHandle The device who initiates the DMA access re= quest. + @param[in] Mapping The mapping value returned from Map(). + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by DeviceAddress and Length. + @retval EFI_INVALID_PARAMETER DeviceHandle is an invalid handle. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned = by Map(). + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED DeviceHandle is unknown by the IOMMU. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by Mapping. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_IOMMU_SET_ATTRIBUTE)( + IN EDKII_IOMMU_PROTOCOL *This, + IN EFI_HANDLE DeviceHandle, + IN VOID *Mapping, + IN UINT64 IoMmuAccess + ); + +/** + Provides the controller-specific addresses required to access system mem= ory from a + DMA bus master. + + @param This The protocol instance pointer. + @param Operation Indicates if the bus master is going to re= ad or write to system memory. + @param HostAddress The system memory address to map to the PC= I controller. + @param NumberOfBytes On input the number of bytes to map. On ou= tput the number of bytes + that were mapped. + @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned Numb= erOfBytes. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a comm= on buffer. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. + @retval EFI_DEVICE_ERROR The system hardware could not map the requ= ested address. + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_IOMMU_MAP)( + IN EDKII_IOMMU_PROTOCOL *This, + IN EDKII_IOMMU_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +/** + Completes the Map() operation and releases any corresponding resources. + + @param This The protocol instance pointer. + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned b= y Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target s= ystem memory. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_IOMMU_UNMAP)( + IN EDKII_IOMMU_PROTOCOL *This, + IN VOID *Mapping + ); + +/** + Allocates pages that are suitable for an OperationBusMasterCommonBuffer = or + OperationBusMasterCommonBuffer64 mapping. + + @param This The protocol instance pointer. + @param Type This parameter is not used and must be ign= ored. + @param MemoryType The type of memory to allocate, EfiBootSer= vicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory = address of the + allocated range. + @param Attributes The requested bit mask of attributes for t= he allocated range. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal = attribute bits are + MEMORY_WRITE_COMBINE and MEMORY_CACHED. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_IOMMU_ALLOCATE_BUFFER)( + IN EDKII_IOMMU_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + IN OUT VOID **HostAddress, + IN UINT64 Attributes + ); + +/** + Frees memory that was allocated with AllocateBuffer(). + + @param This The protocol instance pointer. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allo= cated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress = and Pages + was not allocated with AllocateBuffer(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_IOMMU_FREE_BUFFER)( + IN EDKII_IOMMU_PROTOCOL *This, + IN UINTN Pages, + IN VOID *HostAddress + ); + +/// +/// IOMMU Protocol structure. +/// +struct _EDKII_IOMMU_PROTOCOL { + UINT64 Revision; + EDKII_IOMMU_SET_ATTRIBUTE SetAttribute; + EDKII_IOMMU_MAP Map; + EDKII_IOMMU_UNMAP Unmap; + EDKII_IOMMU_ALLOCATE_BUFFER AllocateBuffer; + EDKII_IOMMU_FREE_BUFFER FreeBuffer; +}; + +/// +/// IOMMU Protocol GUID variable. +/// +extern EFI_GUID gEdkiiIoMmuProtocolGuid; + +#endif diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 356b3e1..db596b6 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -540,6 +540,9 @@ ## Include/Protocol/NonDiscoverableDevice.h gEdkiiNonDiscoverableDeviceProtocolGuid =3D { 0x0d51905b, 0xb77e, 0x452a= , {0xa2, 0xc0, 0xec, 0xa0, 0xcc, 0x8d, 0x51, 0x4a } } =20 + ## Include/Protocol/IoMmu.h + gEdkiiIoMmuProtocolGuid =3D { 0x4e939de9, 0xd948, 0x4b0f, { 0x88, 0xed, = 0xe6, 0xe1, 0xce, 0x51, 0x7c, 0x1e } } + # # [Error.gEfiMdeModulePkgTokenSpaceGuid] # 0x80000001 | Invalid value provided. --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Dec 28 12:43:38 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1493915665217961.5010886117526; Thu, 4 May 2017 09:34:25 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7700421A07091; Thu, 4 May 2017 09:34:18 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2355B21A1348C for ; Thu, 4 May 2017 09:34:17 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 May 2017 09:34:16 -0700 Received: from rhe-mobl1.ccr.corp.intel.com (HELO jyao1-MOBL.ccr.corp.intel.com) ([10.254.211.48]) by fmsmga005.fm.intel.com with ESMTP; 04 May 2017 09:34:15 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,287,1491289200"; d="scan'208";a="97285352" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 5 May 2017 00:32:40 +0800 Message-Id: <1493915561-8500-3-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1493915561-8500-1-git-send-email-jiewen.yao@intel.com> References: <1493915561-8500-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH V5 2/3] MdeModulePkg/PciHostBridge: Add IOMMU support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Leo Duran , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" If IOMMU protocol is installed, PciHostBridge just calls IOMMU AllocateBuffer/FreeBuffer/Map/Unmap. PciHostBridge does not set IOMMU access attribute, because it does not know which device request the DMA. This work is done by PciBus driver. Cc: Ruiyu Ni Cc: Leo Duran Cc: Brijesh Singh Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Leo Duran Reviewed-by: Ruiyu Ni Tested-by: Ard Biesheuvel Tested-by: Brijesh Singh --- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 37 ++++++++++= ++ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf | 2 + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h | 2 + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 61 ++++++++++= ++++++++++ 4 files changed, 102 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeMod= ulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 9005dee..70726a6 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -28,6 +28,10 @@ GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeSt= r[] =3D { L"I/O", L"Mem", L"PMem", L"Mem64", L"PMem64", L"Bus" }; =20 +EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; +EFI_EVENT mIoMmuEvent; +VOID *mIoMmuRegistration; + /** Ensure the compatibility of an IO space descriptor with the IO aperture. =20 @@ -313,6 +317,28 @@ FreeMemorySpaceMap: } =20 /** + Event notification that is fired when IOMMU protocol is installed. + + @param Event The Event that is being processed. + @param Context Event Context. + +**/ +VOID +EFIAPI +IoMmuProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + + Status =3D gBS->LocateProtocol (&gEdkiiIoMmuProtocolGuid, NULL, (VOID **= )&mIoMmuProtocol); + if (!EFI_ERROR(Status)) { + gBS->CloseEvent (mIoMmuEvent); + } +} + +/** =20 Entry point of this driver. =20 @@ -489,6 +515,17 @@ InitializePciHostBridge ( ASSERT_EFI_ERROR (Status); } PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount); + + if (!EFI_ERROR (Status)) { + mIoMmuEvent =3D EfiCreateProtocolNotifyEvent ( + &gEdkiiIoMmuProtocolGuid, + TPL_CALLBACK, + IoMmuProtocolCallback, + NULL, + &mIoMmuRegistration + ); + } + return Status; } =20 diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf b/M= deModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf index d8b0439..42bd8a2 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf @@ -41,6 +41,7 @@ BaseMemoryLib BaseLib PciSegmentLib + UefiLib PciHostBridgeLib =20 [Protocols] @@ -49,6 +50,7 @@ gEfiDevicePathProtocolGuid ## BY_START gEfiPciRootBridgeIoProtocolGuid ## BY_START gEfiPciHostBridgeResourceAllocationProtocolGuid ## BY_START + gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES =20 [Depex] gEfiCpuIo2ProtocolGuid AND diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h b/MdeMod= ulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h index 13185b4..1fec88b 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h @@ -27,6 +27,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include #include #include +#include #include #include #include @@ -34,6 +35,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include #include #include +#include #include "PciHostResource.h" =20 =20 diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeM= odulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index 8af131b..068295b 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -17,6 +17,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include "PciRootBridge.h" #include "PciHostResource.h" =20 +extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; + #define NO_MAPPING (VOID *) (UINTN) -1 =20 // @@ -1072,6 +1074,26 @@ RootBridgeIoMap ( =20 RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); =20 + if (mIoMmuProtocol !=3D NULL) { + if (!RootBridge->DmaAbove4G) { + // + // Clear 64bit support + // + if (Operation > EfiPciOperationBusMasterCommonBuffer) { + Operation =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operati= on - EfiPciOperationBusMasterRead64); + } + } + Status =3D mIoMmuProtocol->Map ( + mIoMmuProtocol, + Operation, + HostAddress, + NumberOfBytes, + DeviceAddress, + Mapping + ); + return Status; + } + PhysicalAddress =3D (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress; if ((!RootBridge->DmaAbove4G || (Operation !=3D EfiPciOperationBusMasterRead64 && @@ -1194,8 +1216,18 @@ RootBridgeIoUnmap ( MAP_INFO *MapInfo; LIST_ENTRY *Link; PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + EFI_STATUS Status; + + if (mIoMmuProtocol !=3D NULL) { + Status =3D mIoMmuProtocol->Unmap ( + mIoMmuProtocol, + Mapping + ); + return Status; + } =20 RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + // // See if the Map() operation associated with this Unmap() required a ma= pping // buffer. If a mapping buffer was not required, then this function simp= ly @@ -1312,6 +1344,24 @@ RootBridgeIoAllocateBuffer ( =20 RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); =20 + if (mIoMmuProtocol !=3D NULL) { + if (!RootBridge->DmaAbove4G) { + // + // Clear DUAL_ADDRESS_CYCLE + // + Attributes &=3D ~EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE; + } + Status =3D mIoMmuProtocol->AllocateBuffer ( + mIoMmuProtocol, + Type, + MemoryType, + Pages, + HostAddress, + Attributes + ); + return Status; + } + AllocateType =3D AllocateAnyPages; if (!RootBridge->DmaAbove4G || (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) =3D=3D 0) { @@ -1356,6 +1406,17 @@ RootBridgeIoFreeBuffer ( OUT VOID *HostAddress ) { + EFI_STATUS Status; + + if (mIoMmuProtocol !=3D NULL) { + Status =3D mIoMmuProtocol->FreeBuffer ( + mIoMmuProtocol, + Pages, + HostAddress + ); + return Status; + } + return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages= ); } =20 --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Dec 28 12:43:38 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1493915667856889.0936420724515; Thu, 4 May 2017 09:34:27 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A8B6D21A134AE; Thu, 4 May 2017 09:34:20 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A962321A070B4 for ; Thu, 4 May 2017 09:34:19 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 May 2017 09:34:19 -0700 Received: from rhe-mobl1.ccr.corp.intel.com (HELO jyao1-MOBL.ccr.corp.intel.com) ([10.254.211.48]) by fmsmga005.fm.intel.com with ESMTP; 04 May 2017 09:34:16 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,287,1491289200"; d="scan'208";a="97285367" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 5 May 2017 00:32:41 +0800 Message-Id: <1493915561-8500-4-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1493915561-8500-1-git-send-email-jiewen.yao@intel.com> References: <1493915561-8500-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH V5 3/3] MdeModulePkg/PciBus: Add IOMMU support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Leo Duran , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" If IOMMU protocol is installed, PciBus need call IOMMU to set access attribute for the PCI device in Map/Ummap. Only after the access attribute is set, the PCI device can access the DMA memory. Cc: Ruiyu Ni Cc: Leo Duran Cc: Brijesh Singh Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Leo Duran Reviewed-by: Ruiyu Ni Tested-by: Ard Biesheuvel Tested-by: Brijesh Singh --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 9 ++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 47 ++++++++++++++++++-- 4 files changed, 54 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.c index f3be47a..950cacc 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c @@ -42,6 +42,7 @@ UINT64 gAllZero = =3D 0; =20 EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol; EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol; +EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; =20 =20 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlug= Request =3D { @@ -284,6 +285,14 @@ PciBusDriverBindingStart ( ); } =20 =20 + if (mIoMmuProtocol =3D=3D NULL) { + gBS->LocateProtocol ( + &gEdkiiIoMmuProtocolGuid, + NULL, + (VOID **) &mIoMmuProtocol + ); + } + if (PcdGetBool (PcdPciDisableBusEnumeration)) { gFullEnumeration =3D FALSE; } else { diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 39ba8b9..3bcc134 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -32,6 +32,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include #include #include +#include =20 #include #include diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bu= s/Pci/PciBusDxe/PciBusDxe.inf index a3ab11f..5da094f 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -95,6 +95,7 @@ gEfiPciRootBridgeIoProtocolGuid ## TO_START gEfiIncompatiblePciDeviceSupportProtocolGuid ## SOMETIMES_CONSUMES gEfiLoadFile2ProtocolGuid ## SOMETIMES_PRODUCES + gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES =20 [FeaturePcd] gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport ## CON= SUMES diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/= PciBusDxe/PciIo.c index f72598d..3b3b53a 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -14,6 +14,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. =20 #include "PciBus.h" =20 +extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; + // // Pci Io Protocol Interface // @@ -965,8 +967,10 @@ PciIoMap ( OUT VOID **Mapping ) { - EFI_STATUS Status; - PCI_IO_DEVICE *PciIoDevice; + EFI_STATUS Status; + PCI_IO_DEVICE *PciIoDevice; + UINT64 IoMmuAttribute; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION RootBridgeIoOperation; =20 PciIoDevice =3D PCI_IO_DEVICE_FROM_PCI_IO_THIS (This); =20 @@ -978,13 +982,14 @@ PciIoMap ( return EFI_INVALID_PARAMETER; } =20 + RootBridgeIoOperation =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)Ope= ration; if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) = !=3D 0) { - Operation =3D (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + EfiPciOpera= tionBusMasterRead64); + RootBridgeIoOperation =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(= Operation + EfiPciOperationBusMasterRead64); } =20 Status =3D PciIoDevice->PciRootBridgeIo->Map ( PciIoDevice->PciRootBridgeIo, - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL= _OPERATION) Operation, + RootBridgeIoOperation, HostAddress, NumberOfBytes, DeviceAddress, @@ -999,6 +1004,31 @@ PciIoMap ( ); } =20 + if (mIoMmuProtocol !=3D NULL) { + if (!EFI_ERROR (Status)) { + switch (Operation) { + case EfiPciIoOperationBusMasterRead: + IoMmuAttribute =3D EDKII_IOMMU_ACCESS_READ; + break; + case EfiPciIoOperationBusMasterWrite: + IoMmuAttribute =3D EDKII_IOMMU_ACCESS_WRITE; + break; + case EfiPciIoOperationBusMasterCommonBuffer: + IoMmuAttribute =3D EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WR= ITE; + break; + default: + ASSERT(FALSE); + return EFI_INVALID_PARAMETER; + } + mIoMmuProtocol->SetAttribute ( + mIoMmuProtocol, + PciIoDevice->Handle, + *Mapping, + IoMmuAttribute + ); + } + } + return Status; } =20 @@ -1024,6 +1054,15 @@ PciIoUnmap ( =20 PciIoDevice =3D PCI_IO_DEVICE_FROM_PCI_IO_THIS (This); =20 + if (mIoMmuProtocol !=3D NULL) { + mIoMmuProtocol->SetAttribute ( + mIoMmuProtocol, + PciIoDevice->Handle, + Mapping, + 0 + ); + } + Status =3D PciIoDevice->PciRootBridgeIo->Unmap ( PciIoDevice->PciRootBridgeIo, Mapping --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel