Add ACPI tables for Cadence CSP platform configured with a single
Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford <stelford@cadence.com>
---
CadencePkg/AcpiTables/AcpiTables.inf | 49 +++++
CadencePkg/AcpiTables/CspPlatform.h | 46 +++++
CadencePkg/AcpiTables/Dsdt.asl | 338 +++++++++++++++++++++++++++++++++++
CadencePkg/AcpiTables/Fadt.aslc | 87 +++++++++
CadencePkg/AcpiTables/Gtdt.aslc | 80 +++++++++
CadencePkg/AcpiTables/Madt.aslc | 71 ++++++++
CadencePkg/AcpiTables/Mcfg.aslc | 76 ++++++++
CadencePkg/AcpiTables/Spcr.aslc | 89 +++++++++
8 files changed, 836 insertions(+)
create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf
create mode 100644 CadencePkg/AcpiTables/CspPlatform.h
create mode 100644 CadencePkg/AcpiTables/Dsdt.asl
create mode 100644 CadencePkg/AcpiTables/Fadt.aslc
create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc
create mode 100644 CadencePkg/AcpiTables/Madt.aslc
create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc
create mode 100644 CadencePkg/AcpiTables/Spcr.aslc
diff --git a/CadencePkg/AcpiTables/AcpiTables.inf b/CadencePkg/AcpiTables/AcpiTables.inf
new file mode 100644
index 0000000..7c18cb4
--- /dev/null
+++ b/CadencePkg/AcpiTables/AcpiTables.inf
@@ -0,0 +1,49 @@
+## @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CspAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt.asl
+ Spcr.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Mcfg.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ CadencePkg/CadenceCspPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
diff --git a/CadencePkg/AcpiTables/CspPlatform.h b/CadencePkg/AcpiTables/CspPlatform.h
new file mode 100644
index 0000000..d3afe9e
--- /dev/null
+++ b/CadencePkg/AcpiTables/CspPlatform.h
@@ -0,0 +1,46 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*
+**/
+
+
+#ifndef _CSP_PLATFORM_H_
+#define _CSP_PLATFORM_H_
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_CSP_OEM_ID 'C','D','N','S',' ',' ' // OEMID 6 bytes long
+#define EFI_ACPI_CSP_OEM_TABLE_ID SIGNATURE_64('C','S','P',' ',' ',' ',' ',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_CSP_OEM_REVISION 0x00000002
+#define EFI_ACPI_CSP_CREATOR_ID SIGNATURE_32('C','D','N','S')
+#define EFI_ACPI_CSP_CREATOR_REVISION 0x00000001
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { EFI_ACPI_CSP_OEM_ID }, /* UINT8 OemId[6] */ \
+ EFI_ACPI_CSP_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_CSP_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_CSP_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_CSP_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#endif
diff --git a/CadencePkg/AcpiTables/Dsdt.asl b/CadencePkg/AcpiTables/Dsdt.asl
new file mode 100644
index 0000000..88c4ab0
--- /dev/null
+++ b/CadencePkg/AcpiTables/Dsdt.asl
@@ -0,0 +1,338 @@
+/*
+* Copyright (c) 2013, Al Stone <al.stone@linaro.org>
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*
+* NB: This License is also known as the "BSD 2-Clause License".
+*
+*
+*
+*/
+
+DefinitionBlock (
+ "dsdt.aml", // output filename
+ "DSDT", // table signature
+ 2, // DSDT compliance revision
+ "CDNS", // OEM ID
+ "CDNSCSP0", // table ID
+ 0x00000001) // OEM revision
+{
+ Scope (\_SB)
+ {
+ Method (_OSC, 4, NotSerialized)
+ {
+ /* Platform-Wide OSPM Capabilities */
+ If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
+ {
+ /* APEI support unconditionally */
+ Return (Arg3)
+ } Else {
+ CreateDWordField (Arg3, Zero, CDW1)
+ /* Set invalid UUID error bit */
+ Or (CDW1, 0x04, CDW1)
+ Return (Arg3)
+ }
+ }
+
+ //
+ // One Emulated aarch64 CPU with 1 core
+ //
+ Device(CPU0) { // Cluster 0, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ }
+ // Cadence UART
+ Device(COM0) {
+ Name(_HID, "CDNS0001")
+ Name(_UID, 0)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xFD000000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x20 }
+ })
+ }
+
+ //Legacy IRQs
+ Name (PR04, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF, Zero, LNKA, Zero
+ },
+ Package (0x04)
+ {
+ 0xFFFF, Zero, LNKB, Zero
+ },
+ Package (0x04)
+ {
+ 0xFFFF, Zero, LNKC, Zero
+ },
+ Package (0x04)
+ {
+ 0xFFFF, Zero, LNKD, Zero
+ }
+ })
+ Device (LNKA)
+ {
+ Name (_HID, Eisaid ("PNP0C0F"))
+ Name (_UID, 1)
+ Name(_PRS, ResourceTemplate(){
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
+ })
+ Method(_DIS) {}
+ Method(_CRS) { Return (_PRS) }
+ Method(_SRS, 1) {}
+ }
+ Device (LNKB)
+ {
+ Name (_HID, Eisaid ("PNP0C0F"))
+ Name (_UID, 1)
+ Name(_PRS, ResourceTemplate(){
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
+ })
+ Method(_DIS) {}
+ Method(_CRS) { Return (_PRS) }
+ Method(_SRS, 1) {}
+ }
+ Device (LNKC)
+ {
+ Name (_HID, Eisaid ("PNP0C0F"))
+ Name (_UID, 1)
+ Name(_PRS, ResourceTemplate(){
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
+ })
+ Method(_DIS) {}
+ Method(_CRS) { Return (_PRS) }
+ Method(_SRS, 1) {}
+ }
+ Device (LNKD)
+ {
+ Name (_HID, Eisaid ("PNP0C0F"))
+ Name (_UID, 1)
+ Name(_PRS, ResourceTemplate(){
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
+ })
+ Method(_DIS) {}
+ Method(_CRS) { Return (_PRS) }
+ Method(_SRS, 1) {}
+ }
+
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08")) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03")) // _CID: Compatible ID
+ Name (_SEG, 0x00) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name(_ADR,Zero)
+ NAME(_CCA,0) // Cache Coherent Architecture = FALSE
+ // Name(_CBA,0x50000000)
+
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+ Method (_OSC, 4, Serialized) // _OSC: Operating System Capabilities
+ {
+ Store (Arg3, Local0)
+ CreateDWordField (Local0, Zero, CDW1)
+ CreateDWordField (Local0, 0x04, CDW2)
+ CreateDWordField (Local0, 0x08, CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return (Local0)
+ }
+
+
+ Name (_UID, Zero) // _UID: Unique ID
+ Device (RP01)
+ {
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ OperationRegion (PXCS, PCI_Config, Zero, 0x0380)
+ Field (PXCS, AnyAcc, NoLock, Preserve)
+ {
+ VDID, 32,
+ Offset (0x19),
+ SCBN, 8,
+ Offset (0x50),
+ L0SE, 1,
+ , 3,
+ LDIS, 1,
+ Offset (0x51),
+ Offset (0x52),
+ , 13,
+ LASX, 1,
+ Offset (0x54),
+ , 6,
+ HPCE, 1,
+ Offset (0x5A),
+ ABPX, 1,
+ , 2,
+ PDCX, 1,
+ , 2,
+ PDSX, 1,
+ Offset (0x5B),
+ Offset (0x60),
+ Offset (0x62),
+ PSPX, 1,
+ PMEP, 1,
+ Offset (0xA4),
+ D3HT, 2,
+ Offset (0xD8),
+ , 30,
+ HPEX, 1,
+ PMEX, 1,
+ Offset (0xE2),
+ , 2,
+ L23E, 1,
+ L23R, 1,
+ Offset (0x324),
+ , 3,
+ LEDM, 1
+ }
+
+ Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0xDC),
+ , 30,
+ HPSX, 1,
+ PMSX, 1
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (LTRV, Package (0x04)
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+
+ Name (OPTS, Zero)
+
+ Name (RPAV, Zero)
+
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ If (LAnd (LEqual (Arg0, 0x02), LEqual (Arg1, One)))
+ {
+ Store (One, RPAV)
+ }
+ }
+
+ Method (HPME, 0, Serialized)
+ {
+ If (LOr (PSPX, PMEP))
+ {
+ Store (PMEX, Local1)
+ Store (Zero, PMEX)
+ Sleep (0x32)
+ Store (One, PSPX)
+ Sleep (0x32)
+ If (PSPX)
+ {
+ Store (One, PSPX)
+ Sleep (0x32)
+ }
+ Store (Local1, PMEX)
+ }
+ If (PMSX)
+ {
+ Store (0xC8, Local0)
+ While (Local0)
+ {
+ Store (One, PMSX)
+ If (PMSX)
+ {
+ Decrement (Local0)
+ }
+ Else
+ {
+ Store (Zero, Local0)
+ }
+ }
+ }
+ }
+ }
+ Name(_PRT, Package()
+ {
+ Package(){0x0000ffff, 0, LNKA, 0}, // Slot 1, INTA
+ Package(){0x0000ffff, 1, LNKB, 0}, // Slot 1, INTB
+ Package(){0x0000ffff, 2, LNKC, 0}, // Slot 1, INTC
+ Package(){0x0000ffff, 3, LNKD, 0}, // Slot 1, INTD
+ })
+ Method (_CRS, 0, Serialized)
+ {
+ Name (PRT0, ResourceTemplate ()
+ {
+ /* bus number is from 0 - 1f */
+ WordBusNumber (ResourceConsumer, MinFixed, MaxFixed, SubDecode,
+ 0x0000,
+ 0x0000,
+ 0x001f,
+ 0x0000,
+ 0x0020)
+ DWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000,
+ 0x42000000,
+ 0x42FFFFFF,
+ 0x00000000,
+ 0x01000000)
+ DWordIO (ResourceConsumer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000,
+ 0x43000000,
+ 0x43FFFFFF,
+ 0x00000000,
+ 0x01000000)
+ })
+ Return (PRT0)
+ }
+ }
+
+ // Device(COM0) {
+ // Name(_HID, "ARMH0011")
+ // Name(_CID, "PL011")
+ // Name(_UID, Zero)
+
+ // Name(_CRS, ResourceTemplate() {
+ // Memory32Fixed(ReadWrite, 0x1c090000, 0x1000)
+ // Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x25 }
+ // })
+ // }
+ }
+}
diff --git a/CadencePkg/AcpiTables/Fadt.aslc b/CadencePkg/AcpiTables/Fadt.aslc
new file mode 100644
index 0000000..2035884
--- /dev/null
+++ b/CadencePkg/AcpiTables/Fadt.aslc
@@ -0,0 +1,87 @@
+/** @file
+* Fixed ACPI Description Table (FADT)
+*
+* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "CspPlatform.h"
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ 0, //EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/CadencePkg/AcpiTables/Gtdt.aslc b/CadencePkg/AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000..ddc88d6
--- /dev/null
+++ b/CadencePkg/AcpiTables/Gtdt.aslc
@@ -0,0 +1,80 @@
+/** @file
+* Generic Timer Description Table (GTDT)
+*
+* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "CspPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
+#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL 0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE GtBlock;
+ EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[0];
+ EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[0];
+ } GENERIC_TIMER_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+ GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
+ {
+ ARM_ACPI_HEADER(
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ GENERIC_TIMER_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 CntReadBasePhysicalAddress
+ 0, // UINT32 PlatformTimerCount
+ sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+ }
+ };
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/CadencePkg/AcpiTables/Madt.aslc b/CadencePkg/AcpiTables/Madt.aslc
new file mode 100644
index 0000000..68903e0
--- /dev/null
+++ b/CadencePkg/AcpiTables/Madt.aslc
@@ -0,0 +1,71 @@
+/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.
+* Copyright (c) 2016 Linaro Ltd. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "CspPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi61.h>
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[1];
+ EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_1_GICR_STRUCTURE Gicr;
+} FVP_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ FVP_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ //
+ // MADT specific fields
+ //
+ 0, // LocalApicAddress
+ 0, // Flags
+ },
+ {
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
+ 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, 0,
+ 0, 0, 0x19, 0, 0),
+ },
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3),
+ /* GIC Redistributor */
+ {
+ EFI_ACPI_6_1_GICR, // UINT8 Type
+ sizeof(EFI_ACPI_6_1_GICR_STRUCTURE), // UINT8 Length
+ EFI_ACPI_RESERVED_WORD, // UINT16 Reserved
+ FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress
+ 0x00200000, // UINT32 DiscoveryRangeLength
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/CadencePkg/AcpiTables/Mcfg.aslc b/CadencePkg/AcpiTables/Mcfg.aslc
new file mode 100644
index 0000000..483258f
--- /dev/null
+++ b/CadencePkg/AcpiTables/Mcfg.aslc
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ * Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * Yi Li - yi.li@linaro.org
+*/
+#include "CspPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define ACPI_5_0_MCFG_VERSION 0x1
+
+#pragma pack(1)
+typedef struct
+{
+ UINT64 ullBaseAddress;
+ UINT16 usSegGroupNum;
+ UINT8 ucStartBusNum;
+ UINT8 ucEndBusNum;
+ UINT32 Reserved2;
+}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved1;
+}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+ EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+ EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[2];
+}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+ {
+ {
+ EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+ ACPI_5_0_MCFG_VERSION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_CSP_OEM_ID},
+ EFI_ACPI_CSP_OEM_TABLE_ID,
+ EFI_ACPI_CSP_OEM_REVISION,
+ EFI_ACPI_CSP_CREATOR_ID,
+ EFI_ACPI_CSP_CREATOR_REVISION
+ },
+ 0x0000000000000000, //Reserved
+ },
+ {
+
+ {
+ 0x0000000040000000, //Base Address
+ 0x0000, //Segment Group Number
+ 0x0, //Start Bus Number
+ 0x1f, //End Bus Number
+ 0x00000000, //Reserved
+ },
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/CadencePkg/AcpiTables/Spcr.aslc b/CadencePkg/AcpiTables/Spcr.aslc
new file mode 100644
index 0000000..6ca20e8
--- /dev/null
+++ b/CadencePkg/AcpiTables/Spcr.aslc
@@ -0,0 +1,89 @@
+/** @file
+* SPCR Table
+*
+* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Ltd. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "CspPlatform.h"
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+/**
+ * References:
+ * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015
+ **/
+
+
+///
+/// SPCR Flow Control
+///
+#define SPCR_FLOW_CONTROL_NONE 0
+
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
+ // UINT8 InterfaceType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+ // UINT8 Reserved1[3];
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ ARM_GAS32 (0xFD000000),
+ // UINT8 InterruptType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+ // UINT8 Irq;
+ 0, // Not used on ARM
+ // UINT32 GlobalSystemInterrupt;
+ 0x25,
+ // UINT8 BaudRate;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+ // UINT8 Parity;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+ // UINT8 StopBits;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+ // UINT8 FlowControl;
+ SPCR_FLOW_CONTROL_NONE,
+ // UINT8 TerminalType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+ // UINT8 Reserved2;
+ EFI_ACPI_RESERVED_BYTE,
+ // UINT16 PciDeviceId;
+ 0xFFFF,
+ // UINT16 PciVendorId;
+ 0xFFFF,
+ // UINT8 PciBusNumber;
+ 0x00,
+ // UINT8 PciDeviceNumber;
+ 0x00,
+ // UINT8 PciFunctionNumber;
+ 0x00,
+ // UINT32 PciFlags;
+ 0x00000000,
+ // UINT8 PciSegment;
+ 0x00,
+ // UINT32 Reserved3;
+ EFI_ACPI_RESERVED_DWORD
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;
--
2.2.2
_______________________________________________
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edk2-devel@lists.01.org
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On 5 June 2017 at 10:50, Scott Telford <stelford@cadence.com> wrote:
> Add ACPI tables for Cadence CSP platform configured with a single
> Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Scott Telford <stelford@cadence.com>
> ---
> CadencePkg/AcpiTables/AcpiTables.inf | 49 +++++
> CadencePkg/AcpiTables/CspPlatform.h | 46 +++++
> CadencePkg/AcpiTables/Dsdt.asl | 338 +++++++++++++++++++++++++++++++++++
> CadencePkg/AcpiTables/Fadt.aslc | 87 +++++++++
> CadencePkg/AcpiTables/Gtdt.aslc | 80 +++++++++
> CadencePkg/AcpiTables/Madt.aslc | 71 ++++++++
> CadencePkg/AcpiTables/Mcfg.aslc | 76 ++++++++
> CadencePkg/AcpiTables/Spcr.aslc | 89 +++++++++
> 8 files changed, 836 insertions(+)
> create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf
> create mode 100644 CadencePkg/AcpiTables/CspPlatform.h
> create mode 100644 CadencePkg/AcpiTables/Dsdt.asl
> create mode 100644 CadencePkg/AcpiTables/Fadt.aslc
> create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc
> create mode 100644 CadencePkg/AcpiTables/Madt.aslc
> create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc
> create mode 100644 CadencePkg/AcpiTables/Spcr.aslc
>
> diff --git a/CadencePkg/AcpiTables/AcpiTables.inf b/CadencePkg/AcpiTables/AcpiTables.inf
> new file mode 100644
> index 0000000..7c18cb4
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/AcpiTables.inf
> @@ -0,0 +1,49 @@
> +## @file
> +#
> +# ACPI table data and ASL sources required to boot the platform.
> +#
> +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = CspAcpiTables
> + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + Dsdt.asl
> + Spcr.aslc
> + Fadt.aslc
> + Gtdt.aslc
> + Madt.aslc
> + Mcfg.aslc
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + CadencePkg/CadenceCspPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> +
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
> diff --git a/CadencePkg/AcpiTables/CspPlatform.h b/CadencePkg/AcpiTables/CspPlatform.h
> new file mode 100644
> index 0000000..d3afe9e
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/CspPlatform.h
> @@ -0,0 +1,46 @@
> +/** @file
> +*
> +* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> +* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2015, Linaro Limited. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +*
> +**/
> +
> +
> +#ifndef _CSP_PLATFORM_H_
> +#define _CSP_PLATFORM_H_
> +
> +//
> +// ACPI table information used to initialize tables.
> +//
> +#define EFI_ACPI_CSP_OEM_ID 'C','D','N','S',' ',' ' // OEMID 6 bytes long
> +#define EFI_ACPI_CSP_OEM_TABLE_ID SIGNATURE_64('C','S','P',' ',' ',' ',' ',' ') // OEM table id 8 bytes long
> +#define EFI_ACPI_CSP_OEM_REVISION 0x00000002
> +#define EFI_ACPI_CSP_CREATOR_ID SIGNATURE_32('C','D','N','S')
> +#define EFI_ACPI_CSP_CREATOR_REVISION 0x00000001
> +
> +// A macro to initialise the common header part of EFI ACPI tables as defined by
> +// EFI_ACPI_DESCRIPTION_HEADER structure.
> +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
> + Signature, /* UINT32 Signature */ \
> + sizeof (Type), /* UINT32 Length */ \
> + Revision, /* UINT8 Revision */ \
> + 0, /* UINT8 Checksum */ \
> + { EFI_ACPI_CSP_OEM_ID }, /* UINT8 OemId[6] */ \
> + EFI_ACPI_CSP_OEM_TABLE_ID, /* UINT64 OemTableId */ \
> + EFI_ACPI_CSP_OEM_REVISION, /* UINT32 OemRevision */ \
> + EFI_ACPI_CSP_CREATOR_ID, /* UINT32 CreatorId */ \
> + EFI_ACPI_CSP_CREATOR_REVISION /* UINT32 CreatorRevision */ \
> + }
> +
> +#endif
> diff --git a/CadencePkg/AcpiTables/Dsdt.asl b/CadencePkg/AcpiTables/Dsdt.asl
> new file mode 100644
> index 0000000..88c4ab0
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Dsdt.asl
> @@ -0,0 +1,338 @@
> +/*
> +* Copyright (c) 2013, Al Stone <al.stone@linaro.org>
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +* All rights reserved.
> +*
> +* Redistribution and use in source and binary forms, with or without
> +* modification, are permitted provided that the following conditions
> +* are met:
> +*
> +* 1. Redistributions of source code must retain the above copyright
> +* notice, this list of conditions and the following disclaimer.
> +*
> +* 2. Redistributions in binary form must reproduce the above copyright
> +* notice, this list of conditions and the following disclaimer in the
> +* documentation and/or other materials provided with the distribution.
> +*
> +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> +* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
> +* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
> +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
> +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
> +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> +*
> +*
> +* NB: This License is also known as the "BSD 2-Clause License".
> +*
> +*
> +*
> +*/
> +
> +DefinitionBlock (
> + "dsdt.aml", // output filename
> + "DSDT", // table signature
> + 2, // DSDT compliance revision
> + "CDNS", // OEM ID
> + "CDNSCSP0", // table ID
> + 0x00000001) // OEM revision
> +{
> + Scope (\_SB)
> + {
> + Method (_OSC, 4, NotSerialized)
> + {
> + /* Platform-Wide OSPM Capabilities */
> + If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
> + {
> + /* APEI support unconditionally */
> + Return (Arg3)
> + } Else {
> + CreateDWordField (Arg3, Zero, CDW1)
> + /* Set invalid UUID error bit */
> + Or (CDW1, 0x04, CDW1)
> + Return (Arg3)
> + }
> + }
> +
> + //
> + // One Emulated aarch64 CPU with 1 core
> + //
> + Device(CPU0) { // Cluster 0, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 0)
> + }
> + // Cadence UART
> + Device(COM0) {
> + Name(_HID, "CDNS0001")
> + Name(_UID, 0)
> + Name(_CRS, ResourceTemplate() {
> + Memory32Fixed(ReadWrite, 0xFD000000, 0x1000)
You can use a FixedPcdGet() here for the base address.
> + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x20 }
> + })
> + }
> +
> + //Legacy IRQs
> + Name (PR04, Package (0x04)
> + {
> + Package (0x04)
> + {
> + 0xFFFF, Zero, LNKA, Zero
> + },
> + Package (0x04)
> + {
> + 0xFFFF, Zero, LNKB, Zero
> + },
> + Package (0x04)
> + {
> + 0xFFFF, Zero, LNKC, Zero
> + },
> + Package (0x04)
> + {
> + 0xFFFF, Zero, LNKD, Zero
> + }
> + })
What is the point of PR04? The _PRT below refers to the LNKA/B/C/D
devices directly.
> + Device (LNKA)
> + {
> + Name (_HID, Eisaid ("PNP0C0F"))
> + Name (_UID, 1)
> + Name(_PRS, ResourceTemplate(){
> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
> + })
> + Method(_DIS) {}
> + Method(_CRS) { Return (_PRS) }
> + Method(_SRS, 1) {}
> + }
> + Device (LNKB)
> + {
> + Name (_HID, Eisaid ("PNP0C0F"))
> + Name (_UID, 1)
> + Name(_PRS, ResourceTemplate(){
> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
> + })
> + Method(_DIS) {}
> + Method(_CRS) { Return (_PRS) }
> + Method(_SRS, 1) {}
> + }
> + Device (LNKC)
> + {
> + Name (_HID, Eisaid ("PNP0C0F"))
> + Name (_UID, 1)
> + Name(_PRS, ResourceTemplate(){
> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
> + })
> + Method(_DIS) {}
> + Method(_CRS) { Return (_PRS) }
> + Method(_SRS, 1) {}
> + }
> + Device (LNKD)
> + {
> + Name (_HID, Eisaid ("PNP0C0F"))
> + Name (_UID, 1)
> + Name(_PRS, ResourceTemplate(){
> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
> + })
> + Method(_DIS) {}
> + Method(_CRS) { Return (_PRS) }
> + Method(_SRS, 1) {}
> + }
> +
This looks like a very complicated way (combined with the _PRT below)
to route all legacy interrupts to GSIV 46. You can fold this into _PRT
instead AFAIK
> + Device (PCI0)
> + {
> + Name (_HID, EisaId ("PNP0A08")) // _HID: Hardware ID
> + Name (_CID, EisaId ("PNP0A03")) // _CID: Compatible ID
> + Name (_SEG, 0x00) // _SEG: PCI Segment
> + Name (_BBN, 0x00) // _BBN: BIOS Bus Number
> + Name(_ADR,Zero)
> + NAME(_CCA,0) // Cache Coherent Architecture = FALSE
> + // Name(_CBA,0x50000000)
Please remove if it is unused.
> +
> + //
> + // OS Control Handoff
> + //
> + Name(SUPP, Zero) // PCI _OSC Support Field value
> + Name(CTRL, Zero) // PCI _OSC Control Field value
> + Method (_OSC, 4, Serialized) // _OSC: Operating System Capabilities
> + {
> + Store (Arg3, Local0)
> + CreateDWordField (Local0, Zero, CDW1)
> + CreateDWordField (Local0, 0x04, CDW2)
> + CreateDWordField (Local0, 0x08, CDW3)
> + // Save Capabilities DWord2 & 3
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> + // Never allow SHPC (no SHPC controller in this system)
> + And(CTRL,0x1D,CTRL)
> + If(LNotEqual(Arg1,One)) { // Unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> + // Update DWORD3 in the buffer
> + Store(CTRL,CDW3)
> + Return (Local0)
> + }
> +
> +
> + Name (_UID, Zero) // _UID: Unique ID
> + Device (RP01)
> + {
> + Name (_ADR, 0x001C0000) // _ADR: Address
> + OperationRegion (PXCS, PCI_Config, Zero, 0x0380)
> + Field (PXCS, AnyAcc, NoLock, Preserve)
> + {
> + VDID, 32,
> + Offset (0x19),
> + SCBN, 8,
> + Offset (0x50),
> + L0SE, 1,
> + , 3,
> + LDIS, 1,
> + Offset (0x51),
> + Offset (0x52),
> + , 13,
> + LASX, 1,
> + Offset (0x54),
> + , 6,
> + HPCE, 1,
> + Offset (0x5A),
> + ABPX, 1,
> + , 2,
> + PDCX, 1,
> + , 2,
> + PDSX, 1,
> + Offset (0x5B),
> + Offset (0x60),
> + Offset (0x62),
> + PSPX, 1,
> + PMEP, 1,
> + Offset (0xA4),
> + D3HT, 2,
> + Offset (0xD8),
> + , 30,
> + HPEX, 1,
> + PMEX, 1,
> + Offset (0xE2),
> + , 2,
> + L23E, 1,
> + L23R, 1,
> + Offset (0x324),
> + , 3,
> + LEDM, 1
> + }
> +
> + Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
> + {
> + Offset (0xDC),
> + , 30,
> + HPSX, 1,
> + PMSX, 1
> + }
> +
> + Method (_STA, 0, NotSerialized) // _STA: Status
> + {
> + Return (0x0F)
> + }
> +
> + Name (LTRV, Package (0x04)
> + {
> + Zero,
> + Zero,
> + Zero,
> + Zero
> + })
> +
> + Name (OPTS, Zero)
> +
> + Name (RPAV, Zero)
> +
> + Method (_REG, 2, NotSerialized) // _REG: Region Availability
> + {
> + If (LAnd (LEqual (Arg0, 0x02), LEqual (Arg1, One)))
> + {
> + Store (One, RPAV)
> + }
> + }
> +
> + Method (HPME, 0, Serialized)
> + {
> + If (LOr (PSPX, PMEP))
> + {
> + Store (PMEX, Local1)
> + Store (Zero, PMEX)
> + Sleep (0x32)
> + Store (One, PSPX)
> + Sleep (0x32)
> + If (PSPX)
> + {
> + Store (One, PSPX)
> + Sleep (0x32)
> + }
> + Store (Local1, PMEX)
> + }
> + If (PMSX)
> + {
> + Store (0xC8, Local0)
> + While (Local0)
> + {
> + Store (One, PMSX)
> + If (PMSX)
> + {
> + Decrement (Local0)
> + }
> + Else
> + {
> + Store (Zero, Local0)
> + }
> + }
> + }
> + }
> + }
> + Name(_PRT, Package()
> + {
> + Package(){0x0000ffff, 0, LNKA, 0}, // Slot 1, INTA
> + Package(){0x0000ffff, 1, LNKB, 0}, // Slot 1, INTB
> + Package(){0x0000ffff, 2, LNKC, 0}, // Slot 1, INTC
> + Package(){0x0000ffff, 3, LNKD, 0}, // Slot 1, INTD
> + })
> + Method (_CRS, 0, Serialized)
> + {
> + Name (PRT0, ResourceTemplate ()
> + {
> + /* bus number is from 0 - 1f */
> + WordBusNumber (ResourceConsumer, MinFixed, MaxFixed, SubDecode,
> + 0x0000,
> + 0x0000,
> + 0x001f,
> + 0x0000,
> + 0x0020)
> + DWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> + 0x00000000,
> + 0x42000000,
> + 0x42FFFFFF,
> + 0x00000000,
> + 0x01000000)
> + DWordIO (ResourceConsumer, MinFixed, MaxFixed, PosDecode, EntireRange,
> + 0x00000000,
> + 0x43000000,
> + 0x43FFFFFF,
> + 0x00000000,
> + 0x01000000)
OK, so the MMIO32 and IO regions are in fact contiguous, but the
MMIO64 region is missing again.
> + })
> + Return (PRT0)
> + }
> + }
> +
> + // Device(COM0) {
> + // Name(_HID, "ARMH0011")
> + // Name(_CID, "PL011")
> + // Name(_UID, Zero)
> +
> + // Name(_CRS, ResourceTemplate() {
> + // Memory32Fixed(ReadWrite, 0x1c090000, 0x1000)
> + // Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x25 }
> + // })
> + // }
Please remove this entire node.
> + }
> +}
> diff --git a/CadencePkg/AcpiTables/Fadt.aslc b/CadencePkg/AcpiTables/Fadt.aslc
> new file mode 100644
> index 0000000..2035884
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Fadt.aslc
> @@ -0,0 +1,87 @@
> +/** @file
> +* Fixed ACPI Description Table (FADT)
> +*
> +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include "CspPlatform.h"
> +#include <Library/AcpiLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
> + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
> + ),
> + 0, // UINT32 FirmwareCtrl
> + 0, // UINT32 Dsdt
> + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
> + EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
> + 0, // UINT16 SciInt
> + 0, // UINT32 SmiCmd
> + 0, // UINT8 AcpiEnable
> + 0, // UINT8 AcpiDisable
> + 0, // UINT8 S4BiosReq
> + 0, // UINT8 PstateCnt
> + 0, // UINT32 Pm1aEvtBlk
> + 0, // UINT32 Pm1bEvtBlk
> + 0, // UINT32 Pm1aCntBlk
> + 0, // UINT32 Pm1bCntBlk
> + 0, // UINT32 Pm2CntBlk
> + 0, // UINT32 PmTmrBlk
> + 0, // UINT32 Gpe0Blk
> + 0, // UINT32 Gpe1Blk
> + 0, // UINT8 Pm1EvtLen
> + 0, // UINT8 Pm1CntLen
> + 0, // UINT8 Pm2CntLen
> + 0, // UINT8 PmTmrLen
> + 0, // UINT8 Gpe0BlkLen
> + 0, // UINT8 Gpe1BlkLen
> + 0, // UINT8 Gpe1Base
> + 0, // UINT8 CstCnt
> + 0, // UINT16 PLvl2Lat
> + 0, // UINT16 PLvl3Lat
> + 0, // UINT16 FlushSize
> + 0, // UINT16 FlushStride
> + 0, // UINT8 DutyOffset
> + 0, // UINT8 DutyWidth
> + 0, // UINT8 DayAlrm
> + 0, // UINT8 MonAlrm
> + 0, // UINT8 Century
> + 0, // UINT16 IaPcBootArch
> + 0, // UINT8 Reserved1
> + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
> + 0, // UINT8 ResetValue
> + 0, //EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
> + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
> + 0, // UINT64 XFirmwareCtrl
> + 0, // UINT64 XDsdt
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
> + NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Fadt;
> diff --git a/CadencePkg/AcpiTables/Gtdt.aslc b/CadencePkg/AcpiTables/Gtdt.aslc
> new file mode 100644
> index 0000000..ddc88d6
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Gtdt.aslc
> @@ -0,0 +1,80 @@
> +/** @file
> +* Generic Timer Description Table (GTDT)
> +*
> +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include "CspPlatform.h"
> +#include <Library/AcpiLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
> +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
> +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
> +#define GTDT_GLOBAL_FLAGS_LEVEL 0
> +
> +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
> +#ifdef SYSTEM_TIMER_BASE_ADDRESS
> + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
> +#else
> + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
> + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
> +#endif
> +
> +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
> +#define GTDT_TIMER_LEVEL_TRIGGERED 0
> +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
> +#define GTDT_TIMER_ACTIVE_HIGH 0
> +
> +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
> +
> +#pragma pack (1)
> +
> +typedef struct {
> + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
> + EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE GtBlock;
> + EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[0];
> + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[0];
> + } GENERIC_TIMER_DESCRIPTION_TABLE;
> +
> +#pragma pack ()
> +
> + GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
> + {
> + ARM_ACPI_HEADER(
> + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
> + GENERIC_TIMER_DESCRIPTION_TABLE,
> + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
> + ),
> + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
> + 0, // UINT32 Reserved
> + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
> + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
> + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
> + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
> + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 CntReadBasePhysicalAddress
> + 0, // UINT32 PlatformTimerCount
> + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
> + }
> + };
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Gtdt;
> diff --git a/CadencePkg/AcpiTables/Madt.aslc b/CadencePkg/AcpiTables/Madt.aslc
> new file mode 100644
> index 0000000..68903e0
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Madt.aslc
> @@ -0,0 +1,71 @@
> +/** @file
> +* Multiple APIC Description Table (MADT)
> +*
> +* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.
> +* Copyright (c) 2016 Linaro Ltd. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include "CspPlatform.h"
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi61.h>
> +
> +//
> +// Multiple APIC Description Table
> +//
> +#pragma pack (1)
> +
> +typedef struct {
> + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
> + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[1];
> + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
> + EFI_ACPI_6_1_GICR_STRUCTURE Gicr;
> +} FVP_MULTIPLE_APIC_DESCRIPTION_TABLE;
Please replace FVP_ with something more appropriate for your platform.
> +
> +#pragma pack ()
> +
> +FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
> + {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
> + FVP_MULTIPLE_APIC_DESCRIPTION_TABLE,
> + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
> + ),
> + //
> + // MADT specific fields
> + //
> + 0, // LocalApicAddress
> + 0, // Flags
> + },
> + {
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
> + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, 0,
> + 0, 0, 0x19, 0, 0),
> + },
> + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3),
> + /* GIC Redistributor */
> + {
> + EFI_ACPI_6_1_GICR, // UINT8 Type
> + sizeof(EFI_ACPI_6_1_GICR_STRUCTURE), // UINT8 Length
> + EFI_ACPI_RESERVED_WORD, // UINT16 Reserved
> + FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress
> + 0x00200000, // UINT32 DiscoveryRangeLength
> + }
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Madt;
> diff --git a/CadencePkg/AcpiTables/Mcfg.aslc b/CadencePkg/AcpiTables/Mcfg.aslc
> new file mode 100644
> index 0000000..483258f
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Mcfg.aslc
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright (c) 2013 Linaro Limited
> + * Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> + *
> + * All rights reserved. This program and the accompanying materials
> + * are made available under the terms of the BSD License which accompanies
> + * this distribution, and is available at
> + * http://opensource.org/licenses/bsd-license.php
> + *
> + * Contributors:
> + * Yi Li - yi.li@linaro.org
> +*/
> +#include "CspPlatform.h"
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#define ACPI_5_0_MCFG_VERSION 0x1
> +
> +#pragma pack(1)
> +typedef struct
> +{
> + UINT64 ullBaseAddress;
> + UINT16 usSegGroupNum;
> + UINT8 ucStartBusNum;
> + UINT8 ucEndBusNum;
> + UINT32 Reserved2;
> +}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
> +
Please get rid of the hungarian prefixes.
> +typedef struct
> +{
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + UINT64 Reserved1;
> +}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
> +
> +typedef struct
> +{
> + EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
> + EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[2];
> +}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
> +#pragma pack()
> +
> +EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
> +{
> + {
> + {
> + EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
> + sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
> + ACPI_5_0_MCFG_VERSION,
> + 0x00, // Checksum will be updated at runtime
> + {EFI_ACPI_CSP_OEM_ID},
> + EFI_ACPI_CSP_OEM_TABLE_ID,
> + EFI_ACPI_CSP_OEM_REVISION,
> + EFI_ACPI_CSP_CREATOR_ID,
> + EFI_ACPI_CSP_CREATOR_REVISION
> + },
> + 0x0000000000000000, //Reserved
> + },
> + {
> +
> + {
> + 0x0000000040000000, //Base Address
> + 0x0000, //Segment Group Number
> + 0x0, //Start Bus Number
> + 0x1f, //End Bus Number
> + 0x00000000, //Reserved
> + },
> + }
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Mcfg;
> diff --git a/CadencePkg/AcpiTables/Spcr.aslc b/CadencePkg/AcpiTables/Spcr.aslc
> new file mode 100644
> index 0000000..6ca20e8
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Spcr.aslc
> @@ -0,0 +1,89 @@
> +/** @file
> +* SPCR Table
> +*
> +* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Linaro Ltd. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials are licensed and made available
> +* under the terms and conditions of the BSD License which accompanies this
> +* distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include "CspPlatform.h"
> +#include <Library/AcpiLib.h>
> +#include <IndustryStandard/Acpi61.h>
> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
> +
> +/**
> + * References:
> + * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015
> + **/
> +
> +
> +///
> +/// SPCR Flow Control
> +///
> +#define SPCR_FLOW_CONTROL_NONE 0
> +
> +
> +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
> + ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
> + // UINT8 InterfaceType;
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
Please drop this table entirely if your platform has no SPCR supported UART.
> + // UINT8 Reserved1[3];
> + {
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE
> + },
> + // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
> + ARM_GAS32 (0xFD000000),
> + // UINT8 InterruptType;
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
> + // UINT8 Irq;
> + 0, // Not used on ARM
> + // UINT32 GlobalSystemInterrupt;
> + 0x25,
> + // UINT8 BaudRate;
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
> + // UINT8 Parity;
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
> + // UINT8 StopBits;
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
> + // UINT8 FlowControl;
> + SPCR_FLOW_CONTROL_NONE,
> + // UINT8 TerminalType;
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
> + // UINT8 Reserved2;
> + EFI_ACPI_RESERVED_BYTE,
> + // UINT16 PciDeviceId;
> + 0xFFFF,
> + // UINT16 PciVendorId;
> + 0xFFFF,
> + // UINT8 PciBusNumber;
> + 0x00,
> + // UINT8 PciDeviceNumber;
> + 0x00,
> + // UINT8 PciFunctionNumber;
> + 0x00,
> + // UINT32 PciFlags;
> + 0x00000000,
> + // UINT8 PciSegment;
> + 0x00,
> + // UINT32 Reserved3;
> + EFI_ACPI_RESERVED_DWORD
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Spcr;
> --
> 2.2.2
>
_______________________________________________
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On Mon, Jun 05, 2017 at 03:40:17PM +0000, Ard Biesheuvel wrote:
> On 5 June 2017 at 10:50, Scott Telford <stelford@cadence.com> wrote:
> > Add ACPI tables for Cadence CSP platform configured with a single
> > Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Scott Telford <stelford@cadence.com>
> > ---
> > CadencePkg/AcpiTables/AcpiTables.inf | 49 +++++
> > CadencePkg/AcpiTables/CspPlatform.h | 46 +++++
> > CadencePkg/AcpiTables/Dsdt.asl | 338 +++++++++++++++++++++++++++++++++++
> > CadencePkg/AcpiTables/Fadt.aslc | 87 +++++++++
> > CadencePkg/AcpiTables/Gtdt.aslc | 80 +++++++++
> > CadencePkg/AcpiTables/Madt.aslc | 71 ++++++++
> > CadencePkg/AcpiTables/Mcfg.aslc | 76 ++++++++
> > CadencePkg/AcpiTables/Spcr.aslc | 89 +++++++++
> > 8 files changed, 836 insertions(+)
> > create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf
> > create mode 100644 CadencePkg/AcpiTables/CspPlatform.h
> > create mode 100644 CadencePkg/AcpiTables/Dsdt.asl
> > create mode 100644 CadencePkg/AcpiTables/Fadt.aslc
> > create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc
> > create mode 100644 CadencePkg/AcpiTables/Madt.aslc
> > create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc
> > create mode 100644 CadencePkg/AcpiTables/Spcr.aslc
> >
> > diff --git a/CadencePkg/AcpiTables/Spcr.aslc b/CadencePkg/AcpiTables/Spcr.aslc
> > new file mode 100644
> > index 0000000..6ca20e8
> > --- /dev/null
> > +++ b/CadencePkg/AcpiTables/Spcr.aslc
> > @@ -0,0 +1,89 @@
> > +/** @file
> > +* SPCR Table
> > +*
> > +* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.
> > +* Copyright (c) 2016, Linaro Ltd. All rights reserved.
> > +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> > +*
> > +* This program and the accompanying materials are licensed and made available
> > +* under the terms and conditions of the BSD License which accompanies this
> > +* distribution. The full text of the license may be found at
> > +* http://opensource.org/licenses/bsd-license.php
> > +*
> > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#include "CspPlatform.h"
> > +#include <Library/AcpiLib.h>
> > +#include <IndustryStandard/Acpi61.h>
> > +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
> > +
> > +/**
> > + * References:
> > + * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015
> > + **/
> > +
> > +
> > +///
> > +/// SPCR Flow Control
> > +///
> > +#define SPCR_FLOW_CONTROL_NONE 0
> > +
> > +
> > +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
> > + ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
> > + // UINT8 InterfaceType;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
>
> Please drop this table entirely if your platform has no SPCR supported UART.
This is a very good point.
Yes, for this development, not having SPCR is probably fine.
However, if you want this Cadence UART to be usable as an operating
system boot console in ACPI systems, you need to get the serial port
type added to DBG2 (which is explicitly referenced from SPCR):
https://msdn.microsoft.com/en-us/library/windows/hardware/dn639131(v=vs.85).aspx
Is this something you would be interested in doing? I could probably
dig up the required contacts if that was the case.
(You would then also need to add some matching code in
linux/drivers/tty/serial/xilinx_uartps.c, to get it autodetected by
Linux.)
/
Leif
> > + // UINT8 Reserved1[3];
> > + {
> > + EFI_ACPI_RESERVED_BYTE,
> > + EFI_ACPI_RESERVED_BYTE,
> > + EFI_ACPI_RESERVED_BYTE
> > + },
> > + // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
> > + ARM_GAS32 (0xFD000000),
> > + // UINT8 InterruptType;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
> > + // UINT8 Irq;
> > + 0, // Not used on ARM
> > + // UINT32 GlobalSystemInterrupt;
> > + 0x25,
> > + // UINT8 BaudRate;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
> > + // UINT8 Parity;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
> > + // UINT8 StopBits;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
> > + // UINT8 FlowControl;
> > + SPCR_FLOW_CONTROL_NONE,
> > + // UINT8 TerminalType;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
> > + // UINT8 Reserved2;
> > + EFI_ACPI_RESERVED_BYTE,
> > + // UINT16 PciDeviceId;
> > + 0xFFFF,
> > + // UINT16 PciVendorId;
> > + 0xFFFF,
> > + // UINT8 PciBusNumber;
> > + 0x00,
> > + // UINT8 PciDeviceNumber;
> > + 0x00,
> > + // UINT8 PciFunctionNumber;
> > + 0x00,
> > + // UINT32 PciFlags;
> > + 0x00000000,
> > + // UINT8 PciSegment;
> > + 0x00,
> > + // UINT32 Reserved3;
> > + EFI_ACPI_RESERVED_DWORD
> > +};
> > +
> > +//
> > +// Reference the table being generated to prevent the optimizer from removing the
> > +// data structure from the executable
> > +//
> > +VOID* CONST ReferenceAcpiTable = &Spcr;
> > --
> > 2.2.2
> >
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