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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:33 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3ybErsVok4YIVXZW/3JS8lzyQhrV2WVr16smsBeVQWA=; b=vPZhPibtoL6S58BDlXqwL200Y2Z/q/Nf3twOe1YNgKDEEbnHSfkKCG7HZCuW1evQ59 kxhgsYCqFSlOLD4AiBy0Z2Z7dhVMTQP0AR9Q5+0+jGG+wAHSx9a5PnFdpjRWE5HL+ZMW 1i0id1EZV367zEhkL8Q5IiLNhdFHOpFqY0XrTHDfY8elF2nwz0uNWtA312GM7JVEalKt OUyKzbuYuafwbhdWnvBdVNEegh2ecqi9lq2U+sDzRzGqP3x97OA2LbUtlQnuSZGKaeYS b19Uiw6znAkKxcP2FyxWQq6Rz/WSRXJuZftnS50eBRN7o7+2adKo1T+94B+OZR6I8K+I zquw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3ybErsVok4YIVXZW/3JS8lzyQhrV2WVr16smsBeVQWA=; b=G76WvTYch7kcZh4igGVQXE+n3qeBCwZAYt42RHfn4kcj1dpUquAAxGNVESBcEo1DDH 1ZNPo8qDkfSWSnl1hJ19n1MwrU63us9fwZ37oCmxw/dRz9rjxSQJnAJo/kZFoR/0kvRR YykepqYNFvw0esDUjW4/lN5D2vFL4zHrSocsoE0Z/S4pQicNoTVyYygcDiflq0v9HpkQ PMJUlqVg0ZoC+sl8rvz+mkznY0FHL/0ZojZ3Becf7traA9WxJTlYzZfO/lnukBgVW94s 3aqP9f5rVG9FwbrqlKRgh1/wRqK53LjN9uWOmdSZ1nCholliUWoj+BzwLZtvfHEUeMcf nBLw== X-Gm-Message-State: AKS2vOyhpGOCNKLxx8GWFaUv1P30BXZfxfhZTU76H1qST1F6bGgtGlL1 ef6dzLa+J6zyWvqyDt2AIA== X-Received: by 10.46.82.208 with SMTP id n77mr12876019lje.93.1499174674372; Tue, 04 Jul 2017 06:24:34 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:10 +0200 Message-Id: <1499174653-330-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 07/10] Platform/Marvell: ComPhyLib: Add missing SFI and RXAUI configuration X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Despite the fact, that SFI and RXAUI modes are present on supported feature list, their configuration was non existent and could not be executed. This patch adds the missing initialization sequences. Because ComPhySgmiiRFUPowerUp routine is common for SGMII, SFI and RXAUI, rename it and reuse for those modes. Also add an option to use XFI mode (SFI @ 5156 MHz). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 464 +++++++++++++++++++= +++- Platform/Marvell/Library/ComPhyLib/ComPhyLib.c | 6 +- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 54 ++- 3 files changed, 515 insertions(+), 9 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyCp110.c index 6f26bc4..329bbe8 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -1179,7 +1179,7 @@ ComPhySgmiiPhyConfiguration ( =20 STATIC EFI_STATUS -ComPhySgmiiRFUPowerUp ( +ComPhyEthCommonRFUPowerUp ( IN EFI_PHYSICAL_ADDRESS SdIpAddr ) { @@ -1265,7 +1265,460 @@ ComPhySgmiiPowerUp ( =20 DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,= Rx\n")); =20 - Status =3D ComPhySgmiiRFUPowerUp (SdIpAddr); + Status =3D ComPhyEthCommonRFUPowerUp (SdIpAddr); + + return Status; +} + +STATIC +VOID +ComPhySfiRFUConfiguration ( + IN EFI_PHYSICAL_ADDRESS ComPhyAddr, + IN EFI_PHYSICAL_ADDRESS SdIpAddr +) +{ + UINT32 Mask, Data; + + MmioAndThenOr32 ( + ComPhyAddr + COMMON_PHY_CFG1_REG, + ~(COMMON_PHY_CFG1_PWR_UP_MASK | COMMON_PHY_CFG1_PIPE_SELECT_MASK= ), + COMMON_PHY_CFG1_PWR_UP_MASK + ); + + /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ + Mask =3D SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK | + SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK | + SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK | + SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK | + SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK | + SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; + Data =3D (0xe << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) | + (0xe << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET); + MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, ~Mask, Data); + + /* Release from hard reset */ + Mask =3D SD_EXTERNAL_CONFIG1_RESET_IN_MASK | + SD_EXTERNAL_CONFIG1_RESET_CORE_MASK | + SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; + Data =3D SD_EXTERNAL_CONFIG1_RESET_IN_MASK | + SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; + MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, ~Mask, Data); + + /* Wait 1ms - until band gap and ref clock are ready */ + MicroSecondDelay (1000); + MemoryFence (); +} + +STATIC +VOID +ComPhySfiPhyConfiguration ( + IN EFI_PHYSICAL_ADDRESS HpipeAddr, + IN UINT32 SfiSpeed +) +{ + UINT32 Mask, Data; + + /* Set reference clock */ + Mask =3D HPIPE_MISC_ICP_FORCE_MASK | HPIPE_MISC_REFCLK_SEL_MASK; + Data =3D (SfiSpeed =3D=3D PHY_SPEED_5_15625G) ? + (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : (0x1 << HPIPE_MISC_ICP_FORCE_OF= FSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_MISC_REG, ~Mask, Data); + + /* Power and PLL Control */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PWR_PLL_REG, + ~(HPIPE_PWR_PLL_REF_FREQ_MASK | HPIPE_PWR_PLL_PHY_MODE_MASK), + 0x1 | (0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) + ); + + /* Loopback register */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_LOOPBACK_REG, + ~HPIPE_LOOPBACK_SEL_MASK, + 0x1 << HPIPE_LOOPBACK_SEL_OFFSET + ); + + /* Rx control 1 */ + MmioOr32 ( + HpipeAddr + HPIPE_RX_CONTROL_1_REG, + HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK | HPIPE_RX_CONTROL_1_CLK8T_E= N_MASK + ); + + /* DTL Control */ + MmioOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, HPIPE_PWR_CTR_DTL_FLOOP_EN_= MASK); + + /* Transmitter/Receiver Speed Divider Force */ + if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + Mask =3D HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK | + HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK | + HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK | + HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; + Data =3D (1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) | + (1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) | + (1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) | + (1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_SPD_DIV_FORCE_REG, ~Mask, Data); + } else { + MmioOr32 (HpipeAddr + HPIPE_SPD_DIV_FORCE_REG, HPIPE_TXDIGCK_DIV_FORCE= _MASK); + } +} + +STATIC +VOID +ComPhySfiSetAnalogParameters ( + IN EFI_PHYSICAL_ADDRESS HpipeAddr, + IN EFI_PHYSICAL_ADDRESS SdIpAddr, + IN UINT32 SfiSpeed +) +{ + UINT32 Mask, Data; + + /* SERDES External Configuration 2 */ + MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_PIN_DF= E_EN_MASK); + + /* DFE Resolution control */ + MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK); + + /* Generation 1 setting_0 */ + if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + Mask =3D HPIPE_GX_SET0_TX_EMPH1_MASK; + Data =3D 0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET; + } else { + Mask =3D HPIPE_GX_SET0_TX_AMP_MASK | HPIPE_GX_SET0_TX_EMPH1_MASK; + Data =3D (0x1c << HPIPE_GX_SET0_TX_AMP_OFFSET) | (0xe << HPIPE_GX_SET0= _TX_EMPH1_OFFSET); + } + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET0_REG, ~Mask, Data); + + /* Generation 1 setting 2 */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_GX_SET2_REG, + ~HPIPE_GX_SET2_TX_EMPH0_MASK, + HPIPE_GX_SET2_TX_EMPH0_EN_MASK + ); + + /* Transmitter Slew Rate Control register */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_TX_REG1_REG, + ~(HPIPE_TX_REG1_TX_EMPH_RES_MASK | HPIPE_TX_REG1_SLC_EN_MASK), + (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) | (0x3f << HPIPE_TX_RE= G1_SLC_EN_OFFSET) + ); + + /* Impedance Calibration Control register */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_CAL_REG1_REG, + ~(HPIPE_CAL_REG_1_EXT_TXIMP_MASK | HPIPE_CAL_REG_1_EXT_TXIMP_EN_= MASK), + (0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) | HPIPE_CAL_REG_1_EXT_= TXIMP_EN_MASK + ); + + /* Generation 1 setting 5 */ + MmioAnd32 (HpipeAddr + HPIPE_G1_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK); + + /* Generation 1 setting 1 */ + if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK; + Data =3D 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET); + } else { + Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_RX_SELMUFI_MASK | + HPIPE_GX_SET1_RX_SELMUFF_MASK | + HPIPE_GX_SET1_RX_DIGCK_DIV_MASK; + Data =3D 0x2 | + (0x2 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) | + (0x1 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) | + (0x3 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET); + } + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data); + MmioOr32 (HpipeAddr + HPIPE_G1_SET1_REG, HPIPE_GX_SET1_RX_DFE_EN_MASK); + + /* DFE F3-F5 Coefficient Control */ + MmioAnd32 ( + HpipeAddr + HPIPE_DFE_F3_F5_REG, + ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK) + ); + + /* Configure Generation 1 setting 4 (DFE) */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G1_SET4_REG, + ~HPIPE_GX_SET4_DFE_RES_MASK, + 0x1 << HPIPE_GX_SET4_DFE_RES_OFFSET + ); + + /* Generation 1 setting 3 */ + MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK); + + if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + /* Force FFE (Feed Forward Equalization) to 5G */ + Mask =3D HPIPE_GX_SET3_FFE_CAP_SEL_MASK | + HPIPE_GX_SET3_FFE_RES_SEL_MASK | + HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK; + Data =3D 0xf | (0x4 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) | HPIPE_GX_SE= T3_FFE_SETTING_FORCE_MASK; + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET3_REG, ~Mask, Data); + } + + /* Configure RX training timer */ + MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~HPIPE_RX_TRAIN_= TIMER_MASK, 0x13); + + /* Enable TX train peak to peak hold */ + MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD= _MASK); + + /* Configure TX preset index */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_TX_PRESET_INDEX_REG, + ~HPIPE_TX_PRESET_INDEX_MASK, + 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET + ); + + /* Disable pattern lock lost timeout */ + MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOC= K_LOST_TIMEOUT_EN_MASK); + + /* Configure TX training pattern and TX training 16bit auto */ + MmioOr32 ( + HpipeAddr + HPIPE_TX_TRAIN_REG, + HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK | HPIPE_TX_TRAIN_PAT_SEL_MASK + ); + + /* Configure training pattern number */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_FRAME_DETECT_CTRL_0_REG, + ~HPIPE_TRAIN_PAT_NUM_MASK, + 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET + ); + + /* Configure differential manchester encoder to ethernet mode */ + MmioOr32 (HpipeAddr + HPIPE_DME_REG, HPIPE_DME_ETHERNET_MODE_MASK); + + /* Configure VDD Continuous Calibration */ + MmioOr32 (HpipeAddr + HPIPE_VDD_CAL_0_REG, HPIPE_CAL_VDD_CONT_MODE_MASK); + + /* Configure sampler gain */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_RX_SAMPLER_OS_GAIN_MASK, + 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET + ); + + /* Trigger sampler enable pulse (by toggling the bit) */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_SAMPLER_MASK, + 0x1 << HPIPE_SAMPLER_OFFSET + ); + MmioAnd32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_SAMPLER_MASK + ); + + /* VDD calibration control */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_VDD_CAL_CTRL_REG, + ~HPIPE_EXT_SELLV_RXSAMPL_MASK, + 0x1a << HPIPE_EXT_SELLV_RXSAMPL_OFFSET + ); +} + +STATIC +EFI_STATUS +ComPhySfiPowerUp ( + IN UINT32 Lane, + IN EFI_PHYSICAL_ADDRESS HpipeBase, + IN EFI_PHYSICAL_ADDRESS ComPhyBase, + IN UINT32 SfiSpeed + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS SdIpAddr =3D SD_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComP= hy\n")); + + ComPhySfiRFUConfiguration (ComPhyAddr, SdIpAddr); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n")); + + ComPhySfiPhyConfiguration (HpipeAddr, SfiSpeed); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n")); + + ComPhySfiSetAnalogParameters (HpipeAddr, SdIpAddr, SfiSpeed); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx= ,Rx\n")); + + Status =3D ComPhyEthCommonRFUPowerUp (SdIpAddr); + + return Status; +} + +STATIC +EFI_STATUS +ComPhyRxauiRFUConfiguration ( + IN UINT32 Lane, + IN EFI_PHYSICAL_ADDRESS ComPhyAddr, + IN EFI_PHYSICAL_ADDRESS SdIpAddr +) +{ + UINT32 Mask, Data; + + MmioAndThenOr32 ( + ComPhyAddr + COMMON_PHY_CFG1_REG, + ~(COMMON_PHY_CFG1_PWR_UP_MASK | COMMON_PHY_CFG1_PIPE_SELECT_MASK= ), + COMMON_PHY_CFG1_PWR_UP_MASK + ); + + switch (Lane) { + case 2: + case 4: + MmioOr32 (ComPhyAddr + COMMON_PHY_SD_CTRL1, COMMON_PHY_SD_CTRL1_RXAUI0= _MASK); + case 3: + case 5: + MmioOr32 (ComPhyAddr + COMMON_PHY_SD_CTRL1, COMMON_PHY_SD_CTRL1_RXAUI1= _MASK); + break; + default: + DEBUG ((DEBUG_ERROR, "RXAUI used on invalid lane %d\n", Lane)); + return EFI_INVALID_PARAMETER; + } + + /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ + Mask =3D SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK | + SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK | + SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK | + SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK | + SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK | + SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK | + SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; + Data =3D (0xb << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) | + (0xb << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) | + (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET); + MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, ~Mask, Data); + + /* Release from hard reset */ + Mask =3D SD_EXTERNAL_CONFIG1_RESET_IN_MASK | + SD_EXTERNAL_CONFIG1_RESET_CORE_MASK | + SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; + Data =3D SD_EXTERNAL_CONFIG1_RESET_IN_MASK | + SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; + MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, ~Mask, Data); + + /* Wait 1ms - until band gap and ref clock are ready */ + MicroSecondDelay (1000); + MemoryFence (); + + return EFI_SUCCESS; +} + +STATIC +VOID +ComPhyRxauiPhyConfiguration ( + IN EFI_PHYSICAL_ADDRESS HpipeAddr +) +{ + /* Set reference clock */ + MmioAnd32 (HpipeAddr + HPIPE_MISC_REG, ~HPIPE_MISC_REFCLK_SEL_MASK); + + /* Power and PLL Control */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PWR_PLL_REG, + ~(HPIPE_PWR_PLL_REF_FREQ_MASK | HPIPE_PWR_PLL_PHY_MODE_MASK), + 0x1 | (0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) + ); + + /* Loopback register */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_LOOPBACK_REG, + ~HPIPE_LOOPBACK_SEL_MASK, + 0x1 << HPIPE_LOOPBACK_SEL_OFFSET + ); + + /* Rx control 1 */ + MmioOr32 ( + HpipeAddr + HPIPE_RX_CONTROL_1_REG, + HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK | HPIPE_RX_CONTROL_1_CLK8T_E= N_MASK + ); + + /* DTL Control */ + MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_E= N_MASK); +} + +STATIC +VOID +ComPhyRxauiSetAnalogParameters ( + IN EFI_PHYSICAL_ADDRESS HpipeAddr, + IN EFI_PHYSICAL_ADDRESS SdIpAddr +) +{ + UINT32 Mask, Data; + + /* SERDES External Configuration 2 */ + MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_PIN_DF= E_EN_MASK); + + /* DFE Resolution control */ + MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK); + + /* Generation 1 setting_0 */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G1_SET0_REG, + ~HPIPE_GX_SET0_TX_EMPH1_MASK, + 0xe << HPIPE_GX_SET0_TX_EMPH1_OFFSET + ); + + /* Generation 1 setting 1 */ + Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_RX_DFE_EN_MASK; + Data =3D 0x1 | + (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) | + (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data); + + /* DFE F3-F5 Coefficient Control */ + MmioAnd32 ( + HpipeAddr + HPIPE_DFE_F3_F5_REG, + ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK) + ); + + /* Configure Generation 1 setting 4 (DFE) */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G1_SET4_REG, + ~HPIPE_GX_SET4_DFE_RES_MASK, + 0x1 << HPIPE_GX_SET4_DFE_RES_OFFSET + ); + + /* Generation 1 setting 3 */ + MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK); +} + +STATIC +EFI_STATUS +ComPhyRxauiPowerUp ( + IN UINT32 Lane, + IN EFI_PHYSICAL_ADDRESS HpipeBase, + IN EFI_PHYSICAL_ADDRESS ComPhyBase + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS SdIpAddr =3D SD_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComP= hy\n")); + + Status =3D ComPhyRxauiRFUConfiguration (Lane, ComPhyAddr, SdIpAddr); + if (EFI_ERROR(Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n")); + + ComPhyRxauiPhyConfiguration (HpipeAddr); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n")); + + ComPhyRxauiSetAnalogParameters (HpipeAddr, SdIpAddr); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx= ,Rx\n")); + + Status =3D ComPhyEthCommonRFUPowerUp (SdIpAddr); =20 return Status; } @@ -1372,6 +1825,13 @@ ComPhyCp110Init ( Status =3D ComPhySgmiiPowerUp(Lane, PtrComPhyMap->Speed, HpipeBaseAd= dr, ComPhyBaseAddr); break; + case PHY_TYPE_SFI: + Status =3D ComPhySfiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr, Ptr= ComPhyMap->Speed); + break; + case PHY_TYPE_RXAUI0: + case PHY_TYPE_RXAUI1: + Status =3D ComPhyRxauiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); + break; default: DEBUG((DEBUG_ERROR, "Unknown SerDes Type, skip initialize SerDes %d\= n", Lane)); diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.c index 88680fc..174f10d 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -42,7 +42,7 @@ CHAR16 * TypeStringTable [] =3D {L"unconnected", L"PCIE0"= , L"PCIE1", L"PCIE2", L"XAUI3", L"RXAUI0", L"RXAUI1", L"SFI"}; =20 CHAR16 * SpeedStringTable [] =3D {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 G= bps", - L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", + L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", L"5= .156 Gbps", L"6 Gbps", L"6.25 Gbps", L"10.31 Gbps"}; =20 CHIP_COMPHY_CONFIG ChipCfgTbl[] =3D { @@ -142,9 +142,9 @@ ParseSerdesSpeed ( { UINT32 i; UINT32 ValueTable [] =3D {0, 1250, 1500, 2500, 3000, 3125, - 5000, 6000, 6250, 10310}; + 5000, 5156, 6000, 6250, 10310}; =20 - for (i =3D 0; i < 10; i++) { + for (i =3D 0; i < PHY_SPEED_MAX; i++) { if (Value =3D=3D ValueTable[i]) { return i; } diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.h index 58f1d81..56bb991 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -80,10 +80,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define PHY_SPEED_3G 4 #define PHY_SPEED_3_125G 5 #define PHY_SPEED_5G 6 -#define PHY_SPEED_6G 7 -#define PHY_SPEED_6_25G 8 -#define PHY_SPEED_10_3125G 9 -#define PHY_SPEED_MAX 10 +#define PHY_SPEED_5_15625G 7 +#define PHY_SPEED_6G 8 +#define PHY_SPEED_6_25G 9 +#define PHY_SPEED_10_3125G 10 +#define PHY_SPEED_MAX 11 #define PHY_SPEED_INVALID 0xff =20 #define PHY_TYPE_UNCONNECTED 0 @@ -132,6 +133,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK (1 << SD_EXTERNAL_CONFIG= 0_SD_PU_TX_OFFSET) #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK (1 << SD_EXTERNAL_CONFIG= 0_HALF_BUS_MODE_OFFSET) +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK (0x1 << SD_EXTERNAL_CONF= IG0_MEDIA_MODE_OFFSET) =20 #define SD_EXTERNAL_CONFIG1_REG 0x4 #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 @@ -168,6 +171,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK (0x1 << HPIPE_KVCO_CALIB= _CTRL_MAX_PLL_OFFSET) =20 +#define HPIPE_CAL_REG1_REG 0xc +#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 +#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK (0x1f << HPIPE_CAL_REG_1= _EXT_TXIMP_OFFSET) +#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 +#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK (0x1 << HPIPE_CAL_REG_1_= EXT_TXIMP_EN_OFFSET) + #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 =20 #define HPIPE_DFE_REG0 0x01C @@ -234,6 +243,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 #define HPIPE_ISOLATE_MODE_GEN_TX_MASK (0xf << HPIPE_ISOLATE_MO= DE_GEN_TX_OFFSET) =20 +#define HPIPE_GX_SET2_REG 0xf4 +#define HPIPE_GX_SET2_TX_EMPH0_OFFSET 0 +#define HPIPE_GX_SET2_TX_EMPH0_MASK (0xf << HPIPE_GX_SET2_TX= _EMPH0_OFFSET) +#define HPIPE_GX_SET2_TX_EMPH0_EN_OFFSET 4 +#define HPIPE_GX_SET2_TX_EMPH0_EN_MASK (0x1 << HPIPE_GX_SET2_TX= _EMPH0_MASK) + #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 =20 #define HPIPE_VDD_CAL_CTRL_REG 0x114 @@ -280,6 +295,18 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. =20 #define HPIPE_PLLINTP_REG1 0x150 =20 +#define HPIPE_SPD_DIV_FORCE_REG 0x154 +#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 +#define HPIPE_TXDIGCK_DIV_FORCE_MASK (0x1 << HPIPE_TXDIGC= K_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DI= V_FORCE_RX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DI= V_FORCE_RX_SPD_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DI= V_FORCE_TX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DI= V_FORCE_TX_SPD_DIV_FORCE_OFFSET) + #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C #define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 #define HPIPE_RX_SAMPLER_OS_GAIN_MASK (0x3 << HPIPE_RX_SAMPLER= _OS_GAIN_OFFSET) @@ -292,6 +319,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 #define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_S= LC_EN_OFFSET) =20 +#define HPIPE_TX_REG1_REG 0x174 +#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 +#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX= _EMPH_RES_OFFSET) +#define HPIPE_TX_REG1_SLC_EN_OFFSET 10 +#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_S= LC_EN_OFFSET) + #define HPIPE_PWR_CTR_DTL_REG 0x184 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK (0x1 << HPIPE_PWR_CT= R_DTL_SQ_DET_EN_OFFSET) @@ -348,6 +381,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define HPIPE_PCIE_REG3 0x290 =20 #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 +#define HPIPE_RX_TRAIN_TIMER_OFFSET 0 +#define HPIPE_RX_TRAIN_TIMER_MASK (0x3ff << HPIPE_RX_TRAIN= _TIMER_OFFSET) #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK (0x1 << HPIPE_TX_TRAIN_S= TART_SQ_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 @@ -362,6 +397,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_C= HK_INIT_OFFSET) #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_C= OE_FM_PIN_PCIE3_OFFSET) +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK (0x1 << HPIPE_TX_TRAIN_1= 6BIT_AUTO_EN_OFFSET) +#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 +#define HPIPE_TX_TRAIN_PAT_SEL_MASK (0x1 << HPIPE_TX_TRAIN_P= AT_SEL_OFFSET) =20 #define HPIPE_CDR_CONTROL_REG 0x418 #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 @@ -413,6 +452,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 #define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_2= 8_PIPE4_OFFSET) =20 +#define HPIPE_G1_SET5_REG 0x538 #define HPIPE_G3_SET5_REG 0x548 #define HPIPE_GX_SET5_ICP_OFFSET 0 #define HPIPE_GX_SET5_ICP_MASK (0xf << HPIPE_GX_SET5_IC= P_OFFSET) @@ -502,6 +542,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define COMMON_SELECTOR_PHY_OFFSET 0x140 #define COMMON_SELECTOR_PIPE_OFFSET 0x144 =20 +#define COMMON_PHY_SD_CTRL1 0x148 +#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26 +#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CT= RL1_RXAUI1_OFFSET) +#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27 +#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK (0x1 << COMMON_PHY_SD_CT= RL1_RXAUI0_OFFSET) + /***** SATA registers *****/ #define SATA3_VENDOR_ADDRESS 0xA0 #define SATA3_VENDOR_ADDR_OFSSET 0 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel