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charset="utf-8" GetProcessorLocationByApicId () - Adjust InitialApicId to properly concatenate Package on AMD processor. - Clean-ups on C Coding standards. Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 49 ++++++++++++++----= ---- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 47 +++++++++++++-----= --- 2 files changed, 61 insertions(+), 35 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index 2091e5e..20371a7 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -48,7 +48,7 @@ StandardSignatureIsAuthenticAMD ( UINT32 RegEcx; UINT32 RegEdx; =20 - AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); @@ -338,7 +338,7 @@ GetInitialApicId ( AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); =20 // - // If CPUID Leaf B is supported,=20 + // If CPUID Leaf B is supported, // And CPUID.0BH:EBX[15:0] reports a non-zero value, // Then the initial 32-bit APIC ID =3D CPUID.0BH:EDX // Else the initial 8-bit APIC ID =3D CPUID.1:EBX[31:24] @@ -1013,13 +1013,14 @@ GetProcessorLocationByApicId ( UINT32 MaxCoresPerNode; UINT32 CorePerNodeMask; UINT32 ApicIdShift; + UINT32 ApicIdMask; UINTN ThreadBits; UINTN CoreBits; =20 // // Check if the processor is capable of supporting more than one logical= processor. // - AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { if (Thread !=3D NULL) { *Thread =3D 0; @@ -1042,8 +1043,8 @@ GetProcessorLocationByApicId ( // // Get max index of CPUID // - AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); - AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NU= LL); + AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, N= ULL); =20 // // If the extended topology enumeration leaf is available, it @@ -1051,7 +1052,7 @@ GetProcessorLocationByApicId ( // TopologyLeafSupported =3D FALSE; if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, 0, &ExtendedTopologyEax.Uint32, @@ -1072,7 +1073,7 @@ GetProcessorLocationByApicId ( // the SMT sub-field of x2APIC ID. // LevelType =3D ExtendedTopologyEcx.Bits.LevelType; - ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; =20 // @@ -1081,7 +1082,7 @@ GetProcessorLocationByApicId ( // SubIndex =3D 1; do { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, SubIndex, &ExtendedTopologyEax.Uint32, @@ -1103,7 +1104,7 @@ GetProcessorLocationByApicId ( // // Get logical processor count // - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); + AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL= ); MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; =20 // @@ -1114,12 +1115,17 @@ GetProcessorLocationByApicId ( // // Check for topology extensions on AMD processor // - if (StandardSignatureIsAuthenticAMD()) { + if (StandardSignatureIsAuthenticAMD ()) { if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { - AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx= .Uint32, NULL); + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEc= x.Uint32, NULL); if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { - AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopolo= gyEbx.Uint32, - &AmdProcessorTopologyEcx.Uint32, NULL); + AsmCpuid ( + CPUID_AMD_PROCESSOR_TOPOLOGY, + NULL, + &AmdProcessorTopologyEbx.Uint32, + &AmdProcessorTopologyEcx.Uint32, + NULL + ); // // Get cores per processor package // @@ -1128,7 +1134,7 @@ GetProcessorLocationByApicId ( // // Account for actual thread count (e.g., SMT disabled) // - AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddre= ssSizeEcx.Uint32, NULL); + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddr= essSizeEcx.Uint32, NULL); MaxThreadPerPackageMask =3D 1 << AmdVirPhyAddressSizeEcx.Bits.Ap= icIdCoreIdSize; ActualThreadPerPackageMask =3D 1; while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage= ) { @@ -1136,7 +1142,7 @@ GetProcessorLocationByApicId ( } =20 // - // Adjust APIC Id to report concatenation of Package|Core|Thread. + // Adjust APIC Id to report concatenation of Core|Thread. // if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { MaxCoresPerNode =3D MaxCoresPerPackage / (AmdProcessorTopology= Ecx.Bits.NodesPerProcessor + 1); @@ -1148,13 +1154,20 @@ GetProcessorLocationByApicId ( CorePerNodeMask -=3D 1; =20 ApicIdShift =3D 0; + ApicIdMask =3D ActualThreadPerPackageMask; do { ApicIdShift +=3D 1; - ActualThreadPerPackageMask <<=3D 1; - } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); + ApicIdMask <<=3D 1; + } while (ApicIdMask < MaxThreadPerPackageMask); =20 InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicI= dShift) | (InitialApicId & CorePerNodeMask); } + // + // Adjust APIC Id to report concatenation of Package|Core|Thread. + // + if ((InitialApicId & ~(MaxThreadPerPackageMask - 1)) !=3D 0) { + InitialApicId =3D (InitialApicId & (ActualThreadPerPackageMask= - 1)) | ActualThreadPerPackageMask; + } } } } @@ -1163,7 +1176,7 @@ GetProcessorLocationByApicId ( // Extract core count based on CACHE information // if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NU= LL, NULL); + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, N= ULL, NULL); if (CacheParamsEax.Uint32 !=3D 0) { MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIds= ForLogicalProcessors + 1; } diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index d5d4efa..9b286fa 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -49,7 +49,7 @@ StandardSignatureIsAuthenticAMD ( UINT32 RegEcx; UINT32 RegEdx; =20 - AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); @@ -1108,13 +1108,14 @@ GetProcessorLocationByApicId ( UINT32 MaxCoresPerNode; UINT32 CorePerNodeMask; UINT32 ApicIdShift; + UINT32 ApicIdMask; UINTN ThreadBits; UINTN CoreBits; =20 // // Check if the processor is capable of supporting more than one logical= processor. // - AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { if (Thread !=3D NULL) { *Thread =3D 0; @@ -1137,8 +1138,8 @@ GetProcessorLocationByApicId ( // // Get max index of CPUID // - AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); - AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NU= LL); + AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, N= ULL); =20 // // If the extended topology enumeration leaf is available, it @@ -1146,7 +1147,7 @@ GetProcessorLocationByApicId ( // TopologyLeafSupported =3D FALSE; if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, 0, &ExtendedTopologyEax.Uint32, @@ -1167,7 +1168,7 @@ GetProcessorLocationByApicId ( // the SMT sub-field of x2APIC ID. // LevelType =3D ExtendedTopologyEcx.Bits.LevelType; - ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; =20 // @@ -1176,7 +1177,7 @@ GetProcessorLocationByApicId ( // SubIndex =3D 1; do { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, SubIndex, &ExtendedTopologyEax.Uint32, @@ -1198,7 +1199,7 @@ GetProcessorLocationByApicId ( // // Get logical processor count // - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); + AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL= ); MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; =20 // @@ -1209,12 +1210,17 @@ GetProcessorLocationByApicId ( // // Check for topology extensions on AMD processor // - if (StandardSignatureIsAuthenticAMD()) { + if (StandardSignatureIsAuthenticAMD ()) { if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { - AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx= .Uint32, NULL); + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEc= x.Uint32, NULL); if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { - AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopolo= gyEbx.Uint32, - &AmdProcessorTopologyEcx.Uint32, NULL); + AsmCpuid ( + CPUID_AMD_PROCESSOR_TOPOLOGY, + NULL, + &AmdProcessorTopologyEbx.Uint32, + &AmdProcessorTopologyEcx.Uint32, + NULL + ); // // Get cores per processor package // @@ -1223,7 +1229,7 @@ GetProcessorLocationByApicId ( // // Account for actual thread count (e.g., SMT disabled) // - AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddre= ssSizeEcx.Uint32, NULL); + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddr= essSizeEcx.Uint32, NULL); MaxThreadPerPackageMask =3D 1 << AmdVirPhyAddressSizeEcx.Bits.Ap= icIdCoreIdSize; ActualThreadPerPackageMask =3D 1; while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage= ) { @@ -1231,7 +1237,7 @@ GetProcessorLocationByApicId ( } =20 // - // Adjust APIC Id to report concatenation of Package|Core|Thread. + // Adjust APIC Id to report concatenation of Core|Thread. // if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { MaxCoresPerNode =3D MaxCoresPerPackage / (AmdProcessorTopology= Ecx.Bits.NodesPerProcessor + 1); @@ -1243,13 +1249,20 @@ GetProcessorLocationByApicId ( CorePerNodeMask -=3D 1; =20 ApicIdShift =3D 0; + ApicIdMask =3D ActualThreadPerPackageMask; do { ApicIdShift +=3D 1; - ActualThreadPerPackageMask <<=3D 1; - } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); + ApicIdMask <<=3D 1; + } while (ApicIdMask < MaxThreadPerPackageMask); =20 InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicI= dShift) | (InitialApicId & CorePerNodeMask); } + // + // Adjust APIC Id to report concatenation of Package|Core|Thread. + // + if ((InitialApicId & ~(MaxThreadPerPackageMask - 1)) !=3D 0) { + InitialApicId =3D (InitialApicId & (ActualThreadPerPackageMask= - 1)) | ActualThreadPerPackageMask; + } } } } @@ -1258,7 +1271,7 @@ GetProcessorLocationByApicId ( // Extract core count based on CACHE information // if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NU= LL, NULL); + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, N= ULL, NULL); if (CacheParamsEax.Uint32 !=3D 0) { MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIds= ForLogicalProcessors + 1; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel