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charset="utf-8" GetProcessorLocationByApicId () - Use max possible thread count to decode InitialApicId on AMD processor. - Clean-up on C Coding standards. Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 64 ++++++------------= ---- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 64 ++++++------------= ---- 2 files changed, 32 insertions(+), 96 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index 2091e5e..b0b7e32 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -48,7 +48,7 @@ StandardSignatureIsAuthenticAMD ( UINT32 RegEcx; UINT32 RegEdx; =20 - AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); @@ -1000,7 +1000,6 @@ GetProcessorLocationByApicId ( CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; - CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; UINT32 MaxStandardCpuIdIndex; UINT32 MaxExtendedCpuIdIndex; @@ -1008,18 +1007,13 @@ GetProcessorLocationByApicId ( UINTN LevelType; UINT32 MaxLogicProcessorsPerPackage; UINT32 MaxCoresPerPackage; - UINT32 MaxThreadPerPackageMask; - UINT32 ActualThreadPerPackageMask; - UINT32 MaxCoresPerNode; - UINT32 CorePerNodeMask; - UINT32 ApicIdShift; UINTN ThreadBits; UINTN CoreBits; =20 // // Check if the processor is capable of supporting more than one logical= processor. // - AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { if (Thread !=3D NULL) { *Thread =3D 0; @@ -1042,8 +1036,8 @@ GetProcessorLocationByApicId ( // // Get max index of CPUID // - AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); - AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NU= LL); + AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, N= ULL); =20 // // If the extended topology enumeration leaf is available, it @@ -1072,7 +1066,7 @@ GetProcessorLocationByApicId ( // the SMT sub-field of x2APIC ID. // LevelType =3D ExtendedTopologyEcx.Bits.LevelType; - ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; =20 // @@ -1081,7 +1075,7 @@ GetProcessorLocationByApicId ( // SubIndex =3D 1; do { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, SubIndex, &ExtendedTopologyEax.Uint32, @@ -1103,7 +1097,7 @@ GetProcessorLocationByApicId ( // // Get logical processor count // - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); + AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL= ); MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; =20 // @@ -1116,45 +1110,19 @@ GetProcessorLocationByApicId ( // if (StandardSignatureIsAuthenticAMD()) { if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { - AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx= .Uint32, NULL); + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEc= x.Uint32, NULL); if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { - AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopolo= gyEbx.Uint32, - &AmdProcessorTopologyEcx.Uint32, NULL); + // + // Account for max possible thread count to decode ApicId + // + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddr= essSizeEcx.Uint32, NULL); + MaxLogicProcessorsPerPackage =3D 1 << AmdVirPhyAddressSizeEcx.Bi= ts.ApicIdCoreIdSize; + // // Get cores per processor package // + AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopol= ogyEbx.Uint32, NULL, NULL); MaxCoresPerPackage =3D MaxLogicProcessorsPerPackage / (AmdProces= sorTopologyEbx.Bits.ThreadsPerCore + 1); - - // - // Account for actual thread count (e.g., SMT disabled) - // - AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddre= ssSizeEcx.Uint32, NULL); - MaxThreadPerPackageMask =3D 1 << AmdVirPhyAddressSizeEcx.Bits.Ap= icIdCoreIdSize; - ActualThreadPerPackageMask =3D 1; - while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage= ) { - ActualThreadPerPackageMask <<=3D 1; - } - - // - // Adjust APIC Id to report concatenation of Package|Core|Thread. - // - if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { - MaxCoresPerNode =3D MaxCoresPerPackage / (AmdProcessorTopology= Ecx.Bits.NodesPerProcessor + 1); - - CorePerNodeMask =3D 1; - while (CorePerNodeMask < MaxCoresPerNode) { - CorePerNodeMask <<=3D 1; - } - CorePerNodeMask -=3D 1; - - ApicIdShift =3D 0; - do { - ApicIdShift +=3D 1; - ActualThreadPerPackageMask <<=3D 1; - } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); - - InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicI= dShift) | (InitialApicId & CorePerNodeMask); - } } } } @@ -1163,7 +1131,7 @@ GetProcessorLocationByApicId ( // Extract core count based on CACHE information // if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NU= LL, NULL); + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, N= ULL, NULL); if (CacheParamsEax.Uint32 !=3D 0) { MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIds= ForLogicalProcessors + 1; } diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index d5d4efa..1f4dcf7 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -49,7 +49,7 @@ StandardSignatureIsAuthenticAMD ( UINT32 RegEcx; UINT32 RegEdx; =20 - AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); @@ -1095,7 +1095,6 @@ GetProcessorLocationByApicId ( CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; - CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; UINT32 MaxStandardCpuIdIndex; UINT32 MaxExtendedCpuIdIndex; @@ -1103,18 +1102,13 @@ GetProcessorLocationByApicId ( UINTN LevelType; UINT32 MaxLogicProcessorsPerPackage; UINT32 MaxCoresPerPackage; - UINT32 MaxThreadPerPackageMask; - UINT32 ActualThreadPerPackageMask; - UINT32 MaxCoresPerNode; - UINT32 CorePerNodeMask; - UINT32 ApicIdShift; UINTN ThreadBits; UINTN CoreBits; =20 // // Check if the processor is capable of supporting more than one logical= processor. // - AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { if (Thread !=3D NULL) { *Thread =3D 0; @@ -1137,8 +1131,8 @@ GetProcessorLocationByApicId ( // // Get max index of CPUID // - AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); - AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NU= LL); + AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, N= ULL); =20 // // If the extended topology enumeration leaf is available, it @@ -1167,7 +1161,7 @@ GetProcessorLocationByApicId ( // the SMT sub-field of x2APIC ID. // LevelType =3D ExtendedTopologyEcx.Bits.LevelType; - ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; =20 // @@ -1176,7 +1170,7 @@ GetProcessorLocationByApicId ( // SubIndex =3D 1; do { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, SubIndex, &ExtendedTopologyEax.Uint32, @@ -1198,7 +1192,7 @@ GetProcessorLocationByApicId ( // // Get logical processor count // - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); + AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL= ); MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; =20 // @@ -1211,45 +1205,19 @@ GetProcessorLocationByApicId ( // if (StandardSignatureIsAuthenticAMD()) { if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { - AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx= .Uint32, NULL); + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEc= x.Uint32, NULL); if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { - AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopolo= gyEbx.Uint32, - &AmdProcessorTopologyEcx.Uint32, NULL); + // + // Account for max possible thread count to decode ApicId + // + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddr= essSizeEcx.Uint32, NULL); + MaxLogicProcessorsPerPackage =3D 1 << AmdVirPhyAddressSizeEcx.Bi= ts.ApicIdCoreIdSize; + // // Get cores per processor package // + AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopol= ogyEbx.Uint32, NULL, NULL); MaxCoresPerPackage =3D MaxLogicProcessorsPerPackage / (AmdProces= sorTopologyEbx.Bits.ThreadsPerCore + 1); - - // - // Account for actual thread count (e.g., SMT disabled) - // - AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddre= ssSizeEcx.Uint32, NULL); - MaxThreadPerPackageMask =3D 1 << AmdVirPhyAddressSizeEcx.Bits.Ap= icIdCoreIdSize; - ActualThreadPerPackageMask =3D 1; - while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage= ) { - ActualThreadPerPackageMask <<=3D 1; - } - - // - // Adjust APIC Id to report concatenation of Package|Core|Thread. - // - if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { - MaxCoresPerNode =3D MaxCoresPerPackage / (AmdProcessorTopology= Ecx.Bits.NodesPerProcessor + 1); - - CorePerNodeMask =3D 1; - while (CorePerNodeMask < MaxCoresPerNode) { - CorePerNodeMask <<=3D 1; - } - CorePerNodeMask -=3D 1; - - ApicIdShift =3D 0; - do { - ApicIdShift +=3D 1; - ActualThreadPerPackageMask <<=3D 1; - } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); - - InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicI= dShift) | (InitialApicId & CorePerNodeMask); - } } } } @@ -1258,7 +1226,7 @@ GetProcessorLocationByApicId ( // Extract core count based on CACHE information // if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NU= LL, NULL); + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, N= ULL, NULL); if (CacheParamsEax.Uint32 !=3D 0) { MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIds= ForLogicalProcessors + 1; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel