From nobody Thu Dec 26 14:32:40 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150302692596620.009792466008435; Thu, 17 Aug 2017 20:28:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 622C32095B9F6; Thu, 17 Aug 2017 20:26:15 -0700 (PDT) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 37C2521B0E537 for ; Thu, 17 Aug 2017 20:26:13 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 17 Aug 2017 20:28:41 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga004.jf.intel.com with ESMTP; 17 Aug 2017 20:28:40 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,391,1498546800"; d="scan'208";a="120284135" From: Eric Dong To: edk2-devel@lists.01.org Date: Fri, 18 Aug 2017 11:28:36 +0800 Message-Id: <1503026917-13296-2-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1503026917-13296-1-git-send-email-eric.dong@intel.com> References: <1503026917-13296-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch v2 1/2] UefiCpuPkg/ArchitecturalMsr.h: Add RTIT TOPA table entry definition. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add RTIT TOPA table entry definition to architecturalMsr.h file. Cc: Michael Kinney Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 55 ++++++++++++++++++++++= ++++ 1 file changed, 55 insertions(+) diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/In= clude/Register/ArchitecturalMsr.h index 4f9c103..40c4383 100644 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h @@ -4534,6 +4534,61 @@ typedef union { UINT64 Uint64; } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER; =20 +/** + Format of ToPA table entries. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (T= oPA)". + /// + UINT32 END:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (T= oPA)". + /// + UINT32 INT:1; + UINT32 Reserved2:1; + /// + /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (= ToPA)". + /// + UINT32 STOP:1; + UINT32 Reserved3:1; + /// + /// [Bit 6:9] Indicates the size of the associated output region. See = Section + /// 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 Size:4; + UINT32 Reserved4:2; + /// + /// [Bit 12:31] Output Region Base Physical Address low part. + /// [Bit 12:31] Output Region Base Physical Address [12:63] value to m= atch. + /// ATTENTION: The size of the address field is determined by the proc= essor's + /// physical-address width (MAXPHYADDR) in bits, as reported in + /// CPUID.80000008H:EAX[7:0]. the above part of address reserved. + /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserv= ed part. + /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 Base:20; + /// + /// [Bit 32:63] Output Region Base Physical Address high part. + /// [Bit 32:63] Output Region Base Physical Address [12:63] value to m= atch. + /// ATTENTION: The size of the address field is determined by the proc= essor's + /// physical-address width (MAXPHYADDR) in bits, as reported in + /// CPUID.80000008H:EAX[7:0]. the above part of address reserved. + /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserv= ed part. + /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 BaseHi:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} RTIT_TOPA_TABLE_ENTRY; =20 /** Trace Control Register (R/W). If (CPUID.(EAX=3D07H, ECX=3D0):EBX[25] =3D= 1). --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 14:32:40 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1503026928153123.84700163882019; Thu, 17 Aug 2017 20:28:48 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 99B9C21E7901D; Thu, 17 Aug 2017 20:26:15 -0700 (PDT) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7540621E79018 for ; Thu, 17 Aug 2017 20:26:14 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 17 Aug 2017 20:28:42 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga004.jf.intel.com with ESMTP; 17 Aug 2017 20:28:41 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,391,1498546800"; d="scan'208";a="120284143" From: Eric Dong To: edk2-devel@lists.01.org Date: Fri, 18 Aug 2017 11:28:37 +0800 Message-Id: <1503026917-13296-3-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1503026917-13296-1-git-send-email-eric.dong@intel.com> References: <1503026917-13296-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch v2 2/2] UefiCpuPkg/CpuCommonFeaturesLib: Use MSR data structure when change MSR value. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When update MSR values, current code use BITxx to modify it. Enhance the co= de to use corresponding MSR's data structures to make it more user friendly. Cc: Michael Kinney Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- .../Library/CpuCommonFeaturesLib/ProcTrace.c | 70 +++++++++++++-----= ---- 1 file changed, 42 insertions(+), 28 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuP= kg/Library/CpuCommonFeaturesLib/ProcTrace.c index 40e6321..a90dd4e 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c @@ -70,7 +70,7 @@ typedef struct { } PROC_TRACE_DATA; =20 typedef struct { - UINT64 TopaEntry[MAX_TOPA_ENTRY_COUNT]; + RTIT_TOPA_TABLE_ENTRY TopaEntry[MAX_TOPA_ENTRY_COUNT]; } PROC_TRACE_TOPA_TABLE; =20 /** @@ -186,7 +186,6 @@ ProcTraceInitialize ( IN BOOLEAN State ) { - UINT64 MsrValue; UINT32 MemRegionSize; UINTN Pages; UINTN Alignment; @@ -199,6 +198,11 @@ ProcTraceInitialize ( PROC_TRACE_TOPA_TABLE *TopaTable; PROC_TRACE_DATA *ProcTraceData; BOOLEAN FirstIn; + MSR_IA32_RTIT_CTL_REGISTER CtrlReg; + MSR_IA32_RTIT_STATUS_REGISTER StatusReg; + MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg; + MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg; + RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr; =20 ProcTraceData =3D (PROC_TRACE_DATA *) ConfigData; =20 @@ -221,29 +225,28 @@ ProcTraceInitialize ( // // Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CT= L[0]=3D=3D1b // - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - if ((MsrValue & BIT0) !=3D 0) { + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + if (CtrlReg.Bits.TraceEn !=3D 0) { /// /// Clear bit 0 in MSR IA32_RTIT_CTL (570) /// - MsrValue &=3D (UINT64) ~BIT0; + CtrlReg.Bits.TraceEn =3D 0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); =20 /// /// Clear MSR IA32_RTIT_STS (571h) to all zeros /// - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_STATUS); - MsrValue &=3D 0x0; + StatusReg.Uint64 =3D 0x0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_STATUS, - MsrValue + StatusReg.Uint64 ); } =20 @@ -309,35 +312,35 @@ ProcTraceInitialize ( // // Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8) // - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - MsrValue &=3D (UINT64) ~BIT8; + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + CtrlReg.Bits.ToPA =3D 0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); =20 // // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with the allo= cated Memory Region // - MsrValue =3D (UINT64) MemRegionBaseAddr; + OutputBaseReg.Uint64 =3D (UINT64) MemRegionBaseAddr; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_BASE, - MsrValue + OutputBaseReg.Uint64 ); =20 // // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT= _MASK_PTRS (561h) // - MsrValue =3D (UINT64) MemRegionSize - 1; + OutputMaskPtrsReg.Uint64 =3D (UINT64) MemRegionSize - 1; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_MASK_PTRS, - MsrValue + OutputMaskPtrsReg.Uint64 ); =20 } @@ -408,55 +411,66 @@ ProcTraceInitialize ( } =20 TopaTable =3D (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr; - TopaTable->TopaEntry[0] =3D (UINT64) (MemRegionBaseAddr | ((ProcTraceD= ata->ProcTraceMemSize) << 6)) & ~BIT0; - TopaTable->TopaEntry[1] =3D (UINT64) TopaTableBaseAddr | BIT0; + TopaEntryPtr =3D &TopaTable->TopaEntry[0]; + TopaEntryPtr->Uint64 =3D (UINT64) MemRegionBaseAddr; + TopaEntryPtr->Bits.Size =3D ProcTraceData->ProcTraceMemSize; + TopaEntryPtr->Bits.END =3D 0; + + TopaEntryPtr =3D &TopaTable->TopaEntry[1]; + TopaEntryPtr->Uint64 =3D (UINT64) TopaTableBaseAddr; + TopaEntryPtr->Bits.END =3D 1; =20 // // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with ToPA= base // - MsrValue =3D (UINT64) TopaTableBaseAddr; + OutputBaseReg.Uint64 =3D (UINT64) TopaTableBaseAddr; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_BASE, - MsrValue + OutputBaseReg.Uint64 ); =20 // // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0 // + OutputMaskPtrsReg.Uint64 =3D (UINT64) 0x7F; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_MASK_PTRS, - 0x7F + OutputMaskPtrsReg.Uint64 ); // // Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToP= A (Bit 8) // - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - MsrValue |=3D BIT8; + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + CtrlReg.Bits.ToPA =3D 1; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); } =20 /// /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h) /// - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - MsrValue |=3D (UINT64) BIT0 + BIT2 + BIT3 + BIT13; + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + CtrlReg.Bits.OS =3D 1; + CtrlReg.Bits.User =3D 1; + CtrlReg.Bits.BranchEn =3D 1; if (!State) { - MsrValue &=3D (UINT64) ~BIT0; + CtrlReg.Bits.TraceEn =3D 0; + } else { + CtrlReg.Bits.TraceEn =3D 1; } CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); =20 return RETURN_SUCCESS; --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel