From nobody Fri Dec 27 03:46:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150306523377153.817105111815636; Fri, 18 Aug 2017 07:07:13 -0700 (PDT) Received: from localhost ([::1]:56002 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihvc-000878-HG for importer@patchew.org; Fri, 18 Aug 2017 10:07:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51637) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqm-0004CY-LT for qemu-devel@nongnu.org; Fri, 18 Aug 2017 10:02:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqg-00007p-T3 for qemu-devel@nongnu.org; Fri, 18 Aug 2017 10:02:12 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2237) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqY-0008RQ-HQ; Fri, 18 Aug 2017 10:01:59 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74412; Fri, 18 Aug 2017 22:00:48 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:14 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Date: Fri, 18 Aug 2017 22:23:47 +0800 Message-ID: <1503066227-18251-7-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0207.5996F310.019D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a2fc3c2d8f4dd5ae8c41d992041e0951 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-devel] [PATCH v11 6/6] target-arm: kvm64: Handle SError interrupt for the guest OS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhengqiang10@huawei.com, wuquanming@huawei.com, huangshaoyu@huawei.com, linuxarm@huawei.com, gengdongjiu@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When guest OS happens SError interrupt(SEI), it will trap to host. Host firstly calls memory failure to deal with this error and decide whether it needs to deliver SIGBUS signal to userspace. The advantage that using signal to notify is that it can make the notification method is general, non-KVM user can also use it. when userspace gets this signal and knows this is SError interrupt, it will translate the delivered host VA to PA and record this PA to GHES. Because ARMv8.2 adds an extension to RAS to allow system software insert implicit Error Synchronization Barrier operations to isolate the error and allow passes specified syndrome to guest OS, so after record the CPER, user space calls IOCTL to pass a specified syndrome to KVM, then switch to guest OS, guest OS can use the recorded CPER record and syndrome information to do the recovery. The steps are shown below: 1. translate the host VA to guest OS PA and record this error PA to HEST ta= ble. 2. set specified virtual SError syndrome and pass the value to KVM. Signed-off-by: Dongjiu Geng Signed-off-by: Quanming Wu --- linux-headers/linux/kvm.h | 1 + target/arm/internals.h | 1 + target/arm/kvm64.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 2aa176e..10dfcab 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1356,6 +1356,7 @@ struct kvm_s390_ucas_mapping { /* Available with KVM_CAP_S390_CMMA_MIGRATION */ #define KVM_S390_GET_CMMA_BITS _IOWR(KVMIO, 0xb8, struct kvm_s390_cmm= a_log) #define KVM_S390_SET_CMMA_BITS _IOW(KVMIO, 0xb9, struct kvm_s390_cmma= _log) +#define KVM_ARM_SEI _IO(KVMIO, 0xb10) =20 #define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0) #define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1) diff --git a/target/arm/internals.h b/target/arm/internals.h index fc0ad6d..18b1cbc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -237,6 +237,7 @@ enum arm_exception_class { #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) #define ARM_EL_EC_MASK ((0x3F) << ARM_EL_EC_SHIFT) #define ARM_EL_FSC_TYPE (0x3C) +#define ARM_EL_ISS_MASK ((1 << ARM_EL_IL_SHIFT) - 1) =20 #define FSC_SEA (0x10) #define FSC_SEA_TTW0 (0x14) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index d3bdab2..b84cb49 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -616,6 +616,22 @@ static int kvm_arm_cpreg_value(ARMCPU *cpu, ptrdiff_t = fieldoffset) return -EINVAL; } =20 +static int kvm_inject_arm_sei(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + unsigned long syndrome =3D env->exception.vaddress; + /* set virtual SError syndrome */ + if (arm_feature(env, ARM_FEATURE_RAS_EXTENSION)) { + syndrome =3D syndrome & ARM_EL_ISS_MASK; + } else { + syndrome =3D 0; + } + + return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_SEI, &syndrome); +} + /* Inject synchronous external abort */ static int kvm_inject_arm_sea(CPUState *c) { @@ -1007,6 +1023,15 @@ static bool is_abort_sea(unsigned long syndrome) } } =20 +static bool is_abort_sei(unsigned long syndrome) +{ + uint8_t ec =3D ((syndrome & ARM_EL_EC_MASK) >> ARM_EL_EC_SHIFT); + if ((ec !=3D EC_SERROR)) + return false; + else + return true; +} + void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) { ram_addr_t ram_addr; @@ -1024,6 +1049,9 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, v= oid *addr) if (is_abort_sea(env->exception.syndrome)) { ghes_update_guest(ACPI_HEST_NOTIFY_SEA, paddr); kvm_inject_arm_sea(c); + } else if (is_abort_sei(env->exception.syndrome)) { + ghes_update_guest(ACPI_HEST_NOTIFY_SEI, paddr); + kvm_inject_arm_sei(c); } return; } --=20 1.8.3.1