From nobody Thu Dec 26 14:46:54 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1503543820954122.68835975181423; Wed, 23 Aug 2017 20:03:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 403C321D2E63C; Wed, 23 Aug 2017 20:01:02 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 62BEE21D2E62C for ; Wed, 23 Aug 2017 20:01:00 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Aug 2017 20:03:34 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 23 Aug 2017 20:03:32 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,419,1498546800"; d="scan'208";a="127637273" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 24 Aug 2017 11:03:24 +0800 Message-Id: <1503543807-6304-2-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1503543807-6304-1-git-send-email-eric.dong@intel.com> References: <1503543807-6304-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 1/4] UefiCpuPkg/ArchitecturalMsr.h: Add RTIT TOPA table entry definition. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add RTIT TOPA table entry definition to architecturalMsr.h file. V2: Add RTIT_TOPA_MEMORY_SIZE definition to architecturalMsr.h file. Cc: Michael Kinney Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Michael Kinney --- UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 79 ++++++++++++++++++++++= +++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/In= clude/Register/ArchitecturalMsr.h index 4f9c103..34fdf5b 100644 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -4534,6 +4534,83 @@ typedef union { UINT64 Uint64; } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER; =20 +/** + Format of ToPA table entries. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (T= oPA)". + /// + UINT32 END:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (T= oPA)". + /// + UINT32 INT:1; + UINT32 Reserved2:1; + /// + /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (= ToPA)". + /// + UINT32 STOP:1; + UINT32 Reserved3:1; + /// + /// [Bit 6:9] Indicates the size of the associated output region. See = Section + /// 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 Size:4; + UINT32 Reserved4:2; + /// + /// [Bit 12:31] Output Region Base Physical Address low part. + /// [Bit 12:31] Output Region Base Physical Address [12:63] value to m= atch. + /// ATTENTION: The size of the address field is determined by the proc= essor's + /// physical-address width (MAXPHYADDR) in bits, as reported in + /// CPUID.80000008H:EAX[7:0]. the above part of address reserved. + /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserv= ed part. + /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 Base:20; + /// + /// [Bit 32:63] Output Region Base Physical Address high part. + /// [Bit 32:63] Output Region Base Physical Address [12:63] value to m= atch. + /// ATTENTION: The size of the address field is determined by the proc= essor's + /// physical-address width (MAXPHYADDR) in bits, as reported in + /// CPUID.80000008H:EAX[7:0]. the above part of address reserved. + /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserv= ed part. + /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 BaseHi:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} RTIT_TOPA_TABLE_ENTRY; + +/// +/// The size of the associated output region usd by Topa. +/// +typedef enum { + RtitTopaMemorySize4K =3D 0, + RtitTopaMemorySize8K, + RtitTopaMemorySize16K, + RtitTopaMemorySize32K, + RtitTopaMemorySize64K, + RtitTopaMemorySize128K, + RtitTopaMemorySize256K, + RtitTopaMemorySize512K, + RtitTopaMemorySize1M, + RtitTopaMemorySize2M, + RtitTopaMemorySize4M, + RtitTopaMemorySize8M, + RtitTopaMemorySize16M, + RtitTopaMemorySize32M, + RtitTopaMemorySize64M, + RtitTopaMemorySize128M +} RTIT_TOPA_MEMORY_SIZE; =20 /** Trace Control Register (R/W). If (CPUID.(EAX=3D07H, ECX=3D0):EBX[25] =3D= 1). --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 14:46:54 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1503543823594480.3173270929233; Wed, 23 Aug 2017 20:03:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7C06D21D2E646; Wed, 23 Aug 2017 20:01:02 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7E76A21D2E633 for ; Wed, 23 Aug 2017 20:01:00 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Aug 2017 20:03:34 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 23 Aug 2017 20:03:33 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,419,1498546800"; d="scan'208";a="127637278" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 24 Aug 2017 11:03:25 +0800 Message-Id: <1503543807-6304-3-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1503543807-6304-1-git-send-email-eric.dong@intel.com> References: <1503543807-6304-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 2/4] UefiCpuPkg/CpuCommonFeaturesLib: Use MSR data structure when change MSR value. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When update MSR values, current code use BITxx to modify it. Enhance the co= de to use corresponding MSR's data structures to make it more user friendly. V2: Move architecturalMsr.h file. definition to architecturalMsr.h file. Use structure members to do value assignment. Cc: Michael Kinney Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Michael Kinney --- .../Library/CpuCommonFeaturesLib/ProcTrace.c | 116 +++++++++++------= ---- 1 file changed, 61 insertions(+), 55 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuP= kg/Library/CpuCommonFeaturesLib/ProcTrace.c index 40e6321..e4636b2 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c @@ -14,30 +14,17 @@ =20 #include "CpuCommonFeatures.h" =20 -#define MAX_TOPA_ENTRY_COUNT 2 - /// -/// Processor trace buffer size selection. +/// This macro define the max entries in the Topa table. +/// Each entry in the table contains some attribute bits, a pointer to an = output region, and the size of the region.=20 +/// The last entry in the table may hold a pointer to the next table. This= pointer can either point to the top of the=20 +/// current table (for circular array) or to the base of another table.=20 +/// At least 2 entries are needed because the list of entries must=20 +/// be terminated by an entry with the END bit set to 1, so 2=20 +/// entries are required to use a single valid entry. /// -typedef enum { - Enum4K =3D 0, - Enum8K, - Enum16K, - Enum32K, - Enum64K, - Enum128K, - Enum256K, - Enum512K, - Enum1M, - Enum2M, - Enum4M, - Enum8M, - Enum16M, - Enum32M, - Enum64M, - Enum128M, - EnumProcTraceMemDisable -} PROC_TRACE_MEM_SIZE; +#define MAX_TOPA_ENTRY_COUNT 2 + =20 /// /// Processor trace output scheme selection. @@ -70,7 +57,7 @@ typedef struct { } PROC_TRACE_DATA; =20 typedef struct { - UINT64 TopaEntry[MAX_TOPA_ENTRY_COUNT]; + RTIT_TOPA_TABLE_ENTRY TopaEntry[MAX_TOPA_ENTRY_COUNT]; } PROC_TRACE_TOPA_TABLE; =20 /** @@ -134,8 +121,8 @@ ProcTraceSupport ( // Check if ProcTraceMemorySize option is enabled (0xFF means disable by= user) // ProcTraceData =3D (PROC_TRACE_DATA *) ConfigData; - if ((ProcTraceData->ProcTraceMemSize >=3D EnumProcTraceMemDisable) || - (ProcTraceData->ProcTraceOutputScheme >=3D OutputSchemeInvalid)) { + if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) || + (ProcTraceData->ProcTraceOutputScheme > ProcTraceOutputSchemeToPA)) { return FALSE; } =20 @@ -186,7 +173,6 @@ ProcTraceInitialize ( IN BOOLEAN State ) { - UINT64 MsrValue; UINT32 MemRegionSize; UINTN Pages; UINTN Alignment; @@ -199,6 +185,11 @@ ProcTraceInitialize ( PROC_TRACE_TOPA_TABLE *TopaTable; PROC_TRACE_DATA *ProcTraceData; BOOLEAN FirstIn; + MSR_IA32_RTIT_CTL_REGISTER CtrlReg; + MSR_IA32_RTIT_STATUS_REGISTER StatusReg; + MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg; + MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg; + RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr; =20 ProcTraceData =3D (PROC_TRACE_DATA *) ConfigData; =20 @@ -221,29 +212,28 @@ ProcTraceInitialize ( // // Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CT= L[0]=3D=3D1b // - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - if ((MsrValue & BIT0) !=3D 0) { + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + if (CtrlReg.Bits.TraceEn !=3D 0) { /// /// Clear bit 0 in MSR IA32_RTIT_CTL (570) /// - MsrValue &=3D (UINT64) ~BIT0; + CtrlReg.Bits.TraceEn =3D 0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); =20 /// /// Clear MSR IA32_RTIT_STS (571h) to all zeros /// - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_STATUS); - MsrValue &=3D 0x0; + StatusReg.Uint64 =3D 0x0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_STATUS, - MsrValue + StatusReg.Uint64 ); } =20 @@ -309,37 +299,38 @@ ProcTraceInitialize ( // // Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8) // - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - MsrValue &=3D (UINT64) ~BIT8; + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + CtrlReg.Bits.ToPA =3D 0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); =20 // - // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with the allo= cated Memory Region + // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the alloc= ated Memory Region // - MsrValue =3D (UINT64) MemRegionBaseAddr; + OutputBaseReg.Bits.Base =3D (MemRegionBaseAddr >> 7) & 0x01FFFFFF; + OutputBaseReg.Bits.BaseHi =3D RShiftU64 ((UINT64) MemRegionBaseAddr, 3= 2) & 0xFFFFFFFF; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_BASE, - MsrValue + OutputBaseReg.Uint64 ); =20 // // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT= _MASK_PTRS (561h) // - MsrValue =3D (UINT64) MemRegionSize - 1; + OutputMaskPtrsReg.Bits.MaskOrTableOffset =3D ((MemRegionSize - 1) >> 7= ) & 0x01FFFFFF; + OutputMaskPtrsReg.Bits.OutputOffset =3D RShiftU64 ((UINT64) (MemRegion= Size - 1), 32) & 0xFFFFFFFF; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_MASK_PTRS, - MsrValue + OutputMaskPtrsReg.Uint64 ); - } =20 // @@ -408,55 +399,70 @@ ProcTraceInitialize ( } =20 TopaTable =3D (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr; - TopaTable->TopaEntry[0] =3D (UINT64) (MemRegionBaseAddr | ((ProcTraceD= ata->ProcTraceMemSize) << 6)) & ~BIT0; - TopaTable->TopaEntry[1] =3D (UINT64) TopaTableBaseAddr | BIT0; + TopaEntryPtr =3D &TopaTable->TopaEntry[0]; + TopaEntryPtr->Bits.Base =3D (MemRegionBaseAddr >> 12) & 0x000FFFFF; + TopaEntryPtr->Bits.BaseHi =3D RShiftU64 ((UINT64) MemRegionBaseAddr, 3= 2) & 0xFFFFFFFF; + TopaEntryPtr->Bits.Size =3D ProcTraceData->ProcTraceMemSize; + TopaEntryPtr->Bits.END =3D 0; + + TopaEntryPtr =3D &TopaTable->TopaEntry[1]; + TopaEntryPtr->Bits.Base =3D (TopaTableBaseAddr >> 12) & 0x000FFFFF; + TopaEntryPtr->Bits.BaseHi =3D RShiftU64 ((UINT64) TopaTableBaseAddr, 3= 2) & 0xFFFFFFFF; + TopaEntryPtr->Bits.END =3D 1; =20 // - // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with ToPA= base + // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA = base // - MsrValue =3D (UINT64) TopaTableBaseAddr; + OutputBaseReg.Bits.Base =3D (TopaTableBaseAddr >> 7) & 0x01FFFFFF; + OutputBaseReg.Bits.BaseHi =3D RShiftU64 ((UINT64) TopaTableBaseAddr, 3= 2) & 0xFFFFFFFF; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_BASE, - MsrValue + OutputBaseReg.Uint64 ); =20 // // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0 // + OutputMaskPtrsReg.Bits.MaskOrTableOffset =3D 0; + OutputMaskPtrsReg.Bits.OutputOffset =3D 0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_MASK_PTRS, - 0x7F + OutputMaskPtrsReg.Uint64 ); // // Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToP= A (Bit 8) // - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - MsrValue |=3D BIT8; + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + CtrlReg.Bits.ToPA =3D 1; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); } =20 /// /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h) /// - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - MsrValue |=3D (UINT64) BIT0 + BIT2 + BIT3 + BIT13; + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + CtrlReg.Bits.OS =3D 1; + CtrlReg.Bits.User =3D 1; + CtrlReg.Bits.BranchEn =3D 1; if (!State) { - MsrValue &=3D (UINT64) ~BIT0; + CtrlReg.Bits.TraceEn =3D 0; + } else { + CtrlReg.Bits.TraceEn =3D 1; } CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); =20 return RETURN_SUCCESS; --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 14:46:54 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1503543826144761.598212697832; Wed, 23 Aug 2017 20:03:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BAAEC21D2E648; Wed, 23 Aug 2017 20:01:05 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CC30221D2E635 for ; Wed, 23 Aug 2017 20:01:01 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Aug 2017 20:03:36 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 23 Aug 2017 20:03:34 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,419,1498546800"; d="scan'208";a="127637283" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 24 Aug 2017 11:03:26 +0800 Message-Id: <1503543807-6304-4-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1503543807-6304-1-git-send-email-eric.dong@intel.com> References: <1503543807-6304-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 3/4] UefiCpuPkg/CpuCommonFeaturesLib: Remove redundant definition. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The EnumProcTraceMemDisable/OutputSchemeInvalid are redundant definitions. These definitions can be handled by other code, so remove them. V2: Change enum members name. Cc: Michael Kinney Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Michael Kinney --- UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuP= kg/Library/CpuCommonFeaturesLib/ProcTrace.c index e4636b2..167c1be 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c @@ -30,10 +30,9 @@ /// Processor trace output scheme selection. /// typedef enum { - OutputSchemeSingleRange =3D 0, - OutputSchemeToPA, - OutputSchemeInvalid -} PROC_TRACE_OUTPUT_SCHEME; + RtitOutputSchemeSingleRange =3D 0, + RtitOutputSchemeToPA +} RTIT_OUTPUT_SCHEME; =20 typedef struct { BOOLEAN ProcTraceSupported; @@ -122,7 +121,7 @@ ProcTraceSupport ( // ProcTraceData =3D (PROC_TRACE_DATA *) ConfigData; if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) || - (ProcTraceData->ProcTraceOutputScheme > ProcTraceOutputSchemeToPA)) { + (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) { return FALSE; } =20 @@ -138,8 +137,8 @@ ProcTraceSupport ( AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAI= N_LEAF, NULL, NULL, &Ecx.Uint32, NULL); ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported =3D (BOOLEAN= ) (Ecx.Bits.RTIT =3D=3D 1); ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported =3D (= BOOLEAN) (Ecx.Bits.SingleRangeOutput =3D=3D 1); - if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported ||=20 - ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported) { + if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (Pro= cTraceData->ProcTraceOutputScheme =3D=3D RtitOutputSchemeToPA)) || + (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = && (ProcTraceData->ProcTraceOutputScheme =3D=3D RtitOutputSchemeSingleRange= ))) { return TRUE; } =20 @@ -291,7 +290,7 @@ ProcTraceInitialize ( // Single Range output scheme // if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &= &=20 - (ProcTraceData->ProcTraceOutputScheme =3D=3D OutputSchemeSingleRange= )) { + (ProcTraceData->ProcTraceOutputScheme =3D=3D RtitOutputSchemeSingleR= ange)) { if (FirstIn) { DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme = \n")); } @@ -337,7 +336,7 @@ ProcTraceInitialize ( // ToPA(Table of physical address) scheme // if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&=20 - (ProcTraceData->ProcTraceOutputScheme =3D=3D OutputSchemeToPA)) { + (ProcTraceData->ProcTraceOutputScheme =3D=3D RtitOutputSchemeToPA)) { // // Create ToPA structure aligned at 4KB for each logical thread // with at least 2 entries by 8 bytes size each. The first entry --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 14:46:54 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1503543829093167.63408386118067; Wed, 23 Aug 2017 20:03:49 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EFAA321D2E658; Wed, 23 Aug 2017 20:01:05 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 863DF21D2E648 for ; Wed, 23 Aug 2017 20:01:02 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Aug 2017 20:03:36 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 23 Aug 2017 20:03:35 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,419,1498546800"; d="scan'208";a="127637287" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 24 Aug 2017 11:03:27 +0800 Message-Id: <1503543807-6304-5-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1503543807-6304-1-git-send-email-eric.dong@intel.com> References: <1503543807-6304-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 4/4] UefiCpuPkg: Update default for PcdCpuProcTraceMemSize/PcdCpuProcTraceOutputScheme. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" These two definitions have redundant definition which can be handle by code. This patch update them to follow new code definitions. V2: Add more comments for the PCDs and keep consistent in .dec and .uni fil= es. Cc: Michael Kinney Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Michael Kinney --- UefiCpuPkg/UefiCpuPkg.dec | 22 ++++++++++++---------- UefiCpuPkg/UefiCpuPkg.uni | 16 +++++++++------- 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index b4e099d..3bd8740 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -286,7 +286,9 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00,= 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019 =20 ## Contains the size of memory required when CPU processor trace is enab= led.

- # Default value is 0x10 which disables the processor trace.
+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) = in PcdCpuFeaturesSetting.

+ # This PCD is ignored if CPU processor trace is disabled.

+ # Default value is 0x00 which means 4KB of memory is allocated if CPU p= rocessor trace is enabled.
# 0x0 - 4K.
# 0x1 - 8K.
# 0x2 - 16K.
@@ -303,19 +305,19 @@ # 0xD - 32M.
# 0xE - 64M.
# 0xF - 128M.
- # 0x10 - ProcTraceMemDisable.
- # @Prompt The memory size used for processor trace. - # @ValidRange 0x80000001 | 0 - 0x10 - gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x10|UINT32|0x60000012 + # @Prompt The memory size used for processor trace if processor trace is= enabled. + # @ValidRange 0x80000001 | 0 - 0xF + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012 =20 ## Contains the processor trace output scheme when CPU processor trace i= s enabled.

- # Default value is 2 which disables the processor trace.
+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) = in PcdCpuFeaturesSetting.

+ # This PCD is ignored if CPU processor trace is disabled.

+ # Default value is 0 which means single range output scheme will be use= d if CPU processor trace is enabled.
# 0 - Single Range output scheme.
# 1 - ToPA(Table of physical address) scheme.
- # 2 - Invalid scheme.
- # @Prompt The processor trace output scheme. - # @ValidRange 0x80000001 | 0 - 2 - gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x2|UINT8|0x600000= 15 + # @Prompt The processor trace output scheme used when processor trace is= enabled. + # @ValidRange 0x80000001 | 0 - 1 + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x600000= 15 =20 [UserExtensions.TianoCore."ExtraFiles"] UefiCpuPkgExtra.uni diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni index 858e4a7..9472b18 100644 --- a/UefiCpuPkg/UefiCpuPkg.uni +++ b/UefiCpuPkg/UefiCpuPkg.uni @@ -197,8 +197,10 @@ =20 #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuProcTraceMemSize_PROMPT #lang= uage en-US "Memory size used by Processor Trace feature." =20 -#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuProcTraceMemSize_HELP #langua= ge en-US "User input the memory size can be used by processor trace feature= .

\n" - = "Default value is 0x10 which disables the processor memory trace.<= BR>\n" +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuProcTraceMemSize_HELP #langua= ge en-US "User input the size of memory required when CPU processor trace i= s enabled.

\n" + = "Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRA= CE) in PcdCpuFeaturesSetting.

\n" + = "This PCD is ignored if CPU processor trace is disabled.

\n" + = "Default value is 0x00 which means 4KB of memory is allocated if C= PU processor trace is enabled.
\n" = "0x0 - 4K.
\n" = "0x1 - 8K.
\n" = "0x2 - 16K.
\n" @@ -215,12 +217,12 @@ = "0xD - 32M.
\n" = "0xE - 64M.
\n" = "0xF - 128M.
\n" - = "0x10 - ProcTraceMemDisable.
\n" =20 #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuProcTraceOutputScheme_PROMPT = #language en-US "Processor Trace output scheme type." =20 -#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuProcTraceOutputScheme_HELP #l= anguage en-US "User input the processor trace output scheme type.

\n" - = "Default value is 2 which disables the processor memory trace= .
\n" +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuProcTraceOutputScheme_HELP #l= anguage en-US "User input the processor trace output scheme when CPU proces= sor trace is enabled.

\n" + = "Processor trace is enabled through set BIT44(CPU_FEATURE_PRO= C_TRACE) in PcdCpuFeaturesSetting.

\n" + = "This PCD is ignored if CPU processor trace is disabled.
<= BR>\n" + = "Default value is 0 which means single range output scheme wi= ll be used if CPU processor trace is enabled.
\n" = "0 - Single Range output scheme.
\n" - = "1 - ToPA(Table of physical address) scheme.
\n" - = "2 - Invalid scheme.
\n" \ No newline at end of file + = "1 - ToPA(Table of physical address) scheme.
\n" \ No newline at end of file --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel