From nobody Fri Dec 27 05:50:44 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1503543820954122.68835975181423; Wed, 23 Aug 2017 20:03:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 403C321D2E63C; Wed, 23 Aug 2017 20:01:02 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 62BEE21D2E62C for ; Wed, 23 Aug 2017 20:01:00 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Aug 2017 20:03:34 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 23 Aug 2017 20:03:32 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,419,1498546800"; d="scan'208";a="127637273" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 24 Aug 2017 11:03:24 +0800 Message-Id: <1503543807-6304-2-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1503543807-6304-1-git-send-email-eric.dong@intel.com> References: <1503543807-6304-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 1/4] UefiCpuPkg/ArchitecturalMsr.h: Add RTIT TOPA table entry definition. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add RTIT TOPA table entry definition to architecturalMsr.h file. V2: Add RTIT_TOPA_MEMORY_SIZE definition to architecturalMsr.h file. Cc: Michael Kinney Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 79 ++++++++++++++++++++++= +++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/In= clude/Register/ArchitecturalMsr.h index 4f9c103..34fdf5b 100644 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -4534,6 +4534,83 @@ typedef union { UINT64 Uint64; } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER; =20 +/** + Format of ToPA table entries. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (T= oPA)". + /// + UINT32 END:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (T= oPA)". + /// + UINT32 INT:1; + UINT32 Reserved2:1; + /// + /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (= ToPA)". + /// + UINT32 STOP:1; + UINT32 Reserved3:1; + /// + /// [Bit 6:9] Indicates the size of the associated output region. See = Section + /// 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 Size:4; + UINT32 Reserved4:2; + /// + /// [Bit 12:31] Output Region Base Physical Address low part. + /// [Bit 12:31] Output Region Base Physical Address [12:63] value to m= atch. + /// ATTENTION: The size of the address field is determined by the proc= essor's + /// physical-address width (MAXPHYADDR) in bits, as reported in + /// CPUID.80000008H:EAX[7:0]. the above part of address reserved. + /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserv= ed part. + /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 Base:20; + /// + /// [Bit 32:63] Output Region Base Physical Address high part. + /// [Bit 32:63] Output Region Base Physical Address [12:63] value to m= atch. + /// ATTENTION: The size of the address field is determined by the proc= essor's + /// physical-address width (MAXPHYADDR) in bits, as reported in + /// CPUID.80000008H:EAX[7:0]. the above part of address reserved. + /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserv= ed part. + /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 BaseHi:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} RTIT_TOPA_TABLE_ENTRY; + +/// +/// The size of the associated output region usd by Topa. +/// +typedef enum { + RtitTopaMemorySize4K =3D 0, + RtitTopaMemorySize8K, + RtitTopaMemorySize16K, + RtitTopaMemorySize32K, + RtitTopaMemorySize64K, + RtitTopaMemorySize128K, + RtitTopaMemorySize256K, + RtitTopaMemorySize512K, + RtitTopaMemorySize1M, + RtitTopaMemorySize2M, + RtitTopaMemorySize4M, + RtitTopaMemorySize8M, + RtitTopaMemorySize16M, + RtitTopaMemorySize32M, + RtitTopaMemorySize64M, + RtitTopaMemorySize128M +} RTIT_TOPA_MEMORY_SIZE; =20 /** Trace Control Register (R/W). If (CPUID.(EAX=3D07H, ECX=3D0):EBX[25] =3D= 1). --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel