From nobody Mon Feb 9 20:03:12 2026 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1503543823594480.3173270929233; Wed, 23 Aug 2017 20:03:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7C06D21D2E646; Wed, 23 Aug 2017 20:01:02 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7E76A21D2E633 for ; Wed, 23 Aug 2017 20:01:00 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Aug 2017 20:03:34 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 23 Aug 2017 20:03:33 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,419,1498546800"; d="scan'208";a="127637278" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 24 Aug 2017 11:03:25 +0800 Message-Id: <1503543807-6304-3-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1503543807-6304-1-git-send-email-eric.dong@intel.com> References: <1503543807-6304-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 2/4] UefiCpuPkg/CpuCommonFeaturesLib: Use MSR data structure when change MSR value. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When update MSR values, current code use BITxx to modify it. Enhance the co= de to use corresponding MSR's data structures to make it more user friendly. V2: Move architecturalMsr.h file. definition to architecturalMsr.h file. Use structure members to do value assignment. Cc: Michael Kinney Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- .../Library/CpuCommonFeaturesLib/ProcTrace.c | 116 +++++++++++------= ---- 1 file changed, 61 insertions(+), 55 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuP= kg/Library/CpuCommonFeaturesLib/ProcTrace.c index 40e6321..e4636b2 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c @@ -14,30 +14,17 @@ =20 #include "CpuCommonFeatures.h" =20 -#define MAX_TOPA_ENTRY_COUNT 2 - /// -/// Processor trace buffer size selection. +/// This macro define the max entries in the Topa table. +/// Each entry in the table contains some attribute bits, a pointer to an = output region, and the size of the region.=20 +/// The last entry in the table may hold a pointer to the next table. This= pointer can either point to the top of the=20 +/// current table (for circular array) or to the base of another table.=20 +/// At least 2 entries are needed because the list of entries must=20 +/// be terminated by an entry with the END bit set to 1, so 2=20 +/// entries are required to use a single valid entry. /// -typedef enum { - Enum4K =3D 0, - Enum8K, - Enum16K, - Enum32K, - Enum64K, - Enum128K, - Enum256K, - Enum512K, - Enum1M, - Enum2M, - Enum4M, - Enum8M, - Enum16M, - Enum32M, - Enum64M, - Enum128M, - EnumProcTraceMemDisable -} PROC_TRACE_MEM_SIZE; +#define MAX_TOPA_ENTRY_COUNT 2 + =20 /// /// Processor trace output scheme selection. @@ -70,7 +57,7 @@ typedef struct { } PROC_TRACE_DATA; =20 typedef struct { - UINT64 TopaEntry[MAX_TOPA_ENTRY_COUNT]; + RTIT_TOPA_TABLE_ENTRY TopaEntry[MAX_TOPA_ENTRY_COUNT]; } PROC_TRACE_TOPA_TABLE; =20 /** @@ -134,8 +121,8 @@ ProcTraceSupport ( // Check if ProcTraceMemorySize option is enabled (0xFF means disable by= user) // ProcTraceData =3D (PROC_TRACE_DATA *) ConfigData; - if ((ProcTraceData->ProcTraceMemSize >=3D EnumProcTraceMemDisable) || - (ProcTraceData->ProcTraceOutputScheme >=3D OutputSchemeInvalid)) { + if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) || + (ProcTraceData->ProcTraceOutputScheme > ProcTraceOutputSchemeToPA)) { return FALSE; } =20 @@ -186,7 +173,6 @@ ProcTraceInitialize ( IN BOOLEAN State ) { - UINT64 MsrValue; UINT32 MemRegionSize; UINTN Pages; UINTN Alignment; @@ -199,6 +185,11 @@ ProcTraceInitialize ( PROC_TRACE_TOPA_TABLE *TopaTable; PROC_TRACE_DATA *ProcTraceData; BOOLEAN FirstIn; + MSR_IA32_RTIT_CTL_REGISTER CtrlReg; + MSR_IA32_RTIT_STATUS_REGISTER StatusReg; + MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg; + MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg; + RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr; =20 ProcTraceData =3D (PROC_TRACE_DATA *) ConfigData; =20 @@ -221,29 +212,28 @@ ProcTraceInitialize ( // // Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CT= L[0]=3D=3D1b // - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - if ((MsrValue & BIT0) !=3D 0) { + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + if (CtrlReg.Bits.TraceEn !=3D 0) { /// /// Clear bit 0 in MSR IA32_RTIT_CTL (570) /// - MsrValue &=3D (UINT64) ~BIT0; + CtrlReg.Bits.TraceEn =3D 0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); =20 /// /// Clear MSR IA32_RTIT_STS (571h) to all zeros /// - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_STATUS); - MsrValue &=3D 0x0; + StatusReg.Uint64 =3D 0x0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_STATUS, - MsrValue + StatusReg.Uint64 ); } =20 @@ -309,37 +299,38 @@ ProcTraceInitialize ( // // Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8) // - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - MsrValue &=3D (UINT64) ~BIT8; + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + CtrlReg.Bits.ToPA =3D 0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); =20 // - // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with the allo= cated Memory Region + // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the alloc= ated Memory Region // - MsrValue =3D (UINT64) MemRegionBaseAddr; + OutputBaseReg.Bits.Base =3D (MemRegionBaseAddr >> 7) & 0x01FFFFFF; + OutputBaseReg.Bits.BaseHi =3D RShiftU64 ((UINT64) MemRegionBaseAddr, 3= 2) & 0xFFFFFFFF; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_BASE, - MsrValue + OutputBaseReg.Uint64 ); =20 // // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT= _MASK_PTRS (561h) // - MsrValue =3D (UINT64) MemRegionSize - 1; + OutputMaskPtrsReg.Bits.MaskOrTableOffset =3D ((MemRegionSize - 1) >> 7= ) & 0x01FFFFFF; + OutputMaskPtrsReg.Bits.OutputOffset =3D RShiftU64 ((UINT64) (MemRegion= Size - 1), 32) & 0xFFFFFFFF; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_MASK_PTRS, - MsrValue + OutputMaskPtrsReg.Uint64 ); - } =20 // @@ -408,55 +399,70 @@ ProcTraceInitialize ( } =20 TopaTable =3D (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr; - TopaTable->TopaEntry[0] =3D (UINT64) (MemRegionBaseAddr | ((ProcTraceD= ata->ProcTraceMemSize) << 6)) & ~BIT0; - TopaTable->TopaEntry[1] =3D (UINT64) TopaTableBaseAddr | BIT0; + TopaEntryPtr =3D &TopaTable->TopaEntry[0]; + TopaEntryPtr->Bits.Base =3D (MemRegionBaseAddr >> 12) & 0x000FFFFF; + TopaEntryPtr->Bits.BaseHi =3D RShiftU64 ((UINT64) MemRegionBaseAddr, 3= 2) & 0xFFFFFFFF; + TopaEntryPtr->Bits.Size =3D ProcTraceData->ProcTraceMemSize; + TopaEntryPtr->Bits.END =3D 0; + + TopaEntryPtr =3D &TopaTable->TopaEntry[1]; + TopaEntryPtr->Bits.Base =3D (TopaTableBaseAddr >> 12) & 0x000FFFFF; + TopaEntryPtr->Bits.BaseHi =3D RShiftU64 ((UINT64) TopaTableBaseAddr, 3= 2) & 0xFFFFFFFF; + TopaEntryPtr->Bits.END =3D 1; =20 // - // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with ToPA= base + // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA = base // - MsrValue =3D (UINT64) TopaTableBaseAddr; + OutputBaseReg.Bits.Base =3D (TopaTableBaseAddr >> 7) & 0x01FFFFFF; + OutputBaseReg.Bits.BaseHi =3D RShiftU64 ((UINT64) TopaTableBaseAddr, 3= 2) & 0xFFFFFFFF; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_BASE, - MsrValue + OutputBaseReg.Uint64 ); =20 // // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0 // + OutputMaskPtrsReg.Bits.MaskOrTableOffset =3D 0; + OutputMaskPtrsReg.Bits.OutputOffset =3D 0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_OUTPUT_MASK_PTRS, - 0x7F + OutputMaskPtrsReg.Uint64 ); // // Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToP= A (Bit 8) // - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - MsrValue |=3D BIT8; + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + CtrlReg.Bits.ToPA =3D 1; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); } =20 /// /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h) /// - MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); - MsrValue |=3D (UINT64) BIT0 + BIT2 + BIT3 + BIT13; + CtrlReg.Uint64 =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + CtrlReg.Bits.OS =3D 1; + CtrlReg.Bits.User =3D 1; + CtrlReg.Bits.BranchEn =3D 1; if (!State) { - MsrValue &=3D (UINT64) ~BIT0; + CtrlReg.Bits.TraceEn =3D 0; + } else { + CtrlReg.Bits.TraceEn =3D 1; } CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, MSR_IA32_RTIT_CTL, - MsrValue + CtrlReg.Uint64 ); =20 return RETURN_SUCCESS; --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel