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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:32 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QQdm0v8wJNqvsSeMGwBeLfBhYVUDF4+R9nmu2cYDt0Q=; b=rFlJLXTtgfVByfgk5YHLcDWr8bsIQTLIgB/NSBjc7P1/ON6d4XkLspXNvYRn8uJ5zO CJLw1eeJTMV758/OOcGQ7bzbeVi/vyafqzN0+MlTG2P5Oo0TUKYoXuMYwhwrgUmKP7Uy CnPSS6QnP3XXhvRz8QMn2sMGrrNVqHJ7M8v3sXj0xVpLWMm0MZuNbLr3QawRtIGlkHQB sPfC2tA5JGnxUoCOzJualKdvViGgtWKBHlzKmWahMDTrmEcmyM9Dxi2GW0KOIW7X8LNG 5GE7Z67M7vaso3cG4t0LbK1Qup/Dh24QOllBgyIedElH8XEZ723EIcsvWfLzs/uee0S0 j3JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QQdm0v8wJNqvsSeMGwBeLfBhYVUDF4+R9nmu2cYDt0Q=; b=crTOb8nxAQZEI4dWb2Sm+H/VN5MtwPTCsNbDEqWQkonMVOaLCKCmn+0bmzS+T/fFdR sF2iTJJJPasJsDL8/fWhhynoaYeEfsM3X+3NqmaghhWC9mXkkPXnRMwpo+Db/ckl8R5K 3qhWhlgMbh3cAp7CO22x3PNkQPNVTNPRWLajGv418NKEhftyFX//KHRCsam/gbWtPpRf +LauLLdB/WwHy9J2kIhP3wIZeEUmQtE/+McA0IAslosdRgNMOR1aAWUhKJsZL37+efVN WkN7SRWoKCoGfHkwv9l6X8gkWDBz6DICw0meZgl3ArRAOEGZK+Mzu9fHFAtGzCODqtRm RZFg== X-Gm-Message-State: AHPjjUiZlteRe83ZHDMlruwrauO7kKHUGDJIfOLZXHXeheDGkP7FvdKs MzO32JLUHx+ocpCm4zTNWw== X-Google-Smtp-Source: ADKCNb6HnHKMvHGCa+d4TTC4Lny0vtidG9w94V5Q/QPVqzZs2uXrlETV68VytzyjP09vHCOQgrBXfQ== X-Received: by 10.25.32.3 with SMTP id g3mr924100lfg.162.1504271073437; Fri, 01 Sep 2017 06:04:33 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:21 +0200 Message-Id: <1504271303-1782-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 09/11] Drivers/Spi/Devices/MvSpiFlash: Fix usage of erase size parameter X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Although, hitherto support allowed for using configurable EraseSize, the erase command was fixed to CMD_ERASE_64K. Also it was assumed that EraseSize equals SectorSize, which is not true for some flash devices. Fix both issues by adding new PCD (gMarvellTokenSpaceGuid.PcdSpiFlashPageSize) and using this parameter properly in MvSpiFlashUpdate routine instead of the EraseSize. Also erase command is adjusted to the settings. Update PortingGuide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Documentation/PortingGuide.txt | 3 +++ Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 26 +++++++++++++++++-= ---- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 6 +++++ .../Marvell/Drivers/Spi/Devices/MvSpiFlash.inf | 1 + Platform/Marvell/Marvell.dec | 1 + 5 files changed, 31 insertions(+), 6 deletions(-) diff --git a/Platform/Marvell/Documentation/PortingGuide.txt b/Platform/Mar= vell/Documentation/PortingGuide.txt index 3b79bd2..f637fee 100644 --- a/Platform/Marvell/Documentation/PortingGuide.txt +++ b/Platform/Marvell/Documentation/PortingGuide.txt @@ -297,6 +297,9 @@ Folowing PCDs for spi flash driver configuration must b= e set properly: - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize (Size of SPI flash page) =20 + - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize + (Size of SPI flash sector, 65536 bytes by default) + - gMarvellTokenSpaceGuid.PcdSpiFlashId (Id of SPI flash) =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index 9a04493..f3fdba4 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -191,7 +191,21 @@ MvSpiFlashErase ( return EFI_DEVICE_ERROR; } =20 - Cmd[0] =3D CMD_ERASE_64K; + switch (EraseSize) { + case SPI_ERASE_SIZE_4K: + Cmd[0] =3D CMD_ERASE_4K; + break; + case SPI_ERASE_SIZE_32K: + Cmd[0] =3D CMD_ERASE_32K; + break; + case SPI_ERASE_SIZE_64K: + Cmd[0] =3D CMD_ERASE_64K; + break; + default: + DEBUG ((DEBUG_ERROR, "MvSpiFlash: Invalid EraseSize parameter\n")); + return EFI_INVALID_PARAMETER; + } + while (Length) { EraseAddr =3D Offset; =20 @@ -353,14 +367,14 @@ MvSpiFlashUpdate ( ) { EFI_STATUS Status; - UINT64 EraseSize, ToUpdate, Scale =3D 1; + UINT64 SectorSize, ToUpdate, Scale =3D 1; UINT8 *TmpBuf, *End; =20 - EraseSize =3D PcdGet64 (PcdSpiFlashEraseSize); + SectorSize =3D PcdGet64 (PcdSpiFlashSectorSize); =20 End =3D Buf + ByteCount; =20 - TmpBuf =3D (UINT8 *)AllocateZeroPool (EraseSize); + TmpBuf =3D (UINT8 *)AllocateZeroPool (SectorSize); if (TmpBuf =3D=3D NULL) { DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); return EFI_OUT_OF_RESOURCES; @@ -370,9 +384,9 @@ MvSpiFlashUpdate ( Scale =3D (End - Buf) / 100; =20 for (; Buf < End; Buf +=3D ToUpdate, Offset +=3D ToUpdate) { - ToUpdate =3D MIN((UINT64)(End - Buf), EraseSize); + ToUpdate =3D MIN((UINT64)(End - Buf), SectorSize); Print (L" \rUpdating, %d%%", 100 - (End - Buf) / Scale); - Status =3D MvSpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buf, TmpBuf= , EraseSize); + Status =3D MvSpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buf, TmpBuf= , SectorSize); =20 if (EFI_ERROR (Status)) { DEBUG((DEBUG_ERROR, "SpiFlash: Error while updating\n")); diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.h index 3889643..646598a 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h @@ -57,6 +57,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_READ_ARRAY_FAST 0x0b #define CMD_PAGE_PROGRAM 0x02 #define CMD_BANK_WRITE 0xc5 +#define CMD_ERASE_4K 0x20 +#define CMD_ERASE_32K 0x52 #define CMD_ERASE_64K 0xd8 #define CMD_4B_ADDR_ENABLE 0xb7 =20 @@ -66,6 +68,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #define SPI_TRANSFER_BEGIN 0x01 // Assert CS before transfer #define SPI_TRANSFER_END 0x02 // Deassert CS after transfe= rs =20 +#define SPI_ERASE_SIZE_4K 4096 +#define SPI_ERASE_SIZE_32K 32768 +#define SPI_ERASE_SIZE_64K 65536 + #define SPI_FLASH_16MB_BOUN 0x1000000 =20 typedef enum { diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf b/Platform= /Marvell/Drivers/Spi/Devices/MvSpiFlash.inf index d035d47..4519b02 100644 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf @@ -58,6 +58,7 @@ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize gMarvellTokenSpaceGuid.PcdSpiFlashPageSize gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd + gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize =20 [Protocols] gMarvellSpiMasterProtocolGuid diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 869e376..fc00f1a 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -127,6 +127,7 @@ gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|0|UINT32|0x3000053 gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 + gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize|65536|UINT64|0x3000059 gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel