From nobody Thu Dec 26 12:05:45 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 15045821856821022.9367990042456; Mon, 4 Sep 2017 20:29:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 012BD21EA35B8; Mon, 4 Sep 2017 20:26:55 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 089EE21EA35A5 for ; Mon, 4 Sep 2017 20:26:52 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP; 04 Sep 2017 20:29:40 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.239.196.73]) by fmsmga005.fm.intel.com with ESMTP; 04 Sep 2017 20:29:39 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,477,1498546800"; d="scan'208";a="147473575" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Tue, 5 Sep 2017 11:29:32 +0800 Message-Id: <1504582173-9088-2-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504582173-9088-1-git-send-email-jiewen.yao@intel.com> References: <1504582173-9088-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 1/2] IntelSiliconPkg/Vtd: Support CSM usage. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Remove zero address check in IoMmuMap. The reason is that a CSM legacy driver may use legacy memory for DMA. As such, the legacyBios need allow below 1M to the legacy device. This patch also fixed some typo. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- IntelSiliconPkg/IntelVTdDxe/BmDma.c | 8 ++++---- IntelSiliconPkg/IntelVTdDxe/TranslationTable.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/IntelSiliconPkg/IntelVTdDxe/BmDma.c b/IntelSiliconPkg/IntelVTd= Dxe/BmDma.c index 5dcee00..7a5f361 100644 --- a/IntelSiliconPkg/IntelVTdDxe/BmDma.c +++ b/IntelSiliconPkg/IntelVTdDxe/BmDma.c @@ -77,14 +77,14 @@ IoMmuMap ( EFI_PHYSICAL_ADDRESS DmaMemoryTop; BOOLEAN NeedRemap; =20 - DEBUG ((DEBUG_VERBOSE, "IoMmuMap: =3D=3D> 0x%08x - 0x%08x (%x)\n", HostA= ddress, NumberOfBytes, Operation)); - - if (HostAddress =3D=3D NULL || NumberOfBytes =3D=3D NULL || DeviceAddres= s =3D=3D NULL || + if (NumberOfBytes =3D=3D NULL || DeviceAddress =3D=3D NULL || Mapping =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", EFI_INVALID_PARAMETER)); return EFI_INVALID_PARAMETER; } =20 + DEBUG ((DEBUG_VERBOSE, "IoMmuMap: =3D=3D> 0x%08x - 0x%08x (%x)\n", HostA= ddress, *NumberOfBytes, Operation)); + // // Make sure that Operation is valid // @@ -135,7 +135,7 @@ IoMmuMap ( if (NeedRemap) { // // Common Buffer operations can not be remapped. If the common buff= er - // if above 4GB, then it is not possible to generate a mapping, so r= eturn + // is above 4GB, then it is not possible to generate a mapping, so r= eturn // an error. // DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", EFI_UNSUPPORTED)); diff --git a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c b/IntelSiliconP= kg/IntelVTdDxe/TranslationTable.c index cd3111c..ccecc95 100644 --- a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c +++ b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c @@ -891,7 +891,7 @@ SetAccessAttribute ( =20 SecondLevelPagingEntry =3D NULL; =20 - DEBUG ((DEBUG_INFO,"SetAccessAttribute (S%04x B%02x D%02x F%02x) (0x%016= lx - 0x%08x, %x)\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, Sour= ceId.Bits.Function, BaseAddress, (UINTN)Length, IoMmuAccess)); + DEBUG ((DEBUG_VERBOSE,"SetAccessAttribute (S%04x B%02x D%02x F%02x) (0x%= 016lx - 0x%08x, %x)\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, S= ourceId.Bits.Function, BaseAddress, (UINTN)Length, IoMmuAccess)); =20 VtdIndex =3D FindVtdIndexByPciDevice (Segment, SourceId, &ExtContextEntr= y, &ContextEntry); if (VtdIndex =3D=3D (UINTN)-1) { --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 12:05:45 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150458218748177.13244333077182; Mon, 4 Sep 2017 20:29:47 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4948421EA35BB; Mon, 4 Sep 2017 20:26:55 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E763521EA35B5 for ; Mon, 4 Sep 2017 20:26:52 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP; 04 Sep 2017 20:29:41 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.239.196.73]) by fmsmga005.fm.intel.com with ESMTP; 04 Sep 2017 20:29:40 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,477,1498546800"; d="scan'208";a="147473579" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Tue, 5 Sep 2017 11:29:33 +0800 Message-Id: <1504582173-9088-3-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504582173-9088-1-git-send-email-jiewen.yao@intel.com> References: <1504582173-9088-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 2/2] IntelFramdworkModulePkg/LegacyBios: Add IoMmu Support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" If IOMMU is enabled, the legacy BIOS need allow the legacy memory access by the legacy device. The legacy memory is below 1M memory and HighPmm memory. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf | 1 + IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h | 1 + IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c | 72 +++++= ++++++++++++++- 3 files changed, 73 insertions(+), 1 deletion(-) diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf b/= IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf index 4ca412a..48473a0 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf @@ -137,6 +137,7 @@ gEfiLegacyBiosProtocolGuid ## PRODUCES gEfiSerialIoProtocolGuid ## CONSUMES gEfiSioProtocolGuid ## CONSUMES + gEdkiiIoMmuProtocolGuid ## CONSUMES =20 [Pcd] gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion= ## CONSUMES diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.= h b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h index 069646b..fe9dd74 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h @@ -47,6 +47,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include #include #include +#include =20 #include #include diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c b/IntelF= rameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c index c4c77ec..8ffdf0c 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c @@ -41,7 +41,7 @@ BOOLEAN mIgnoreBbsUpdateFlag; BOOLEAN mVgaInstallationInProgress =3D FALSE; UINT32 mRomCount =3D 0x00; ROM_INSTANCE_ENTRY mRomEntry[ROM_MAX_ENTRIES]; - +EDKII_IOMMU_PROTOCOL *mIoMmu; =20 /** Query shadowed legacy ROM parameters registered by RomShadow() previousl= y. @@ -2697,6 +2697,61 @@ Done: } =20 /** + Let IOMMU grant DMA access for the PCI device. + + @param PciHandle The EFI handle for the PCI device. + @param HostAddress The system memory address to map to the PC= I controller. + @param NumberOfBytes The number of bytes to map. + + @retval EFI_SUCCESS The DMA access is granted. +**/ +EFI_STATUS +IoMmuGrantAccess ( + IN EFI_HANDLE PciHandle, + IN EFI_PHYSICAL_ADDRESS HostAddress, + IN UINTN NumberOfBytes + ) +{ + EFI_PHYSICAL_ADDRESS DeviceAddress; + VOID *Mapping; + EFI_STATUS Status; + + if (PciHandle =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + Status =3D EFI_SUCCESS; + if (mIoMmu =3D=3D NULL) { + gBS->LocateProtocol (&gEdkiiIoMmuProtocolGuid, NULL, (VOID **)&mIoMmu); + } + if (mIoMmu !=3D NULL) { + Status =3D mIoMmu->Map ( + mIoMmu, + EdkiiIoMmuOperationBusMasterCommonBuffer, + (VOID *)(UINTN)HostAddress, + &NumberOfBytes, + &DeviceAddress, + &Mapping + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuMap - %r\n", Status)); + } else { + ASSERT (DeviceAddress =3D=3D HostAddress); + Status =3D mIoMmu->SetAttribute ( + mIoMmu, + PciHandle, + Mapping, + EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuSetAttribute - %r\n", Statu= s)); + } + } + } + return Status; +} + +/** Load a legacy PC-AT OPROM on the PciHandle device. Return information about how many disks were added by the OPROM and the shadow address and size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C: @@ -2978,6 +3033,21 @@ LegacyBiosInstallPciRom ( RuntimeImageLength =3D Pcir->MaxRuntimeImageLength * 512; } } + + // + // Grant access for below 1M + // BDA/EBDA/LowPMM and scratch memory for OPROM. + // + IoMmuGrantAccess (PciHandle, 0, SIZE_1MB); + // + // Grant access for HiPmm + // + IoMmuGrantAccess ( + PciHandle, + Private->IntThunk->EfiToLegacy16InitTable.HiPmmMemory, + Private->IntThunk->EfiToLegacy16InitTable.HiPmmMemorySizeInBytes + ); + // // Shadow and initialize the OpROM. // --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel