From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504883047240130.50473274769934; Fri, 8 Sep 2017 08:04:07 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EF47E21CEB11B; Fri, 8 Sep 2017 08:01:11 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7A31020945C1A for ; Fri, 8 Sep 2017 08:01:10 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:02 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:02 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511576" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:44 +0800 Message-Id: <1504883034-22060-2-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 01/11] MdeModulePkg/Include: Add IOMMU_PPI. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This IOMMU_PPI is to provide IOMMU abstraction in PEI. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- MdeModulePkg/Include/Ppi/IoMmu.h | 196 ++++++++++++++++++++ 1 file changed, 196 insertions(+) diff --git a/MdeModulePkg/Include/Ppi/IoMmu.h b/MdeModulePkg/Include/Ppi/Io= Mmu.h new file mode 100644 index 0000000..5303d68 --- /dev/null +++ b/MdeModulePkg/Include/Ppi/IoMmu.h @@ -0,0 +1,196 @@ +/** @file + PEI IOMMU PPI. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made availabl= e under +the terms and conditions of the BSD License that accompanies this distribu= tion. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + +**/ + + +#ifndef __PEI_IOMMU_H__ +#define __PEI_IOMMU_H__ + +// +// for EFI_ALLOCATE_TYPE +// +#include + +// +// Include protocol for common definition +// EDKII_IOMMU_ACCESS_xxx +// EDKII_IOMMU_OPERATION +// +#include + +// +// IOMMU Ppi GUID value +// +#define EDKII_IOMMU_PPI_GUID \ + { \ + 0x70b0af26, 0xf847, 0x4bb6, { 0xaa, 0xb9, 0xcd, 0xe8, 0x4f, 0xc6, 0x= 14, 0x31 } \ + } + +// +// Forward reference for pure ANSI compatability +// +typedef struct _EDKII_IOMMU_PPI EDKII_IOMMU_PPI; + +// +// Revision The revision to which the IOMMU interface adheres. +// All future revisions must be backwards compatible. +// If a future version is not back wards compatible it is not the= same GUID. +// +#define EDKII_IOMMU_PPI_REVISION 0x00010000 + +/** + Set IOMMU attribute for a system memory. + + If the IOMMU PPI exists, the system memory cannot be used + for DMA by default. + + When a device requests a DMA access for a system memory, + the device driver need use SetAttribute() to update the IOMMU + attribute to request DMA access (read and/or write). + + @param[in] This The PPI instance pointer. + @param[in] Mapping The mapping value returned from Map(). + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by DeviceAddress and Length. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned = by Map(). + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by Mapping. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_IOMMU_SET_ATTRIBUTE)( + IN EDKII_IOMMU_PPI *This, + IN VOID *Mapping, + IN UINT64 IoMmuAccess + ); + +/** + Provides the controller-specific addresses required to access system mem= ory from a + DMA bus master. + + @param This The PPI instance pointer. + @param Operation Indicates if the bus master is going to re= ad or write to system memory. + @param HostAddress The system memory address to map to the PC= I controller. + @param NumberOfBytes On input the number of bytes to map. On ou= tput the number of bytes + that were mapped. + @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned Numb= erOfBytes. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a comm= on buffer. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. + @retval EFI_DEVICE_ERROR The system hardware could not map the requ= ested address. + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_IOMMU_MAP)( + IN EDKII_IOMMU_PPI *This, + IN EDKII_IOMMU_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +/** + Completes the Map() operation and releases any corresponding resources. + + @param This The PPI instance pointer. + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned b= y Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target s= ystem memory. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_IOMMU_UNMAP)( + IN EDKII_IOMMU_PPI *This, + IN VOID *Mapping + ); + +/** + Allocates pages that are suitable for an OperationBusMasterCommonBuffer = or + OperationBusMasterCommonBuffer64 mapping. + + @param This The PPI instance pointer. + @param MemoryType The type of memory to allocate, EfiBootSer= vicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory = address of the + allocated range. + @param Attributes The requested bit mask of attributes for t= he allocated range. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal = attribute bits are + MEMORY_WRITE_COMBINE and MEMORY_CACHED. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_IOMMU_ALLOCATE_BUFFER)( + IN EDKII_IOMMU_PPI *This, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + IN OUT VOID **HostAddress, + IN UINT64 Attributes + ); + +/** + Frees memory that was allocated with AllocateBuffer(). + + @param This The protocol instance pointer. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allo= cated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress = and Pages + was not allocated with AllocateBuffer(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_IOMMU_FREE_BUFFER)( + IN EDKII_IOMMU_PPI *This, + IN UINTN Pages, + IN VOID *HostAddress + ); + +/// +/// IOMMU PPI structure. +/// +struct _EDKII_IOMMU_PPI { + UINT64 Revision; + EDKII_PEI_IOMMU_SET_ATTRIBUTE SetAttribute; + EDKII_PEI_IOMMU_MAP Map; + EDKII_PEI_IOMMU_UNMAP Unmap; + EDKII_PEI_IOMMU_ALLOCATE_BUFFER AllocateBuffer; + EDKII_PEI_IOMMU_FREE_BUFFER FreeBuffer; +}; + +/// +/// IOMMU PPI GUID variable. +/// +extern EFI_GUID gEdkiiIoMmuPpiGuid; + +#endif --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 15048830497801017.2382999124467; Fri, 8 Sep 2017 08:04:09 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3DB0621D492C9; Fri, 8 Sep 2017 08:01:12 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4D28020945BFC for ; Fri, 8 Sep 2017 08:01:11 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:03 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:02 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511587" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:45 +0800 Message-Id: <1504883034-22060-3-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 02/11] MdeModulePkg/Dec: Add IOMMU_PPI GUID. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- MdeModulePkg/MdeModulePkg.dec | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 593bff3..403a66a 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -431,6 +431,9 @@ ## Include/Ppi/SdMmcHostController.h gEdkiiPeiSdMmcHostControllerPpiGuid =3D { 0xb30dfeed, 0x947f, 0x4396, { = 0xb1, 0x5a, 0xdf, 0xbd, 0xb9, 0x16, 0xdc, 0x24 }} =20 + ## Include/Ppi/IoMmu.h + gEdkiiIoMmuPpiGuid =3D { 0x70b0af26, 0xf847, 0x4bb6, { 0xaa, 0xb9, 0xcd,= 0xe8, 0x4f, 0xc6, 0x14, 0x31 } } + [Protocols] ## Load File protocol provides capability to load and unload EFI image i= nto memory and execute it. # Include/Protocol/LoadPe32Image.h --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504883052996522.2434243058839; Fri, 8 Sep 2017 08:04:12 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7A51821D492D2; Fri, 8 Sep 2017 08:01:14 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 332D221D492C5 for ; Fri, 8 Sep 2017 08:01:12 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:04 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:03 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511615" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:46 +0800 Message-Id: <1504883034-22060-4-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 03/11] IntelSiliconPkg/Vtd.h: Add definition for PMR. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add missing PMR definition in VTd spec. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- IntelSiliconPkg/Include/IndustryStandard/Vtd.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/IntelSiliconPkg/Include/IndustryStandard/Vtd.h b/IntelSiliconP= kg/Include/IndustryStandard/Vtd.h index 3b7012c..cfead61 100644 --- a/IntelSiliconPkg/Include/IndustryStandard/Vtd.h +++ b/IntelSiliconPkg/Include/IndustryStandard/Vtd.h @@ -247,6 +247,12 @@ typedef union { =20 #define R_FRCD_REG 0x00 // + FRO =20 +#define R_PMEN_ENABLE_REG 0x64 +#define R_PMEN_LOW_BASE_REG 0x68 +#define R_PMEN_LOW_LIMITE_REG 0x6C +#define R_PMEN_HIGH_BASE_REG 0x70 +#define R_PMEN_HIGH_LIMITE_REG 0x78 + typedef union { struct { UINT8 ND:3; // Number of domains supported --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504883056120270.1154308073162; Fri, 8 Sep 2017 08:04:16 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B387421D492DD; Fri, 8 Sep 2017 08:01:14 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0833621CEB103 for ; Fri, 8 Sep 2017 08:01:13 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:05 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:04 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511635" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:47 +0800 Message-Id: <1504883034-22060-5-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When VTd translation is enabled, PMR can be disable. Or the DMA will be blocked by PMR. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 51 +++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c b/IntelSiliconPkg/IntelVT= dDxe/VtdReg.c index 7402d81..1404af7 100644 --- a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c +++ b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c @@ -196,6 +196,39 @@ PrepareVtdConfig ( } =20 /** + Disable PMR in all VTd engine. +**/ +VOID +DisablePmr ( + VOID + ) +{ + UINT32 Reg32; + VTD_CAP_REG CapReg; + UINTN Index; + + DEBUG ((DEBUG_INFO,"DisablePmr\n")); + for (Index =3D 0; Index < mVtdUnitNumber; Index++) { + CapReg.Uint64 =3D MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAd= dress + R_CAP_REG); + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { + continue ; + } + + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_PMEN_ENABLE_REG); + if ((Reg32 & BIT0) !=3D 0) { + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_= ENABLE_REG, 0x0); + do { + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddres= s + R_PMEN_ENABLE_REG); + } while((Reg32 & BIT0) !=3D 0); + DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index)); + } else { + DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index)); + } + } + return ; +} + +/** Enable DMAR translation. =20 @retval EFI_SUCCESS DMAR translation is enabled. @@ -259,6 +292,11 @@ EnableDmar ( DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index)); } =20 + // + // Need disable PMR, since we already setup translation table. + // + DisablePmr (); + mVtdEnabled =3D TRUE; =20 return EFI_SUCCESS; @@ -502,7 +540,7 @@ DumpVtdIfError ( for (Index =3D 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) { FrcdReg.Uint64[0] =3D MmioRead64 (mVtdUnitInformation[Num].VtdUnitBa= seAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG)); FrcdReg.Uint64[1] =3D MmioRead64 (mVtdUnitInformation[Num].VtdUnitBa= seAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UI= NT64))); - if ((FrcdReg.Uint64[0] !=3D 0) || (FrcdReg.Uint64[1] !=3D 0)) { + if (FrcdReg.Bits.F !=3D 0) { HasError =3D TRUE; } } @@ -511,6 +549,17 @@ DumpVtdIfError ( DEBUG((DEBUG_INFO, "\n#### ERROR ####\n")); DumpVtdRegs (Num); DEBUG((DEBUG_INFO, "#### ERROR ####\n\n")); + // + // Clear + // + for (Index =3D 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) { + FrcdReg.Uint64[1] =3D MmioRead64 (mVtdUnitInformation[Num].VtdUnit= BaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(= UINT64))); + if (FrcdReg.Bits.F !=3D 0) { + FrcdReg.Bits.F =3D 0; + MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((Cap= Reg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), FrcdReg.U= int64[1]); + } + MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_= REG, MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG)); + } } } } --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504883060202503.71390152902075; Fri, 8 Sep 2017 08:04:20 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id ED34F21D492E5; Fri, 8 Sep 2017 08:01:14 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CD71720945C1E for ; Fri, 8 Sep 2017 08:01:13 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:06 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:05 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511644" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:48 +0800 Message-Id: <1504883034-22060-6-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 05/11] IntelSiliconPkg/include: Add VTD_INFO PPI. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This VTD_INFO_PPI is to provide VTD information in PEI. As such, we can have a generic VTd driver. It is a lightweight version DMAR table, but it does not contain PCI device information. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- IntelSiliconPkg/Include/Ppi/VtdInfo.h | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/IntelSiliconPkg/Include/Ppi/VtdInfo.h b/IntelSiliconPkg/Includ= e/Ppi/VtdInfo.h new file mode 100644 index 0000000..e8be63f --- /dev/null +++ b/IntelSiliconPkg/Include/Ppi/VtdInfo.h @@ -0,0 +1,40 @@ +/** @file + The definition for VTD information PPI. + + This is a lightweight VTd information report in PEI phase. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __VTD_INFO_PPI_H__ +#define __VTD_INFO_PPI_H__ + +#define EDKII_VTD_INFO_PPI_GUID \ + { \ + 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x= 68, 0x4a } \ + } + +typedef struct _EDKII_VTD_INFO_PPI EDKII_VTD_INFO_PPI; + +#define EDKII_VTD_INFO_PPI_REVISION 0x00010000 + +struct _EDKII_VTD_INFO_PPI { + UINT64 Revision; + UINT8 HostAddressWidth; + UINT8 Reserved[3]; + UINT32 VTdEngineCount; + UINT64 VTdEngineAddress[1]; +}; + +extern EFI_GUID gEdkiiVTdInfoPpiGuid; + +#endif + --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504883063513908.8644854219788; Fri, 8 Sep 2017 08:04:23 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3072920945C1E; Fri, 8 Sep 2017 08:01:17 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B683621D492DE for ; Fri, 8 Sep 2017 08:01:14 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:07 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:06 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511652" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:49 +0800 Message-Id: <1504883034-22060-7-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 06/11] IntelSiliconPkg/dec: Add VTD_INFO PPI GUID X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- IntelSiliconPkg/IntelSiliconPkg.dec | 3 +++ 1 file changed, 3 insertions(+) diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec b/IntelSiliconPkg/IntelSil= iconPkg.dec index 2fc6379..941380a 100644 --- a/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/IntelSiliconPkg/IntelSiliconPkg.dec @@ -33,6 +33,9 @@ # Generic DXE Library / Driver can locate HOB(s) and add SMBIOS records = into SMBIOS table gIntelSmbiosDataHobGuid =3D { 0x798e722e, 0x15b2, 0x4e13, { 0x8a= , 0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }} =20 +[Ppis] + gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x6= 7, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } + [Protocols] gEdkiiPlatformVTdPolicyProtocolGuid =3D { 0x3d17e448, 0x466, 0x4e20, { 0= x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }} =20 --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504883067266451.3017544202967; Fri, 8 Sep 2017 08:04:27 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 66EBE21D492ED; Fri, 8 Sep 2017 08:01:17 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E8B5B21D492E9 for ; Fri, 8 Sep 2017 08:01:15 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:08 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:07 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511665" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:50 +0800 Message-Id: <1504883034-22060-8-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 07/11] IntelSiliconPkg: Add IntelVTdPmrPei. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PEIM is to produce IOMMU_PPI, so that PEI device driver can have better DAM management. This PEIM will setup VTD PMR register to protect most DRAM. It allocates a big chunk DMA buffer in the entrypoint, and only use this buffer for DMA. Any other region is DMA protected. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c | 314 ++++++++++ IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c | 615 +++++++++++++= +++++++ IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.h | 68 +++ IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf | 59 ++ IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.uni | 20 + IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni | 20 + 6 files changed, 1096 insertions(+) diff --git a/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c b/IntelSiliconPkg= /IntelVTdPmrPei/IntelVTdPmr.c new file mode 100644 index 0000000..ef08e29 --- /dev/null +++ b/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c @@ -0,0 +1,314 @@ +/** @file + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble under + the terms and conditions of the BSD License which accompanies this distr= ibution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "IntelVTdPmrPei.h" + +extern EDKII_VTD_INFO_PPI *mVTdInfoPpi; + +/** + Get protected low memory alignment. + + @param VtdUnitBaseAddress The base address of the VTd engine. + + @return protected low memory alignment. +**/ +UINT32 +GetPlmrAlignment ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Data32; + + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, 0xFFFFFFFF); + Data32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG); + Data32 =3D ~Data32 + 1; + + return Data32; +} + +/** + Get protected high memory alignment. + + @param VtdUnitBaseAddress The base address of the VTd engine. + + @return protected high memory alignment. +**/ +UINT64 +GetPhmrAlignment ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT64 Data64; + UINT8 HostAddressWidth; + + HostAddressWidth =3D mVTdInfoPpi->HostAddressWidth; + + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, 0xFFFFFFFFFFFFFF= FF); + Data64 =3D MmioRead64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG); + Data64 =3D ~Data64 + 1; + Data64 =3D Data64 & (LShiftU64 (1, HostAddressWidth) - 1); + + return Data64; +} + +/** + Get protected low memory alignment. + + @return protected low memory alignment. +**/ +UINT32 +GetLowMemoryAlignment ( + VOID + ) +{ + UINTN Index; + UINT32 Alignment; + UINT32 FinalAlignment; + + FinalAlignment =3D 0; + for (Index =3D 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) { + Alignment =3D GetPlmrAlignment ((UINTN)mVTdInfoPpi->VTdEngineAddress[I= ndex]); + if (FinalAlignment < Alignment) { + FinalAlignment =3D Alignment; + } + } + return FinalAlignment; +} + +/** + Get protected high memory alignment. + + @return protected high memory alignment. +**/ +UINT64 +GetHighMemoryAlignment ( + VOID + ) +{ + UINTN Index; + UINT64 Alignment; + UINT64 FinalAlignment; + + FinalAlignment =3D 0; + for (Index =3D 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) { + Alignment =3D GetPhmrAlignment ((UINTN)mVTdInfoPpi->VTdEngineAddress[I= ndex]); + if (FinalAlignment < Alignment) { + FinalAlignment =3D Alignment; + } + } + return FinalAlignment; +} + +/** + Enable PMR in the VTd engine. + + @param VtdUnitBaseAddress The base address of the VTd engine. + + @retval EFI_SUCCESS The PMR is enabled. + @retval EFI_UNSUPPORTED The PMR is not supported. +**/ +EFI_STATUS +EnablePmr ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Reg32; + VTD_CAP_REG CapReg; + + CapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_CAP_REG); + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { + return EFI_UNSUPPORTED; + } + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); + if ((Reg32 & BIT0) =3D=3D 0) { + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG, BIT31); + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); + } while((Reg32 & BIT0) =3D=3D 0); + } + + return EFI_SUCCESS; +} + +/** + Disable PMR in the VTd engine. + + @param VtdUnitBaseAddress The base address of the VTd engine. + + @retval EFI_SUCCESS The PMR is disabled. + @retval EFI_UNSUPPORTED The PMR is not supported. +**/ +EFI_STATUS +DisablePmr ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Reg32; + VTD_CAP_REG CapReg; + + CapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_CAP_REG); + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { + return EFI_UNSUPPORTED; + } + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); + if ((Reg32 & BIT0) !=3D 0) { + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG, 0x0); + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); + } while((Reg32 & BIT0) !=3D 0); + } + + return EFI_SUCCESS; +} + +/** + Set PMR region in the VTd engine. + + @param VtdUnitBaseAddress The base address of the VTd engine. + @param LowMemoryBase The protected low memory region base. + @param LowMemoryLength The protected low memory region length. + @param HighMemoryBase The protected high memory region base. + @param HighMemoryLength The protected high memory region length. + + @retval EFI_SUCCESS The PMR is set to protected region. + @retval EFI_UNSUPPORTED The PMR is not supported. +**/ +EFI_STATUS +SetPmrRegion ( + IN UINTN VtdUnitBaseAddress, + IN UINT32 LowMemoryBase, + IN UINT32 LowMemoryLength, + IN UINT64 HighMemoryBase, + IN UINT64 HighMemoryLength + ) +{ + VTD_CAP_REG CapReg; + UINT32 PlmrAlignment; + UINT64 PhmrAlignment; + + DEBUG ((DEBUG_INFO, "VtdUnitBaseAddress - 0x%x\n", VtdUnitBaseAddress)); + + CapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_CAP_REG); + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "PLMR/PHMR unsupported\n")); + return EFI_UNSUPPORTED; + } + + PlmrAlignment =3D GetPlmrAlignment (VtdUnitBaseAddress); + DEBUG ((DEBUG_INFO, "PlmrAlignment - 0x%x\n", PlmrAlignment)); + PhmrAlignment =3D GetPhmrAlignment (VtdUnitBaseAddress); + DEBUG ((DEBUG_INFO, "PhmrAlignment - 0x%lx\n", PhmrAlignment)); + + if ((LowMemoryBase !=3D ALIGN_VALUE(LowMemoryBase, PlmrAlignment)) || + (LowMemoryLength !=3D ALIGN_VALUE(LowMemoryLength, PlmrAlignment)) = || + (HighMemoryBase !=3D ALIGN_VALUE(HighMemoryBase, PhmrAlignment)) || + (HighMemoryLength !=3D ALIGN_VALUE(HighMemoryLength, PhmrAlignment))= ) { + DEBUG ((DEBUG_ERROR, "PLMR/PHMR alignment issue\n")); + return EFI_UNSUPPORTED; + } + + if (LowMemoryBase =3D=3D 0 && LowMemoryLength =3D=3D 0) { + LowMemoryBase =3D 0xFFFFFFFF; + } + if (HighMemoryBase =3D=3D 0 && HighMemoryLength =3D=3D 0) { + HighMemoryBase =3D 0xFFFFFFFFFFFFFFFF; + } + + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, LowMemoryBase); + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_LIMITE_REG, LowMemoryBase = + LowMemoryLength - 1); + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, HighMemoryBase= ); + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_LIMITE_REG, HighMemoryBase= + HighMemoryLength - 1); + + return EFI_SUCCESS; +} + +/** + Set DMA protected region. + + @param LowMemoryBase The protected low memory region base. + @param LowMemoryLength The protected low memory region length. + @param HighMemoryBase The protected high memory region base. + @param HighMemoryLength The protected high memory region length. + + @retval EFI_SUCCESS The DMA protection is set. + @retval EFI_UNSUPPORTED The DMA protection is not set. +**/ +EFI_STATUS +SetDmaProtectedRange ( + IN UINT32 LowMemoryBase, + IN UINT32 LowMemoryLength, + IN UINT64 HighMemoryBase, + IN UINT64 HighMemoryLength + ) +{ + UINTN Index; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "SetDmaProtectedRange - [0x%x, 0x%x] [0x%lx, 0x%lx]\= n", LowMemoryBase, LowMemoryLength, HighMemoryBase, HighMemoryLength)); + + for (Index =3D 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) { + DisablePmr ((UINTN)mVTdInfoPpi->VTdEngineAddress[Index]); + Status =3D SetPmrRegion ( + (UINTN)mVTdInfoPpi->VTdEngineAddress[Index], + LowMemoryBase, + LowMemoryLength, + HighMemoryBase, + HighMemoryLength + ); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D EnablePmr ((UINTN)mVTdInfoPpi->VTdEngineAddress[Index]); + if (EFI_ERROR(Status)) { + return Status; + } + } + + return EFI_SUCCESS; +} + +/** + Diable DMA protection. + + @retval DMA protection is disabled. +**/ +EFI_STATUS +DisableDmaProtection ( + VOID + ) +{ + UINTN Index; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "DisableDmaProtection\n")); + + for (Index =3D 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) { + Status =3D DisablePmr ((UINTN)mVTdInfoPpi->VTdEngineAddress[Index]); + if (EFI_ERROR(Status)) { + return Status; + } + } + + return EFI_SUCCESS; +} diff --git a/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c b/IntelSilicon= Pkg/IntelVTdPmrPei/IntelVTdPmrPei.c new file mode 100644 index 0000000..d118b7e --- /dev/null +++ b/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c @@ -0,0 +1,615 @@ +/** @file + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble under + the terms and conditions of the BSD License which accompanies this distr= ibution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "IntelVTdPmrPei.h" + +#define TOTAL_DMA_BUFFER_SIZE SIZE_4MB + +EDKII_VTD_INFO_PPI *mVTdInfoPpi; +UINTN mDmaBufferBase; +UINTN mDmaBufferSize =3D TOTAL_DMA_BUFFER_SIZE; +UINTN mDmaBufferCurrentTop; +UINTN mDmaBufferCurrentBottom; + +#define MAP_INFO_SIGNATURE SIGNATURE_32 ('D', 'M', 'A', 'P') +typedef struct { + UINT32 Signature; + EDKII_IOMMU_OPERATION Operation; + UINTN NumberOfBytes; + EFI_PHYSICAL_ADDRESS HostAddress; + EFI_PHYSICAL_ADDRESS DeviceAddress; +} MAP_INFO; + +/** + + PEI Memory Layout: + + +------------------+ <------- EfiMemoryTop + | PEI allocated | + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + ^ | Commom Buf | + | | -------------- | + DMA Buffer | * DMA FREE * | + | | -------------- | + V | Read/Write Buf | + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + | PEI allocated | + | -------------- | <------- EfiFreeMemoryTop + | * PEI FREE * | + | -------------- | <------- EfiFreeMemoryBottom + | hob | + | -------------- | + | Stack | + +------------------+ <------- EfiMemoryBottom / Stack Bottom + + +------------------+ + | Mem Alloc Hob | + +------------------+ + +**/ + + +/** + Set IOMMU attribute for a system memory. + + If the IOMMU PPI exists, the system memory cannot be used + for DMA by default. + + When a device requests a DMA access for a system memory, + the device driver need use SetAttribute() to update the IOMMU + attribute to request DMA access (read and/or write). + + @param[in] This The PPI instance pointer. + @param[in] Mapping The mapping value returned from Map(). + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by DeviceAddress and Length. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned = by Map(). + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by Mapping. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. + +**/ +EFI_STATUS +EFIAPI +PeiIoMmuSetAttribute ( + IN EDKII_IOMMU_PPI *This, + IN VOID *Mapping, + IN UINT64 IoMmuAccess + ) +{ + return EFI_SUCCESS; +} + +/** + Provides the controller-specific addresses required to access system mem= ory from a + DMA bus master. + + @param This The PPI instance pointer. + @param Operation Indicates if the bus master is going to re= ad or write to system memory. + @param HostAddress The system memory address to map to the PC= I controller. + @param NumberOfBytes On input the number of bytes to map. On ou= tput the number of bytes + that were mapped. + @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned Numb= erOfBytes. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a comm= on buffer. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. + @retval EFI_DEVICE_ERROR The system hardware could not map the requ= ested address. + +**/ +EFI_STATUS +EFIAPI +PeiIoMmuMap ( + IN EDKII_IOMMU_PPI *This, + IN EDKII_IOMMU_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + MAP_INFO *MapInfo; + UINTN Length; + + if (Operation =3D=3D EdkiiIoMmuOperationBusMasterCommonBuffer || + Operation =3D=3D EdkiiIoMmuOperationBusMasterCommonBuffer64) { + *DeviceAddress =3D (UINTN)HostAddress; + *Mapping =3D 0; + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_VERBOSE, "PeiIoMmuMap - HostAddress - 0x%x, NumberOfBytes = - %x\n", HostAddress, *NumberOfBytes)); + DEBUG ((DEBUG_VERBOSE, " mDmaBufferCurrentTop - %x\n", mDmaBufferCurren= tTop)); + DEBUG ((DEBUG_VERBOSE, " mDmaBufferCurrentBottom - %x\n", mDmaBufferCur= rentBottom)); + + Length =3D *NumberOfBytes + sizeof(MAP_INFO); + if (Length > mDmaBufferCurrentTop - mDmaBufferCurrentBottom) { + DEBUG ((DEBUG_ERROR, "PeiIoMmuMap - OUT_OF_RESOURCE\n")); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + *DeviceAddress =3D mDmaBufferCurrentBottom; + mDmaBufferCurrentBottom +=3D Length; + + MapInfo =3D (VOID *)(UINTN)(*DeviceAddress + *NumberOfBytes); + MapInfo->Signature =3D MAP_INFO_SIGNATURE; + MapInfo->Operation =3D Operation; + MapInfo->NumberOfBytes =3D *NumberOfBytes; + MapInfo->HostAddress =3D (UINTN)HostAddress; + MapInfo->DeviceAddress =3D *DeviceAddress; + *Mapping =3D MapInfo; + DEBUG ((DEBUG_VERBOSE, " Op(%x):DeviceAddress - %x, Mapping - %x\n", Op= eration, (UINTN)*DeviceAddress, MapInfo)); + + // + // If this is a read operation from the Bus Master's point of view, + // then copy the contents of the real buffer into the mapped buffer + // so the Bus Master can read the contents of the real buffer. + // + if (Operation =3D=3D EdkiiIoMmuOperationBusMasterRead || + Operation =3D=3D EdkiiIoMmuOperationBusMasterRead64) { + CopyMem ( + (VOID *) (UINTN) MapInfo->DeviceAddress, + (VOID *) (UINTN) MapInfo->HostAddress, + MapInfo->NumberOfBytes + ); + } + + return EFI_SUCCESS; +} + +/** + Completes the Map() operation and releases any corresponding resources. + + @param This The PPI instance pointer. + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned b= y Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target s= ystem memory. +**/ +EFI_STATUS +EFIAPI +PeiIoMmuUnmap ( + IN EDKII_IOMMU_PPI *This, + IN VOID *Mapping + ) +{ + MAP_INFO *MapInfo; + UINTN Length; + + if (Mapping =3D=3D NULL) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_VERBOSE, "PeiIoMmuUnmap - Mapping - %x\n", Mapping)); + DEBUG ((DEBUG_VERBOSE, " mDmaBufferCurrentTop - %x\n", mDmaBufferCurren= tTop)); + DEBUG ((DEBUG_VERBOSE, " mDmaBufferCurrentBottom - %x\n", mDmaBufferCur= rentBottom)); + + MapInfo =3D Mapping; + ASSERT (MapInfo->Signature =3D=3D MAP_INFO_SIGNATURE); + DEBUG ((DEBUG_VERBOSE, " Op(%x):DeviceAddress - %x, NumberOfBytes - %x\= n", MapInfo->Operation, (UINTN)MapInfo->DeviceAddress, MapInfo->NumberOfByt= es)); + + // + // If this is a write operation from the Bus Master's point of view, + // then copy the contents of the mapped buffer into the real buffer + // so the processor can read the contents of the real buffer. + // + if (MapInfo->Operation =3D=3D EdkiiIoMmuOperationBusMasterWrite || + MapInfo->Operation =3D=3D EdkiiIoMmuOperationBusMasterWrite64) { + CopyMem ( + (VOID *) (UINTN) MapInfo->HostAddress, + (VOID *) (UINTN) MapInfo->DeviceAddress, + MapInfo->NumberOfBytes + ); + } + + Length =3D MapInfo->NumberOfBytes + sizeof(MAP_INFO); + if (mDmaBufferCurrentBottom =3D=3D MapInfo->DeviceAddress + Length) { + mDmaBufferCurrentBottom -=3D Length; + } + + return EFI_SUCCESS; +} + +/** + Allocates pages that are suitable for an OperationBusMasterCommonBuffer = or + OperationBusMasterCommonBuffer64 mapping. + + @param This The PPI instance pointer. + @param MemoryType The type of memory to allocate, EfiBootSer= vicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory = address of the + allocated range. + @param Attributes The requested bit mask of attributes for t= he allocated range. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal = attribute bits are + MEMORY_WRITE_COMBINE and MEMORY_CACHED. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +EFI_STATUS +EFIAPI +PeiIoMmuAllocateBuffer ( + IN EDKII_IOMMU_PPI *This, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + IN OUT VOID **HostAddress, + IN UINT64 Attributes + ) +{ + UINTN Length; + + DEBUG ((DEBUG_VERBOSE, "PeiIoMmuAllocateBuffer - page - %x\n", Pages)); + DEBUG ((DEBUG_VERBOSE, " mDmaBufferCurrentTop - %x\n", mDmaBufferCurren= tTop)); + DEBUG ((DEBUG_VERBOSE, " mDmaBufferCurrentBottom - %x\n", mDmaBufferCur= rentBottom)); + + Length =3D EFI_PAGES_TO_SIZE(Pages); + if (Length > mDmaBufferCurrentTop - mDmaBufferCurrentBottom) { + DEBUG ((DEBUG_ERROR, "PeiIoMmuAllocateBuffer - OUT_OF_RESOURCE\n")); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + *HostAddress =3D (VOID *)(UINTN)(mDmaBufferCurrentTop - Length); + mDmaBufferCurrentTop -=3D Length; + + DEBUG ((DEBUG_VERBOSE, "PeiIoMmuAllocateBuffer - allocate - %x\n", *Host= Address)); + return EFI_SUCCESS; +} + +/** + Frees memory that was allocated with AllocateBuffer(). + + @param This The PPI instance pointer. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allo= cated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress = and Pages + was not allocated with AllocateBuffer(). + +**/ +EFI_STATUS +EFIAPI +PeiIoMmuFreeBuffer ( + IN EDKII_IOMMU_PPI *This, + IN UINTN Pages, + IN VOID *HostAddress + ) +{ + UINTN Length; + + DEBUG ((DEBUG_VERBOSE, "PeiIoMmuFreeBuffer - page - %x, HostAddr - %x\n"= , Pages, HostAddress)); + DEBUG ((DEBUG_VERBOSE, " mDmaBufferCurrentTop - %x\n", mDmaBufferCurren= tTop)); + DEBUG ((DEBUG_VERBOSE, " mDmaBufferCurrentBottom - %x\n", mDmaBufferCur= rentBottom)); + + Length =3D EFI_PAGES_TO_SIZE(Pages); + if ((UINTN)HostAddress =3D=3D mDmaBufferCurrentTop) { + mDmaBufferCurrentTop +=3D Length; + } + + return EFI_SUCCESS; +} + +EDKII_IOMMU_PPI mIoMmuPpi =3D { + EDKII_IOMMU_PPI_REVISION, + PeiIoMmuSetAttribute, + PeiIoMmuMap, + PeiIoMmuUnmap, + PeiIoMmuAllocateBuffer, + PeiIoMmuFreeBuffer, +}; + +CONST EFI_PEI_PPI_DESCRIPTOR mIoMmuPpiList =3D { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEdkiiIoMmuPpiGuid, + (VOID *) &mIoMmuPpi +}; + +#define MEMORY_ATTRIBUTE_MASK (EFI_RESOURCE_ATTRIBUTE_PRESENT | \ + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \ + EFI_RESOURCE_ATTRIBUTE_TESTED | \ + EFI_RESOURCE_ATTRIBUTE_16_BIT_IO | \ + EFI_RESOURCE_ATTRIBUTE_32_BIT_IO | \ + EFI_RESOURCE_ATTRIBUTE_64_BIT_IO \ + ) + +#define TESTED_MEMORY_ATTRIBUTES (EFI_RESOURCE_ATTRIBUTE_PRESENT | EF= I_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_TESTED) + +#define INITIALIZED_MEMORY_ATTRIBUTES (EFI_RESOURCE_ATTRIBUTE_PRESENT | EF= I_RESOURCE_ATTRIBUTE_INITIALIZED) + +#define PRESENT_MEMORY_ATTRIBUTES (EFI_RESOURCE_ATTRIBUTE_PRESENT) + +GLOBAL_REMOVE_IF_UNREFERENCED CHAR8 *mResourceTypeShortName[] =3D { + "Mem", + "MMIO", + "I/O", + "FD", + "MM Port I/O", + "Reserved Mem", + "Reserved I/O", +}; + +/** + Return the short name of resource type. + + @param Type resource type. + + @return the short name of resource type. +**/ +CHAR8 * +ShortNameOfResourceType ( + IN UINT32 Type + ) +{ + if (Type < sizeof(mResourceTypeShortName) / sizeof(mResourceTypeShortNam= e[0])) { + return mResourceTypeShortName[Type]; + } else { + return "Unknown"; + } +} + +/** + Dump resource hob. + + @param HobList the HOB list. +**/ +VOID +DumpResourceHob ( + IN VOID *HobList + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_HOB_RESOURCE_DESCRIPTOR *ResourceHob; + + DEBUG ((DEBUG_VERBOSE, "Resource Descriptor HOBs\n")); + for (Hob.Raw =3D HobList; !END_OF_HOB_LIST (Hob); Hob.Raw =3D GET_NEXT_H= OB (Hob)) { + if (GET_HOB_TYPE (Hob) =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + ResourceHob =3D Hob.ResourceDescriptor; + DEBUG ((DEBUG_VERBOSE, + " BA=3D%016lx L=3D%016lx Attr=3D%08x ", + ResourceHob->PhysicalStart, + ResourceHob->ResourceLength, + ResourceHob->ResourceAttribute + )); + DEBUG ((DEBUG_VERBOSE, ShortNameOfResourceType(ResourceHob->Resource= Type))); + switch (ResourceHob->ResourceType) { + case EFI_RESOURCE_SYSTEM_MEMORY: + if ((ResourceHob->ResourceAttribute & EFI_RESOURCE_ATTRIBUTE_PERSI= STENT) !=3D 0) { + DEBUG ((DEBUG_VERBOSE, " (Persistent)")); + } else if ((ResourceHob->ResourceAttribute & EFI_RESOURCE_ATTRIBUT= E_MORE_RELIABLE) !=3D 0) { + DEBUG ((DEBUG_VERBOSE, " (MoreReliable)")); + } else if ((ResourceHob->ResourceAttribute & MEMORY_ATTRIBUTE_MASK= ) =3D=3D TESTED_MEMORY_ATTRIBUTES) { + DEBUG ((DEBUG_VERBOSE, " (Tested)")); + } else if ((ResourceHob->ResourceAttribute & MEMORY_ATTRIBUTE_MASK= ) =3D=3D INITIALIZED_MEMORY_ATTRIBUTES) { + DEBUG ((DEBUG_VERBOSE, " (Init)")); + } else if ((ResourceHob->ResourceAttribute & MEMORY_ATTRIBUTE_MASK= ) =3D=3D PRESENT_MEMORY_ATTRIBUTES) { + DEBUG ((DEBUG_VERBOSE, " (Present)")); + } else { + DEBUG ((DEBUG_VERBOSE, " (Unknown)")); + } + break; + default: + break; + } + DEBUG ((DEBUG_VERBOSE, "\n")); + } + } +} + +/** + Dump PHIT hob. + + @param HobList the HOB list. +**/ +VOID +DumpPhitHob ( + IN VOID *HobList + ) +{ + EFI_HOB_HANDOFF_INFO_TABLE *PhitHob; + + PhitHob =3D HobList; + ASSERT(GET_HOB_TYPE(HobList) =3D=3D EFI_HOB_TYPE_HANDOFF); + DEBUG ((DEBUG_VERBOSE, "PHIT HOB\n")); + DEBUG ((DEBUG_VERBOSE, " PhitHob - 0x%x\n", PhitHob)); + DEBUG ((DEBUG_VERBOSE, " BootMode - 0x%x\n", PhitHob->BootMo= de)); + DEBUG ((DEBUG_VERBOSE, " EfiMemoryTop - 0x%016lx\n", PhitHob->Ef= iMemoryTop)); + DEBUG ((DEBUG_VERBOSE, " EfiMemoryBottom - 0x%016lx\n", PhitHob->Ef= iMemoryBottom)); + DEBUG ((DEBUG_VERBOSE, " EfiFreeMemoryTop - 0x%016lx\n", PhitHob->Ef= iFreeMemoryTop)); + DEBUG ((DEBUG_VERBOSE, " EfiFreeMemoryBottom - 0x%016lx\n", PhitHob->Ef= iFreeMemoryBottom)); + DEBUG ((DEBUG_VERBOSE, " EfiEndOfHobList - 0x%lx\n", PhitHob->EfiEn= dOfHobList)); +} + +/** + Get the highest memory. + + @param HobList the HOB list. + + @return the highest memory. +**/ +UINT64 +GetTopMemory ( + IN VOID *HobList + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_HOB_RESOURCE_DESCRIPTOR *ResourceHob; + UINT64 TopMemory; + UINT64 ResourceTop; + + TopMemory =3D 0; + for (Hob.Raw =3D HobList; !END_OF_HOB_LIST (Hob); Hob.Raw =3D GET_NEXT_H= OB (Hob)) { + if (GET_HOB_TYPE (Hob) =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + ResourceHob =3D Hob.ResourceDescriptor; + switch (ResourceHob->ResourceType) { + case EFI_RESOURCE_SYSTEM_MEMORY: + ResourceTop =3D ResourceHob->PhysicalStart + ResourceHob->Resource= Length; + if (TopMemory < ResourceTop) { + TopMemory =3D ResourceTop; + } + break; + default: + break; + } + DEBUG ((DEBUG_VERBOSE, "\n")); + } + } + return TopMemory; +} + +/** + Initialize DMA protection. + + @param DmaBufferSize the DMA buffer size + @param DmaBufferBase the DMA buffer base + + @retval EFI_SUCCESS the DMA protection is initialized. + @retval EFI_OUT_OF_RESOURCES no enough resource to initialize DMA prote= ction. +**/ +EFI_STATUS +InitDmaProtection ( + IN UINTN DmaBufferSize, + OUT UINTN *DmaBufferBase + ) +{ + EFI_STATUS Status; + VOID *HobList; + EFI_HOB_HANDOFF_INFO_TABLE *PhitHob; + UINT32 LowMemoryAlignment; + UINT64 HighMemoryAlignment; + UINTN MemoryAlignment; + UINTN LowBottom; + UINTN LowTop; + UINTN HighBottom; + UINT64 HighTop; + + HobList =3D GetHobList (); + DumpPhitHob (HobList); + DumpResourceHob (HobList); + + PhitHob =3D HobList; + + ASSERT (PhitHob->EfiMemoryBottom < PhitHob->EfiMemoryTop); + + LowMemoryAlignment =3D GetLowMemoryAlignment (); + HighMemoryAlignment =3D GetHighMemoryAlignment (); + if (LowMemoryAlignment < HighMemoryAlignment) { + MemoryAlignment =3D (UINTN)HighMemoryAlignment; + } else { + MemoryAlignment =3D LowMemoryAlignment; + } + ASSERT (DmaBufferSize =3D=3D ALIGN_VALUE(DmaBufferSize, MemoryAlignment)= ); + *DmaBufferBase =3D (UINTN)AllocateAlignedPages (EFI_SIZE_TO_PAGES(DmaBuf= ferSize), MemoryAlignment); + if (*DmaBufferBase =3D=3D 0) { + DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); + return EFI_OUT_OF_RESOURCES; + } + + LowBottom =3D 0; + LowTop =3D *DmaBufferBase; + HighBottom =3D *DmaBufferBase + DmaBufferSize; + HighTop =3D GetTopMemory (HobList); + + Status =3D SetDmaProtectedRange ( + (UINT32)LowBottom, + (UINT32)(LowTop - LowBottom), + HighBottom, + HighTop - HighBottom + ); + + if (EFI_ERROR(Status)) { + FreePages ((VOID *)*DmaBufferBase, EFI_SIZE_TO_PAGES(DmaBufferSize)); + } + + return Status; +} + +/** + Initializes the Intel VTd PMR PEIM. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Usb bot driver is successfully initialize= d. + @retval EFI_OUT_OF_RESOURCES Can't initialize the driver. + +**/ +EFI_STATUS +EFIAPI +IntelVTdPmrInitialize ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT0) =3D=3D 0) { + return EFI_UNSUPPORTED; + } + + Status =3D PeiServicesLocatePpi ( + &gEdkiiVTdInfoPpiGuid, + 0, + NULL, + (VOID **)&mVTdInfoPpi + ); + ASSERT_EFI_ERROR(Status); + + // + // Find a pre-memory in resource hob as DMA buffer + // Mark PEI memory to be DMA protected. + // + Status =3D InitDmaProtection (mDmaBufferSize, &mDmaBufferBase); + if (EFI_ERROR(Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", mDmaBufferBase)); + DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", mDmaBufferSize)); + + mDmaBufferCurrentTop =3D mDmaBufferBase + mDmaBufferSize; + mDmaBufferCurrentBottom =3D mDmaBufferBase; + + // + // Install PPI. + // + Status =3D PeiServicesInstallPpi (&mIoMmuPpiList); + ASSERT_EFI_ERROR(Status); + + return Status; +} + diff --git a/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.h b/IntelSilicon= Pkg/IntelVTdPmrPei/IntelVTdPmrPei.h new file mode 100644 index 0000000..aa5926a7 --- /dev/null +++ b/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.h @@ -0,0 +1,68 @@ +/** @file + The definition for DMA access Library. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __DMA_ACCESS_LIB_H__ +#define __DMA_ACCESS_LIB_H__ + +/** + Set DMA protected region. + + @param LowMemoryBase The protected low memory region base. + @param LowMemoryLength The protected low memory region length. + @param HighMemoryBase The protected high memory region base. + @param HighMemoryLength The protected high memory region length. + + @retval EFI_SUCCESS The DMA protection is set. + @retval EFI_UNSUPPORTED The DMA protection is not set. +**/ +EFI_STATUS +SetDmaProtectedRange ( + IN UINT32 LowMemoryBase, + IN UINT32 LowMemoryLength, + IN UINT64 HighMemoryBase, + IN UINT64 HighMemoryLength + ); + +/** + Diable DMA protection. + + @retval DMA protection is disabled. +**/ +EFI_STATUS +DisableDmaProtection ( + VOID + ); + +/** + Get protected low memory alignment. + + @return protected low memory alignment. +**/ +UINT32 +GetLowMemoryAlignment ( + VOID + ); + +/** + Get protected high memory alignment. + + @return protected high memory alignment. +**/ +UINT64 +GetHighMemoryAlignment ( + VOID + ); + +#endif + diff --git a/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf b/IntelSilic= onPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf new file mode 100644 index 0000000..86cd7d1 --- /dev/null +++ b/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf @@ -0,0 +1,59 @@ +## @file +# Component INF file for the Intel VTd PMR PEIM. +# +# This driver initializes VTd engine based upon EDKII_VTD_INFO_PPI +# and provide DMA protection in PEI. +# +# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BS= D License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D IntelVTdPmrPei + MODULE_UNI_FILE =3D IntelVTdPmrPei.uni + FILE_GUID =3D F906769F-4AED-4A0D-8C7C-FF21B9D1051A + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D IntelVTdPmrInitialize + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + IntelVTdPmrPei.c + IntelVTdPmrPei.h + IntelVTdPmr.c + +[LibraryClasses] + DebugLib + BaseMemoryLib + BaseLib + PeimEntryPoint + PeiServicesLib + HobLib + IoLib + +[Ppis] + gEdkiiIoMmuPpiGuid ## PRODUCES + gEdkiiVTdInfoPpiGuid ## CONSUMES + +[Pcd] + gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask ## CONSUMES + +[Depex] + gEfiPeiMemoryDiscoveredPpiGuid AND + gEdkiiVTdInfoPpiGuid + +[UserExtensions.TianoCore."ExtraFiles"] + IntelVTdPmrPeiExtra.uni + diff --git a/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.uni b/IntelSilic= onPkg/IntelVTdPmrPei/IntelVTdPmrPei.uni new file mode 100644 index 0000000..11508a4 --- /dev/null +++ b/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.uni @@ -0,0 +1,20 @@ +// /** @file +// IntelVTdPmrPei Module Localized Abstract and Description Content +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials are +// licensed and made available under the terms and conditions of the BSD L= icense +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Intel VTd PMR PEI= Driver." + +#string STR_MODULE_DESCRIPTION #language en-US "This driver initi= alizes VTd engine based upon EDKII_VTD_INFO_PPI and provide DMA protection = to device in PEI." + diff --git a/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni b/Intel= SiliconPkg/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni new file mode 100644 index 0000000..c6b2dec --- /dev/null +++ b/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni @@ -0,0 +1,20 @@ +// /** @file +// IntelVTdPmrPei Localized Strings and Content +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials are +// licensed and made available under the terms and conditions of the BSD L= icense +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Intel VTd PMR PEI Driver" + + --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504883071446870.9385586905751; Fri, 8 Sep 2017 08:04:31 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A277B21D492F5; Fri, 8 Sep 2017 08:01:20 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C431F21D492EC for ; Fri, 8 Sep 2017 08:01:16 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:09 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:08 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511673" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:51 +0800 Message-Id: <1504883034-22060-9-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 08/11] IntelSiliconPkg/dsc: Add IntelVTdPmrPeim. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- IntelSiliconPkg/IntelSiliconPkg.dsc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc b/IntelSiliconPkg/IntelSil= iconPkg.dsc index 9a9920f..33e822f 100644 --- a/IntelSiliconPkg/IntelSiliconPkg.dsc +++ b/IntelSiliconPkg/IntelSiliconPkg.dsc @@ -40,6 +40,14 @@ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf =20 +[LibraryClasses.common.PEIM] + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + [LibraryClasses.common.DXE_DRIVER] UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf @@ -72,6 +80,7 @@ [Components] IntelSiliconPkg/Library/DxeSmbiosDataHobLib/DxeSmbiosDataHobLib.inf IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf + IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf =20 [BuildOptions] --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504883075246411.7596064562031; Fri, 8 Sep 2017 08:04:35 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E12DA21D492FB; Fri, 8 Sep 2017 08:01:20 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 964D621D492EF for ; Fri, 8 Sep 2017 08:01:17 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:09 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:09 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511683" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:52 +0800 Message-Id: <1504883034-22060-10-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 09/11] IntelSiliconPkg: Add PlatformVTdInfoSamplePei. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This is a sample driver to produce VTD_INFO PPI. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c = | 65 ++++++++++++++++++++ IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf = | 51 +++++++++++++++ IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni = | 20 ++++++ IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePeiExtra.uni= | 20 ++++++ 4 files changed, 156 insertions(+) diff --git a/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSample= Pei.c b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c new file mode 100644 index 0000000..c79398f --- /dev/null +++ b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c @@ -0,0 +1,65 @@ +/** @file + Platform VTd Info Sample PEI driver. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include + +#include +#include + +typedef struct { + UINT64 Revision; + UINT8 HostAddressWidth; + UINT8 Reserved[3]; + UINT32 VTdEngineCount; + UINT64 VTdEngineAddress[2]; +} MY_VTD_INFO_PPI; + +MY_VTD_INFO_PPI mPlatformVTdSample =3D { + EDKII_VTD_INFO_PPI_REVISION, + 0x26, + {0}, + 2, + {0xFED90000, 0xFED91000}, +}; + +EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEdkiiVTdInfoPpiGuid, + &mPlatformVTdSample +}; + +/** + Platform VTd Info sample driver. + + @param[in] FileHandle Handle of the file being invoked. + @param[in] PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS if it completed successfully. +**/ +EFI_STATUS +EFIAPI +PlatformVTdInfoSampleInitialize ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + Status =3D PeiServicesInstallPpi (&mPlatformVTdInfoSampleDesc); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSample= Pei.inf b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei= .inf new file mode 100644 index 0000000..fe12821 --- /dev/null +++ b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf @@ -0,0 +1,51 @@ +## @file +# Platform VTd Info Sample PEI driver. +# +# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BS= D License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformVTdInfoSamplePei + MODULE_UNI_FILE =3D PlatformVTdInfoSamplePei.uni + FILE_GUID =3D 839EB770-5C64-4EED-A6D5-EC515B2B2B23 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformVTdInfoSampleInitialize + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# +# + +[Sources] + PlatformVTdInfoSamplePei.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[LibraryClasses] + PeimEntryPoint + PeiServicesLib + +[Ppis] + gEdkiiVTdInfoPpiGuid ## PRODUCES + +[Depex] + gEfiPeiMemoryDiscoveredPpiGuid + +[UserExtensions.TianoCore."ExtraFiles"] + PlatformVTdInfoSamplePeiExtra.uni + diff --git a/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSample= Pei.uni b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei= .uni new file mode 100644 index 0000000..36f9183 --- /dev/null +++ b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni @@ -0,0 +1,20 @@ +// /** @file +// PlatformVTdInfoSamplePei Module Localized Abstract and Description Cont= ent +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials are +// licensed and made available under the terms and conditions of the BSD L= icense +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Platform VTd Info= PEI Driver." + +#string STR_MODULE_DESCRIPTION #language en-US "This driver provi= des sample on how to produce Platform VTd Info PPI." + diff --git a/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSample= PeiExtra.uni b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePeiExtra.uni new file mode 100644 index 0000000..df6345f --- /dev/null +++ b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePeiExtr= a.uni @@ -0,0 +1,20 @@ +// /** @file +// PlatformVTdInfoSamplePei Localized Strings and Content +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials are +// licensed and made available under the terms and conditions of the BSD L= icense +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Platform VTd Info Sample PEI Driver" + + --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504883078682850.7781593883961; Fri, 8 Sep 2017 08:04:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2521621DF8078; Fri, 8 Sep 2017 08:01:21 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6700821CEB103 for ; Fri, 8 Sep 2017 08:01:18 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:10 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:10 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511687" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:53 +0800 Message-Id: <1504883034-22060-11-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 10/11] IntelSiliconPkg/dsc: Add PlatformVTdInfoSamplePei. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- IntelSiliconPkg/IntelSiliconPkg.dsc | 1 + 1 file changed, 1 insertion(+) diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc b/IntelSiliconPkg/IntelSil= iconPkg.dsc index 33e822f..422e202 100644 --- a/IntelSiliconPkg/IntelSiliconPkg.dsc +++ b/IntelSiliconPkg/IntelSiliconPkg.dsc @@ -82,6 +82,7 @@ IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf + IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf =20 [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504883083001693.7293483608747; Fri, 8 Sep 2017 08:04:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6431821E2BE37; Fri, 8 Sep 2017 08:01:21 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7E5F620945BFC for ; Fri, 8 Sep 2017 08:01:19 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 08:04:11 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.209.82]) by fmsmga004.fm.intel.com with ESMTP; 08 Sep 2017 08:04:10 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,361,1500966000"; d="scan'208";a="309511694" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 23:03:54 +0800 Message-Id: <1504883034-22060-12-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 11/11] MdeModulePkg/XhciPei: Support IoMmu. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Update XHCI driver to consume IOMMU_PPI to allocate DMA buffer. If no IOMMU_PPI exists, this driver still calls PEI service to allocate DMA buffer, with assumption that DRAM=3D=3DDMA. This is a compatible change. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c | 249 ++++++++++++++++++++ MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c | 55 +++-- MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h | 9 +- MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 55 ++++- MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h | 107 +++++++++ MdeModulePkg/Bus/Pci/XhciPei/XhciPei.inf | 3 + MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 47 +++- MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h | 1 + 8 files changed, 492 insertions(+), 34 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c b/MdeModulePkg/Bus/Pci/X= hciPei/DmaMem.c new file mode 100644 index 0000000..6e2c1b5 --- /dev/null +++ b/MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c @@ -0,0 +1,249 @@ +/** @file +The DMA memory help function. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions +of the BSD License which accompanies this distribution. The +full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + +**/ + +#include "XhcPeim.h" + +EDKII_IOMMU_PPI *mIoMmu; + +/** + Provides the controller-specific addresses required to access system mem= ory from a + DMA bus master. + + @param Operation Indicates if the bus master is going to re= ad or write to system memory. + @param HostAddress The system memory address to map to the PC= I controller. + @param NumberOfBytes On input the number of bytes to map. On ou= tput the number of bytes + that were mapped. + @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned Numb= erOfBytes. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a comm= on buffer. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. + @retval EFI_DEVICE_ERROR The system hardware could not map the requ= ested address. + +**/ +EFI_STATUS +IoMmuMap ( + IN EDKII_IOMMU_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + EFI_STATUS Status; + UINT64 Attribute; + + if (mIoMmu !=3D NULL) { + Status =3D mIoMmu->Map ( + mIoMmu, + Operation, + HostAddress, + NumberOfBytes, + DeviceAddress, + Mapping + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + switch (Operation) { + case EdkiiIoMmuOperationBusMasterRead: + case EdkiiIoMmuOperationBusMasterRead64: + Attribute =3D EDKII_IOMMU_ACCESS_READ; + break; + case EdkiiIoMmuOperationBusMasterWrite: + case EdkiiIoMmuOperationBusMasterWrite64: + Attribute =3D EDKII_IOMMU_ACCESS_WRITE; + break; + case EdkiiIoMmuOperationBusMasterCommonBuffer: + case EdkiiIoMmuOperationBusMasterCommonBuffer64: + Attribute =3D EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE; + break; + default: + ASSERT(FALSE); + return EFI_INVALID_PARAMETER; + } + Status =3D mIoMmu->SetAttribute ( + mIoMmu, + *Mapping, + Attribute + ); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + *DeviceAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress; + *Mapping =3D NULL; + Status =3D EFI_SUCCESS; + } + return Status; +} + +/** + Completes the Map() operation and releases any corresponding resources. + + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned b= y Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target s= ystem memory. +**/ +EFI_STATUS +IoMmuUnmap ( + IN VOID *Mapping + ) +{ + EFI_STATUS Status; + + if (mIoMmu !=3D NULL) { + Status =3D mIoMmu->SetAttribute (mIoMmu, Mapping, 0); + Status =3D mIoMmu->Unmap (mIoMmu, Mapping); + } else { + Status =3D EFI_SUCCESS; + } + return Status; +} + +/** + Allocates pages that are suitable for an OperationBusMasterCommonBuffer = or + OperationBusMasterCommonBuffer64 mapping. + + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory = address of the + allocated range. + @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal = attribute bits are + MEMORY_WRITE_COMBINE and MEMORY_CACHED. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +EFI_STATUS +IoMmuAllocateBuffer ( + IN UINTN Pages, + OUT VOID **HostAddress, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + EFI_STATUS Status; + UINTN NumberOfBytes; + EFI_PHYSICAL_ADDRESS HostPhyAddress; + + *HostAddress =3D NULL; + *DeviceAddress =3D 0; + + if (mIoMmu !=3D NULL) { + Status =3D mIoMmu->AllocateBuffer ( + mIoMmu, + EfiBootServicesData, + Pages, + HostAddress, + 0 + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + NumberOfBytes =3D EFI_PAGES_TO_SIZE(Pages); + Status =3D mIoMmu->Map ( + mIoMmu, + EdkiiIoMmuOperationBusMasterCommonBuffer, + *HostAddress, + &NumberOfBytes, + DeviceAddress, + Mapping + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + Status =3D mIoMmu->SetAttribute ( + mIoMmu, + *Mapping, + EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE + ); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + Status =3D PeiServicesAllocatePages ( + EfiBootServicesData, + Pages, + &HostPhyAddress + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + *HostAddress =3D (VOID *)(UINTN)HostPhyAddress; + *DeviceAddress =3D HostPhyAddress; + *Mapping =3D NULL; + } + return Status; +} + +/** + Frees memory that was allocated with AllocateBuffer(). + + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allo= cated range. + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress = and Pages + was not allocated with AllocateBuffer(). + +**/ +EFI_STATUS +IoMmuFreeBuffer ( + IN UINTN Pages, + IN VOID *HostAddress, + IN VOID *Mapping + ) +{ + EFI_STATUS Status; + + if (mIoMmu !=3D NULL) { + Status =3D mIoMmu->SetAttribute (mIoMmu, Mapping, 0); + Status =3D mIoMmu->Unmap (mIoMmu, Mapping); + Status =3D mIoMmu->FreeBuffer (mIoMmu, Pages, HostAddress); + } else { + Status =3D EFI_SUCCESS; + } + return Status; +} + +/** + Initialize IOMMU. +**/ +VOID +IoMmuInit ( + VOID + ) +{ + PeiServicesLocatePpi ( + &gEdkiiIoMmuPpiGuid, + 0, + NULL, + (VOID **)&mIoMmu + ); +} + diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c b/MdeModulePkg/Bus/Pci= /XhciPei/UsbHcMem.c index 6a3f3a5..5d0232c 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c @@ -31,6 +31,9 @@ UsbHcAllocMemBlock ( ) { USBHC_MEM_BLOCK *Block; + VOID *BufHost; + VOID *Mapping; + EFI_PHYSICAL_ADDRESS MappedAddr; EFI_STATUS Status; UINTN PageNumber; EFI_PHYSICAL_ADDRESS TempPtr; @@ -71,18 +74,20 @@ UsbHcAllocMemBlock ( =20 Block->Bits =3D (UINT8 *) (UINTN) TempPtr; =20 - Status =3D PeiServicesAllocatePages ( - EfiBootServicesData, + Status =3D IoMmuAllocateBuffer ( Pages, - &TempPtr + &BufHost, + &MappedAddr, + &Mapping ); if (EFI_ERROR (Status)) { return NULL; } - ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (Pages)); + ZeroMem ((VOID *) (UINTN) BufHost, EFI_PAGES_TO_SIZE (Pages)); =20 - Block->BufHost =3D (UINT8 *) (UINTN) TempPtr;; - Block->Buf =3D (UINT8 *) (UINTN) TempPtr; + Block->BufHost =3D (UINT8 *) (UINTN) BufHost; + Block->Buf =3D (UINT8 *) (UINTN) MappedAddr; + Block->Mapping =3D Mapping; Block->Next =3D NULL; =20 return Block; @@ -102,6 +107,9 @@ UsbHcFreeMemBlock ( ) { ASSERT ((Pool !=3D NULL) && (Block !=3D NULL)); + + IoMmuFreeBuffer (EFI_SIZE_TO_PAGES (Block->BufLen), Block->BufHost, Bloc= k->Mapping); + // // No free memory in PEI. // @@ -567,6 +575,7 @@ UsbHcFreeMem ( @param HostAddress The system memory address to map to the PC= I controller. @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). =20 @retval EFI_SUCCESS Success to allocate aligned pages. @retval EFI_INVALID_PARAMETER Pages or Alignment is not valid. @@ -578,13 +587,16 @@ UsbHcAllocateAlignedPages ( IN UINTN Pages, IN UINTN Alignment, OUT VOID **HostAddress, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping ) { EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS Memory; + VOID *Memory; UINTN AlignedMemory; UINTN AlignmentMask; + EFI_PHYSICAL_ADDRESS DeviceMemory; + UINTN AlignedDeviceMemory; UINTN RealPages; =20 // @@ -611,32 +623,36 @@ UsbHcAllocateAlignedPages ( // ASSERT (RealPages > Pages); =20 - Status =3D PeiServicesAllocatePages ( - EfiBootServicesData, + Status =3D IoMmuAllocateBuffer ( Pages, - &Memory + &Memory, + &DeviceMemory, + Mapping ); if (EFI_ERROR (Status)) { return EFI_OUT_OF_RESOURCES; } AlignedMemory =3D ((UINTN) Memory + AlignmentMask) & ~AlignmentMask; + AlignedDeviceMemory =3D ((UINTN) DeviceMemory + AlignmentMask) & ~Alig= nmentMask; } else { // // Do not over-allocate pages in this case. // - Status =3D PeiServicesAllocatePages ( - EfiBootServicesData, + Status =3D IoMmuAllocateBuffer ( Pages, - &Memory + &Memory, + &DeviceMemory, + Mapping ); if (EFI_ERROR (Status)) { return EFI_OUT_OF_RESOURCES; } AlignedMemory =3D (UINTN) Memory; + AlignedDeviceMemory =3D (UINTN) DeviceMemory; } =20 *HostAddress =3D (VOID *) AlignedMemory; - *DeviceAddress =3D (EFI_PHYSICAL_ADDRESS) AlignedMemory; + *DeviceAddress =3D (EFI_PHYSICAL_ADDRESS) AlignedDeviceMemory; =20 return EFI_SUCCESS; } @@ -646,17 +662,18 @@ UsbHcAllocateAlignedPages ( =20 @param HostAddress The system memory address to map to the PC= I controller. @param Pages The number of pages to free. + @param Mapping The mapping value returned from Map(). =20 **/ VOID UsbHcFreeAlignedPages ( IN VOID *HostAddress, - IN UINTN Pages + IN UINTN Pages, + IN VOID *Mapping ) { ASSERT (Pages !=3D 0); - // - // No free memory in PEI. - // + + IoMmuFreeBuffer (Pages, HostAddress, Mapping); } =20 diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h b/MdeModulePkg/Bus/Pci= /XhciPei/UsbHcMem.h index c314e92..c315e6e 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h @@ -29,6 +29,7 @@ struct _USBHC_MEM_BLOCK { UINT8 *Buf; UINT8 *BufHost; UINTN BufLen; // Memory size in bytes + VOID *Mapping; USBHC_MEM_BLOCK *Next; }; =20 @@ -112,6 +113,7 @@ UsbHcGetHostAddrForPciAddr ( @param HostAddress The system memory address to map to the PC= I controller. @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). =20 @retval EFI_SUCCESS Success to allocate aligned pages. @retval EFI_INVALID_PARAMETER Pages or Alignment is not valid. @@ -123,7 +125,8 @@ UsbHcAllocateAlignedPages ( IN UINTN Pages, IN UINTN Alignment, OUT VOID **HostAddress, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping ); =20 /** @@ -131,12 +134,14 @@ UsbHcAllocateAlignedPages ( =20 @param HostAddress The system memory address to map to the PC= I controller. @param Pages The number of pages to free. + @param Mapping The mapping value returned from Map(). =20 **/ VOID UsbHcFreeAlignedPages ( IN VOID *HostAddress, - IN UINTN Pages + IN UINTN Pages, + IN VOID *Mapping ); =20 #endif diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c b/MdeModulePkg/Bus/Pci/= XhciPei/XhcPeim.c index 38f0d21..99f69f7 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c @@ -662,7 +662,8 @@ XhcPeiControlTransfer ( if (EFI_ERROR(RecoveryStatus)) { DEBUG((EFI_D_ERROR, "XhcPeiControlTransfer: XhcPeiDequeueTrbFromEndp= oint failed\n")); } - goto FREE_URB; + XhcPeiFreeUrb (Xhc, Urb); + goto ON_EXIT; } else { if (*TransferResult =3D=3D EFI_USB_NOERROR) { Status =3D EFI_SUCCESS; @@ -672,11 +673,17 @@ XhcPeiControlTransfer ( DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: XhcPeiRecoverHaltedEn= dpoint failed\n")); } Status =3D EFI_DEVICE_ERROR; - goto FREE_URB; + XhcPeiFreeUrb (Xhc, Urb); + goto ON_EXIT; } else { - goto FREE_URB; + XhcPeiFreeUrb (Xhc, Urb); + goto ON_EXIT; } } + // + // Unmap data before consume. + // + XhcPeiFreeUrb (Xhc, Urb); =20 // // Hook Get_Descriptor request from UsbBus as we need evaluate context a= nd configure endpoint. @@ -704,7 +711,7 @@ XhcPeiControlTransfer ( Xhc->UsbDevContext[SlotId].ConfDesc =3D AllocateZeroPool (Xhc->UsbDe= vContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIP= TOR *)); if (Xhc->UsbDevContext[SlotId].ConfDesc =3D=3D NULL) { Status =3D EFI_OUT_OF_RESOURCES; - goto FREE_URB; + goto ON_EXIT; } if (Xhc->HcCParams.Data.Csz =3D=3D 0) { Status =3D XhcPeiEvaluateContext (Xhc, SlotId, MaxPacket0); @@ -722,7 +729,7 @@ XhcPeiControlTransfer ( Xhc->UsbDevContext[SlotId].ConfDesc[Index] =3D AllocateZeroPool (*= DataLength); if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] =3D=3D NULL) { Status =3D EFI_OUT_OF_RESOURCES; - goto FREE_URB; + goto ON_EXIT; } CopyMem (Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLe= ngth); } @@ -844,9 +851,6 @@ XhcPeiControlTransfer ( *(UINT32 *) Data =3D *(UINT32 *) &PortStatus; } =20 -FREE_URB: - XhcPeiFreeUrb (Xhc, Urb); - ON_EXIT: =20 if (EFI_ERROR (Status)) { @@ -1399,6 +1403,34 @@ XhcPeiGetRootHubPortStatus ( } =20 /** + One notified function to stop the Host Controller at the end of PEI + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDescriptor Pointer to the descriptor for the Notific= ation event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with t= his function. + + @retval EFI_SUCCESS The function completes successfully + @retval others +**/ +EFI_STATUS +EFIAPI +XhcEndOfPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + PEI_XHC_DEV *Xhc; + + Xhc =3D PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(NotifyDescriptor); + + XhcPeiHaltHC (Xhc, XHC_GENERIC_TIMEOUT); + + return EFI_SUCCESS; +} + +/** @param FileHandle Handle of the file being invoked. @param PeiServices Describes the list of possible PEI Services. =20 @@ -1429,6 +1461,8 @@ XhcPeimEntry ( return EFI_SUCCESS; } =20 + IoMmuInit (); + Status =3D PeiServicesLocatePpi ( &gPeiUsbControllerPpiGuid, 0, @@ -1530,7 +1564,12 @@ XhcPeimEntry ( XhcDev->PpiDescriptor.Guid =3D &gPeiUsb2HostControllerPpiGuid; XhcDev->PpiDescriptor.Ppi =3D &XhcDev->Usb2HostControllerPpi; =20 + XhcDev->EndOfPeiNotifyList.Flags =3D (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CA= LLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST); + XhcDev->EndOfPeiNotifyList.Guid =3D &gEfiEndOfPeiSignalPpiGuid; + XhcDev->EndOfPeiNotifyList.Notify =3D XhcEndOfPei; + PeiServicesInstallPpi (&XhcDev->PpiDescriptor); + PeiServicesNotifyPpi (&XhcDev->EndOfPeiNotifyList); =20 Index++; } diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h b/MdeModulePkg/Bus/Pci/= XhciPei/XhcPeim.h index 99f0396..e7a100f 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h @@ -21,6 +21,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. =20 #include #include +#include +#include =20 #include #include @@ -153,6 +155,12 @@ struct _PEI_XHC_DEV { USBHC_MEM_POOL *MemPool; =20 // + // EndOfPei callback is used to stop the XHC DMA operation + // after exit PEI phase. + // + EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList; + + // // XHCI configuration data // UINT8 CapLength; ///< Capability Register= Length @@ -164,7 +172,9 @@ struct _PEI_XHC_DEV { UINT32 PageSize; UINT32 MaxScratchpadBufs; UINT64 *ScratchBuf; + VOID *ScratchMap; UINT64 *ScratchEntry; + UINTN *ScratchEntryMap; UINT64 *DCBAA; UINT32 MaxSlotsEn; // @@ -184,6 +194,7 @@ struct _PEI_XHC_DEV { }; =20 #define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2Host= ControllerPpi, USB_XHC_DEV_SIGNATURE) +#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, E= ndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE) =20 /** Initialize the memory management pool for the host controller. @@ -242,4 +253,100 @@ UsbHcFreeMem ( ) ; =20 + +/** + Initialize IOMMU. +**/ +VOID +IoMmuInit ( + VOID + ); + +/** + Provides the controller-specific addresses required to access system mem= ory from a + DMA bus master. + + @param Operation Indicates if the bus master is going to re= ad or write to system memory. + @param HostAddress The system memory address to map to the PC= I controller. + @param NumberOfBytes On input the number of bytes to map. On ou= tput the number of bytes + that were mapped. + @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned Numb= erOfBytes. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a comm= on buffer. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. + @retval EFI_DEVICE_ERROR The system hardware could not map the requ= ested address. + +**/ +EFI_STATUS +IoMmuMap ( + IN EDKII_IOMMU_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +/** + Completes the Map() operation and releases any corresponding resources. + + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned b= y Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target s= ystem memory. +**/ +EFI_STATUS +IoMmuUnmap ( + IN VOID *Mapping + ); + +/** + Allocates pages that are suitable for an OperationBusMasterCommonBuffer = or + OperationBusMasterCommonBuffer64 mapping. + + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory = address of the + allocated range. + @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal = attribute bits are + MEMORY_WRITE_COMBINE and MEMORY_CACHED. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +EFI_STATUS +IoMmuAllocateBuffer ( + IN UINTN Pages, + OUT VOID **HostAddress, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +/** + Frees memory that was allocated with AllocateBuffer(). + + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allo= cated range. + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress = and Pages + was not allocated with AllocateBuffer(). + +**/ +EFI_STATUS +IoMmuFreeBuffer ( + IN UINTN Pages, + IN VOID *HostAddress, + IN VOID *Mapping + ); + #endif diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciPei.inf b/MdeModulePkg/Bus/Pc= i/XhciPei/XhciPei.inf index dc65f28..f307ea7 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciPei.inf +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciPei.inf @@ -37,6 +37,7 @@ XhcPeim.h XhciSched.c UsbHcMem.c + DmaMem.c XhciReg.h XhciSched.h UsbHcMem.h @@ -56,6 +57,8 @@ [Ppis] gPeiUsb2HostControllerPpiGuid ## PRODUCES gPeiUsbControllerPpiGuid ## CONSUMES + gEdkiiIoMmuPpiGuid ## CONSUMES + gEfiEndOfPeiSignalPpiGuid ## CONSUMES =20 [Depex] gEfiPeiMemoryDiscoveredPpiGuid AND gPeiUsbControllerPpiGuid AND gEfiPeiB= ootInRecoveryModePpiGuid diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pc= i/XhciPei/XhciSched.c index 3dd2b89..e5aee49 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c @@ -200,6 +200,8 @@ XhcPeiFreeUrb ( return; } =20 + IoMmuUnmap (Urb->DataMap); + FreePool (Urb); } =20 @@ -227,6 +229,10 @@ XhcPeiCreateTransferTrb ( UINTN TotalLen; UINTN Len; UINTN TrbNum; + EDKII_IOMMU_OPERATION MapOp; + EFI_PHYSICAL_ADDRESS PhyAddr; + VOID *Map; + EFI_STATUS Status; =20 SlotId =3D XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr); if (SlotId =3D=3D 0) { @@ -249,7 +255,27 @@ XhcPeiCreateTransferTrb ( EPType =3D (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EP= Type; } =20 - Urb->DataPhy =3D Urb->Data; + // + // No need to remap. + // + if ((Urb->Data !=3D NULL) && (Urb->DataMap =3D=3D NULL)) { + if (((UINT8) (Urb->Ep.Direction)) =3D=3D EfiUsbDataIn) { + MapOp =3D EdkiiIoMmuOperationBusMasterWrite; + } else { + MapOp =3D EdkiiIoMmuOperationBusMasterRead; + } + + Len =3D Urb->DataLen; + Status =3D IoMmuMap (MapOp, Urb->Data, &Len, &PhyAddr, &Map); + + if (EFI_ERROR (Status) || (Len !=3D Urb->DataLen)) { + DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n= ")); + return EFI_OUT_OF_RESOURCES; + } + + Urb->DataPhy =3D (VOID *) ((UINTN) PhyAddr); + Urb->DataMap =3D Map; + } =20 // // Construct the TRB @@ -2812,6 +2838,7 @@ XhcPeiInitSched ( UINT64 *ScratchEntry; EFI_PHYSICAL_ADDRESS ScratchEntryPhy; UINT32 Index; + UINTN *ScratchEntryMap; EFI_STATUS Status; =20 // @@ -2848,6 +2875,13 @@ XhcPeiInitSched ( ASSERT (MaxScratchpadBufs <=3D 1023); if (MaxScratchpadBufs !=3D 0) { // + // Allocate the buffer to record the Mapping for each scratch buffer i= n order to Unmap them + // + ScratchEntryMap =3D AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBu= fs); + ASSERT (ScratchEntryMap !=3D NULL); + Xhc->ScratchEntryMap =3D ScratchEntryMap; + + // // Allocate the buffer to record the host address for each entry // ScratchEntry =3D AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs= ); @@ -2859,7 +2893,8 @@ XhcPeiInitSched ( EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)), Xhc->PageSize, (VOID **) &ScratchBuf, - &ScratchPhy + &ScratchPhy, + &Xhc->ScratchMap ); ASSERT_EFI_ERROR (Status); =20 @@ -2875,7 +2910,8 @@ XhcPeiInitSched ( EFI_SIZE_TO_PAGES (Xhc->PageSize), Xhc->PageSize, (VOID **) &ScratchEntry[Index], - &ScratchEntryPhy + &ScratchEntryPhy, + (VOID **) &ScratchEntryMap[Index] ); ASSERT_EFI_ERROR (Status); ZeroMem ((VOID *) (UINTN) ScratchEntry[Index], Xhc->PageSize); @@ -2967,12 +3003,13 @@ XhcPeiFreeSched ( // // Free Scratchpad Buffers // - UsbHcFreeAlignedPages ((VOID*) (UINTN) ScratchEntry[Index], EFI_SIZE= _TO_PAGES (Xhc->PageSize)); + UsbHcFreeAlignedPages ((VOID*) (UINTN) ScratchEntry[Index], EFI_SIZE= _TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]); } // // Free Scratchpad Buffer Array // - UsbHcFreeAlignedPages (Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScr= atchpadBufs * sizeof (UINT64))); + UsbHcFreeAlignedPages (Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScr= atchpadBufs * sizeof (UINT64)), Xhc->ScratchMap); + FreePool (Xhc->ScratchEntryMap); FreePool (Xhc->ScratchEntry); } =20 diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h b/MdeModulePkg/Bus/Pc= i/XhciPei/XhciSched.h index b3d4c45..faf2e63 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h @@ -170,6 +170,7 @@ typedef struct _URB { VOID *Data; UINTN DataLen; VOID *DataPhy; + VOID *DataMap; EFI_ASYNC_USB_TRANSFER_CALLBACK Callback; VOID *Context; // --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel