From nobody Thu Dec 26 12:29:07 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1505628421857850.0327603838444; Sat, 16 Sep 2017 23:07:01 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CE17621E977FF; Sat, 16 Sep 2017 23:03:55 -0700 (PDT) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 54F3621E97814 for ; Sat, 16 Sep 2017 23:03:52 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Sep 2017 23:06:54 -0700 Received: from aseyoum-mobl1.amr.corp.intel.com (HELO jyao1-MOBL.ccr.corp.intel.com) ([10.254.211.37]) by fmsmga005.fm.intel.com with ESMTP; 16 Sep 2017 23:06:53 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,406,1500966000"; d="scan'208";a="152200637" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Sun, 17 Sep 2017 14:06:47 +0800 Message-Id: <1505628407-7368-4-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1505628407-7368-1-git-send-email-jiewen.yao@intel.com> References: <1505628407-7368-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 3/3] IntelSiliconPkg/VTdInfoSample: Add RMRR table. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Let system report RMRR table for the platform support PEI graphic. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao --- IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSample= Pei.c | 156 ++++++++++++++++++-- IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSample= Pei.inf | 3 + 2 files changed, 149 insertions(+), 10 deletions(-) diff --git a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformV= TdInfoSamplePei.c b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Pl= atformVTdInfoSamplePei.c index c79398f..423e2f1 100644 --- a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoS= amplePei.c +++ b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoS= amplePei.c @@ -18,21 +18,111 @@ =20 #include #include +#include +#include + +#define R_SA_MCHBAR (0x48) +#define R_SA_GGC (0x50) +#define N_SKL_SA_GGC_GGMS_OFFSET (0x6) +#define B_SKL_SA_GGC_GGMS_MASK (0xc0) +#define N_SKL_SA_GGC_GMS_OFFSET (0x8) +#define B_SKL_SA_GGC_GMS_MASK (0xff00) +#define V_SKL_SA_GGC_GGMS_8MB 3 +#define R_SA_TOLUD (0xbc) + +#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT for IGD +#define R_SA_MCHBAR_VTD2_OFFSET 0x5410 ///< HW UNIT for all other - PEG,= USB, SATA etc =20 typedef struct { - UINT64 Revision; - UINT8 HostAddressWidth; - UINT8 Reserved[3]; - UINT32 VTdEngineCount; - UINT64 VTdEngineAddress[2]; + EFI_ACPI_DMAR_HEADER DmarHeader; + // + // VTd engine 1 - integrated graphic + // + EFI_ACPI_DMAR_DRHD_HEADER Drhd1; + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER Drhd11; + EFI_ACPI_DMAR_PCI_PATH Drhd111; + // + // VTd engine 2 - all rest + // + EFI_ACPI_DMAR_DRHD_HEADER Drhd2; + // + // RMRR 1 - integrated graphic + // + EFI_ACPI_DMAR_RMRR_HEADER Rmrr1; + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER Rmrr11; + EFI_ACPI_DMAR_PCI_PATH Rmrr111; } MY_VTD_INFO_PPI; =20 MY_VTD_INFO_PPI mPlatformVTdSample =3D { - EDKII_VTD_INFO_PPI_REVISION, - 0x26, - {0}, - 2, - {0xFED90000, 0xFED91000}, + { // DmarHeader + { // Header + EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE, + sizeof(MY_VTD_INFO_PPI), + EFI_ACPI_DMAR_REVISION, + }, + 0x26, // HostAddressWidth + }, + + { // Drhd1 + { // Header + EFI_ACPI_DMAR_TYPE_DRHD, + sizeof(EFI_ACPI_DMAR_DRHD_HEADER) + + sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) + + sizeof(EFI_ACPI_DMAR_PCI_PATH) + }, + 0, // Flags + 0, // Reserved + 0, // SegmentNumber + 0xFED90000 // RegisterBaseAddress -- TO BE PATCHED + }, + { // Drhd11 + EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT, + sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) + + sizeof(EFI_ACPI_DMAR_PCI_PATH), + 0, // Reserved2 + 0, // EnumerationId + 0 // StartBusNumber + }, + { // Drhd111 + 2, // Device + 0 // Function + }, + + { // Drhd2 + { // Header + EFI_ACPI_DMAR_TYPE_DRHD, + sizeof(EFI_ACPI_DMAR_DRHD_HEADER) + }, + EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags + 0, // Reserved + 0, // SegmentNumber + 0xFED91000 // RegisterBaseAddress -- TO BE PATCHED + }, + + { // Rmrr1 + { // Header + EFI_ACPI_DMAR_TYPE_RMRR, + sizeof(EFI_ACPI_DMAR_RMRR_HEADER) + + sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) + + sizeof(EFI_ACPI_DMAR_PCI_PATH) + }, + {0}, // Reserved + 0, // SegmentNumber + 0x0, // ReservedMemoryRegionBaseAddress -- TO BE PATCHED + 0x0 // ReservedMemoryRegionLimitAddress -- TO BE PATCHED + }, + { // Rmrr11 + EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT, + sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) + + sizeof(EFI_ACPI_DMAR_PCI_PATH), + 0, // Reserved2 + 0, // EnumerationId + 0 // StartBusNumber + }, + { // Rmrr111 + 2, // Device + 0 // Function + }, }; =20 EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc =3D { @@ -42,6 +132,50 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc =3D { }; =20 /** + Patch Graphic UMA address in RMRR and base address. +**/ +VOID +PatchDmar ( + VOID + ) +{ + UINT32 MchBar; + UINT16 IgdMode; + UINT16 GttMode; + UINT32 IgdMemSize; + UINT32 GttMemSize; + + /// + /// Calculate IGD memsize + /// + IgdMode =3D ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_= GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF; + if (IgdMode < 0xF0) { + IgdMemSize =3D IgdMode * 32 * (1024) * (1024); + } else { + IgdMemSize =3D 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024); + } + + /// + /// Calculate GTT mem size + /// + GttMemSize =3D 0; + GttMode =3D PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC) & B_SKL_SA_GGC= _GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET; + if (GttMode <=3D V_SKL_SA_GGC_GGMS_8MB) { + GttMemSize =3D (1 << GttMode) * (1024) * (1024); + } + + mPlatformVTdSample.Rmrr1.ReservedMemoryRegionBaseAddress =3D (PciRead32= (PCI_LIB_ADDRESS(0, 0, 0, R_SA_TOLUD)) & ~(0x01)) - IgdMemSize - GttMemSiz= e; + mPlatformVTdSample.Rmrr1.ReservedMemoryRegionLimitAddress =3D mPlatformV= TdSample.Rmrr1.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize - = 1; + + /// + /// Update DRHD structures of DmarTable + /// + MchBar =3D PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0; + mPlatformVTdSample.Drhd1.RegisterBaseAddress =3D (MmioRead32 (MchBar + R= _SA_MCHBAR_VTD1_OFFSET) &~1); + mPlatformVTdSample.Drhd2.RegisterBaseAddress =3D (MmioRead32 (MchBar + R= _SA_MCHBAR_VTD2_OFFSET) &~1); +} + +/** Platform VTd Info sample driver. =20 @param[in] FileHandle Handle of the file being invoked. @@ -58,6 +192,8 @@ PlatformVTdInfoSampleInitialize ( { EFI_STATUS Status; =20 + PatchDmar (); + Status =3D PeiServicesInstallPpi (&mPlatformVTdInfoSampleDesc); ASSERT_EFI_ERROR (Status); =20 diff --git a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformV= TdInfoSamplePei.inf b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/= PlatformVTdInfoSamplePei.inf index fe12821..96adb70 100644 --- a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoS= amplePei.inf +++ b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoS= amplePei.inf @@ -39,6 +39,9 @@ [LibraryClasses] PeimEntryPoint PeiServicesLib + DebugLib + PciLib + IoLib =20 [Ppis] gEdkiiVTdInfoPpiGuid ## PRODUCES --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel