From nobody Thu Dec 26 00:48:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506303970892779.8176649949661; Sun, 24 Sep 2017 18:46:10 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7969021E43B43; Sun, 24 Sep 2017 18:42:56 -0700 (PDT) Received: from mail-wr0-x22b.google.com (mail-wr0-x22b.google.com [IPv6:2a00:1450:400c:c0c::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7984D21E1B764 for ; Sun, 24 Sep 2017 18:42:54 -0700 (PDT) Received: by mail-wr0-x22b.google.com with SMTP id m18so5213516wrm.2 for ; Sun, 24 Sep 2017 18:46:05 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f16sm809520lfe.66.2017.09.24.18.46.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Sep 2017 18:46:01 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c0c::22b; helo=mail-wr0-x22b.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OnmGu2C9TFSnAbTiBL4s28PsgCK/uyZSRE3VI8w/1nc=; b=dADriURePEWEE3DTQOpL0Z5AqOAawoVD2uWhuO4OWFVXFMFKYAO7eCV86/6DWyDJ6Y M2M1vetjZeploYF6+BIw6lvbzGSv7PhPpm+3LwqAmZs2eiK2QVnl7eZvWGYl6VaoBF0J 7/FFnqIfWKaoC+8kmyC88IbsV1D5iAhevfluQ0/OmGIthZqX7flYotQn5PaBCQwVbHdl 3ABax3uePnOyjRKb00okiKL1/3jHWnBrCLjzese0Uk+qJmfrpwP4rOTZzFC4CGl2Q9qY FFKdkauulKPMSiZxD0UWCuofHLRGFNrGMKoT0lTmfhPbjaOxpYly/l6n/LDxjcaqaXQm ifgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OnmGu2C9TFSnAbTiBL4s28PsgCK/uyZSRE3VI8w/1nc=; b=Uy36jVLdR+Qu9wxoqFfuTB8VLHd7EfFn1eoXCFrnQ2KK+8k+85LkQwocoF/fqMobx2 qaqJupHCTR/8lYeHp0JBh8TKlk2tDFnddstJc7NHuBXND1Y9dovIUtp9KomeMnwAZsLU bMvl64+fNHyUqB6F1KFvK/Z6AuKTTmU3Hqb2KvWjavBQe5jUPE4DGtHEIZV727oKFSkr rk9sDpRPj/9xMYPsC+pmBZb6wIsSCp5NYhFqhlLg7SkAgzRCw1gmcWG4xvifwE9Y1hvp z/G5cNaw+fflW5bJJBp49iPHMM/fjPLdKb6TeerjCG7lW3kTKXob5w7HkotiXcjjecQD glpA== X-Gm-Message-State: AHPjjUgi7jEodyNxwWe2DMyLl1abZHE15ZFHdMr8j5pdkb6eW1rzIzRs nBNGXFbrRzt7FldMJQJpFLMj8WRr6XA= X-Google-Smtp-Source: AOwi7QDMctE7tYK52TV9Z4z3tfw59QHqV08A4Pr2zz24uEBXw/rdzKGsuT0bijR7egfjc7gmrAcSjA== X-Received: by 10.25.233.8 with SMTP id g8mr1822386lfh.197.1506303962118; Sun, 24 Sep 2017 18:46:02 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 25 Sep 2017 03:51:50 +0200 Message-Id: <1506304319-8620-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506304319-8620-1-git-send-email-mw@semihalf.com> References: <1506304319-8620-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 01/10] Silicon/Marvell: Refactor Documentation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, Nir Erez MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Nir Erez This patch introduces following improvements to the PortingGuide * Replace split documentation with single file * Update paths to new directory structure in edk2-platforms * Align format to Doxygen constraints Moreover the PortingGuide and remaining Drivers' documentation is moved to the new location under Silicon/Marvell, where in future all other bits of the support will be moved. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Documentation/Drivers/EepromDriver.txt | 96 ----- Platform/Marvell/Documentation/Drivers/I2cDriver.txt | 64 ---- Platform/Marvell/Documentation/Drivers/SpiDriver.txt | 116 ------ Platform/Marvell/Documentation/PortingGuide/ComPhy.txt | 45 --- Platform/Marvell/Documentation/PortingGuide/I2c.txt | 20 -- Platform/Marvell/Documentation/PortingGuide/Mdio.txt | 7 - Platform/Marvell/Documentation/PortingGuide/Mpp.txt | 48 --- Platform/Marvell/Documentation/PortingGuide/PciEmulation.txt | 31 -- Platform/Marvell/Documentation/PortingGuide/Phy.txt | 45 --- Platform/Marvell/Documentation/PortingGuide/Pp2.txt | 35 -- Platform/Marvell/Documentation/PortingGuide/Reset.txt | 7 - Platform/Marvell/Documentation/PortingGuide/Spi.txt | 16 - Platform/Marvell/Documentation/PortingGuide/SpiFlash.txt | 23 -- Platform/Marvell/Documentation/PortingGuide/Utmi.txt | 35 -- Silicon/Marvell/Documentation/Drivers/EepromDriver.txt | 96 +++++ Silicon/Marvell/Documentation/Drivers/I2cDriver.txt | 64 ++++ Silicon/Marvell/Documentation/Drivers/SpiDriver.txt | 116 ++++++ Silicon/Marvell/Documentation/PortingGuide.txt | 373 +++++++= +++++++++++++ 18 files changed, 649 insertions(+), 588 deletions(-) diff --git a/Platform/Marvell/Documentation/Drivers/EepromDriver.txt b/Plat= form/Marvell/Documentation/Drivers/EepromDriver.txt deleted file mode 100644 index d3b3b9f..0000000 --- a/Platform/Marvell/Documentation/Drivers/EepromDriver.txt +++ /dev/null @@ -1,96 +0,0 @@ -1. Introduction ---------------- -**MvEeprom** driver creates MARVELL_EEPROM_PROTOCOL, which -+is used for managing eeprom. - -2. MvEeprom driver design -------------------------- -Every I2C device driver should implement EFI_DRIVER_BINDING_PROTOCOL and -consume EFI_I2C_IO_PROTOCOL for transactions on I2C bus. MvEeprom driver -additionally implements MARVELL_EEPROM_PROTOCOL. - - 2.1 EFI_DRIVER_BINDING_PROTOCOL - ------------------------------- - Driver Binding protocol is extensively covered in UEFI documentation, as - it is not specific to I2C stack. The only difference is that Supported() - function should check if EFI_I2C_IO_PROTOCOL provides valid EFI_GUID and - DeviceIndex values. - Excerpt from MvEepromSupported(): - - Status =3D gBS->OpenProtocol ( - ControllerHandle, - &gEfiI2cIoProtocolGuid, - (VOID **) &TmpI2cIo, - gImageHandle, - ControllerHandle, - EFI_OPEN_PROTOCOL_BY_DRIVER - ); - if (EFI_ERROR(Status)) { - return EFI_UNSUPPORTED; - } - - /* get EEPROM devices' addresses from PCD */ - EepromAddresses =3D PcdGetPtr (PcdEepromI2cAddresses); - if (EepromAddresses =3D=3D 0) { - Status =3D EFI_UNSUPPORTED; - goto out; - } - - Status =3D EFI_UNSUPPORTED; - for (i =3D 0; EepromAddresses[i] !=3D '\0'; i++) { - /* I2C guid must fit and valid DeviceIndex must be provided */ - if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) && - TmpI2cIo->DeviceIndex =3D=3D EepromAddresses[i]) { - DEBUG((DEBUG_INFO, "A8kEepromSupported: attached to EEPROM device\= n")); - Status =3D EFI_SUCCESS; - break; - } - } - - 2.2 EFI_I2C_IO_PROTOCOL - ----------------------- - This protocol is provided by generic I2C stack. Multiple drivers can use= IO - protocol at once, as queueing is implemented. - - QueueRequest is a routine that queues an I2C transaction to the I2C - controller for execution on the I2C bus. - - 2.3 MARVELL_EEPROM_PROTOCOL - ----------------------- - typedef struct _MARVELL_EEPROM_PROTOCOL MARVELL_EEPROM_PROTOCOL; - - #define EEPROM_READ 0x1 - #define EEPROM_WRITE 0x0 - typedef - EFI_STATUS - (EFIAPI *EFI_EEPROM_TRANSFER) ( - IN CONST MARVELL_EEPROM_PROTOCOL *This, - IN UINT16 Address, - IN UINT32 Length, - IN UINT8 *Buffer, - IN UINT8 Operation - ); - - struct _MARVELL_EEPROM_PROTOCOL { - EFI_EEPROM_TRANSFER Transfer; - UINT8 Identifier; - }; - -3. Adding new I2C slave device drivers --------------------------------------- -In order to support I2C slave device other than EEPROM, new driver should -be created. Required steps follow. - - 1. Create driver directory (Platform/Marvell/Drivers/I2c/Devices/...). - 2. Create stubs of .inf and .c files (MvEeprom files are a reference), - include .inf file in platform .dsc and .fdf files. - 3. Implement EFI_DRIVER_BINDING_PROTOCOL - Start(), Stop(), Supported() - functions' implementation is a must. EFI_DRIVER_BINDING_PROTOCOL - should be installed at driver's entry point. - 4. Add I2C address of device to PcdI2cSlaveAddresses in .dsc file. - 5. Test available EFI_I2C_IO_PROTOCOLs in Supported() - find instance - with valid GUID and DeviceIndex (I2C slave address). - 6. Open EFI_I2C_IO_PROTOCOL for usage in Start(). After that, QueueReque= st - function should be available. - 7. Implement core functionality of driver (using QueueRequest to access = I2C). - 8. (not mandatory) Produce/consume additional protocols. diff --git a/Platform/Marvell/Documentation/Drivers/I2cDriver.txt b/Platfor= m/Marvell/Documentation/Drivers/I2cDriver.txt deleted file mode 100644 index 2f890de..0000000 --- a/Platform/Marvell/Documentation/Drivers/I2cDriver.txt +++ /dev/null @@ -1,64 +0,0 @@ -1. Introduction ---------------- -**MvI2cDxe** is a driver supporting I2C controller on Marvell SOCs boards. -It is connected through protocols to generic UEFI I2C stack, which exposes -IO functionality to drivers of specific devices on I2C bus. - -2. MvI2cDxe driver design --------------------------- -MvI2cDxe produces several protocols from generic I2C stack: - - EFI_I2C_MASTER_PROTOCOL, - - EFI_I2C_ENUMERATE_PROTOCOL, - - EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL - - general-purpose EFI_DRIVER_BINDING_PROTOCOL. - - 2.1 EFI_I2C_MASTER_PROTOCOL - --------------------------- - This is the most important protocol produced by MvI2cDxe. Following func= tions - are implemented: - - /// - /// Reset the I2C host controller. - /// - EFI_I2C_MASTER_PROTOCOL_RESET Reset; - - /// - /// Start an I2C transaction in master mode on the host controller. - /// - EFI_I2C_MASTER_PROTOCOL_START_REQUEST StartRequest; - - StartRequest and Reset functions are used by I2cHost. - These should **not** be used by I2C device drivers - required - synchronization is not provided. Instead, members of EFI_I2C_IO_PROTOC= OL - should be used. - - 2.2 EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL - ------------------------------------------------- - The only function exposed via this protocol is MvI2cEnableConf. It is - required by I2C stack in order to allow changing I2C bus configuration f= rom - device drivers. - - 2.3 EFI_I2C_ENUMERATE_PROTOCOL - ------------------------------ - Provides Enumerate function, which is used by I2cBus code as an iterator= over - devices on I2C bus. - - typedef - EFI_STATUS - (EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE) ( - IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This, - IN OUT CONST EFI_I2C_DEVICE **Device - ); - - /// - /// Traverse the set of I2C devices on an I2C bus. This routine - /// returns the next I2C device on an I2C bus. - /// - EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE Enumerate; - - MvI2cDevice creates EFI_I2C_DEVICE structure for every device on the bus. - Due to the fact that hardware-based I2C enumeration isn't safe, informat= ion - about attached devices should be provided through PCDs. After EFI_I2C_DE= VICE - structure is created and filled properly, it is returned to I2cBus. It is - followed by attachment of I2C device driver. - diff --git a/Platform/Marvell/Documentation/Drivers/SpiDriver.txt b/Platfor= m/Marvell/Documentation/Drivers/SpiDriver.txt deleted file mode 100644 index 42b5e3c..0000000 --- a/Platform/Marvell/Documentation/Drivers/SpiDriver.txt +++ /dev/null @@ -1,116 +0,0 @@ -1. Introduction ---------------- -**SpiDxe** driver implements MARVELL_SPI_MASTER_PROTOCOL in order to manag= e SPI -controller on Marvell A8k boards. It exposes below functionalities: - - create and setup SPI slaves - - raw transfer over SPI bus - -2. SpiDxe driver design ------------------------ - - 2.1 MARVELL_SPI_MASTER_PROTOCOL - ----------------------- - First member of SPI_MASTER protocol is Init function, implemented for SPI - master controller initialization. - - ->Init() - - // - //Initializes the host controller to execute SPI commands. - // - - param[IN] This Pointer to the MARVELL_SPI_MASTER_PROTOCOL instance - - return EFI_SUCCESS Opcode initialization on the SPI h= ost - controller completed. - return EFI_ACCESS_DENIED The SPI configuration interface is - locked. - return EFI_OUT_OF_RESOURCES Not enough resource available to - initialize the device. - return EFI_DEVICE_ERROR Device error, operation failed. - - ******** - - SPI devices (slaves) do not support any kind of automatic discovery or - enumaration, so every device needs manual configuration, which may be do= ne - with SetupDevice function. - - ->SetupDevice() - - // - //Allocate and zero all fields in the SPI_DEVICE struct. Set the chip - //select, max frequency and transfer mode supported by slave device. - // - - param[IN] Cs Chip select ID of the slave chip. - param[IN] MaxFreq Maximum SCK rate in Hz. - param[IN] Mode Clock polarity and clock phase. - - return *SPI_DEVICE Pointer to new allocated struct SPI_DEVICE. - return NULL NULL pointer if any eroor occured. - - ******** - - Developers have to destroy all created SPI device structs (with FreeDevi= ce - function) in order to prevent from memory leak. - - ->FreeDevice() - - // - //Free any memory associated with a SPI device. - // - - param[in] SpiDev Pointer to the SPI_DEVICE struct. - - return EFI_SUCCESS Memory fried succesfully. - return EFI_DEVICE_ERROR Device error, operation failed. - - ******** - - Transfer function allows write/read raw bytes over SPI bus. - - ->Transfer() - - // - //Perform transfer over SPI bus - // - param[in] This Pointer to the MARVELL_SPI_MASTER_= PROTOCOL - instance. - param[in] Slave Pointer to the SPI_DEVICE struct. - param[in] DataByteCount Number of bytes in the data portio= n of - the SPI cycle. - param[in] DataOut Pointer to caller-allocated buffer - containing the data to send. - param[out] DataIn Pointer to caller-allocated buffer - where received data will be placed. - param[in] Flag Flags which indicate state of CS l= ine - during/after transfer (see file - Drivers/Spi/Devices/A8kSpiFlash.h) - - return EFI_SUCCESS Memory fried succesfully. - return EFI_DEVICE_ERROR Device error, operation failed. - - ********* - - When working with SPI devices it is often necessary to perform "command = and - address" transactions. It may be done via ReadWrite function. - - ->ReadWrite() - - // - //Perform two steps transactions. First write Command, then read/write - //buffer - // - - param[in] This Pointer to the MARVELL_SPI_MASTER_= PROTOCOL - instance. - param[in] Slave Pointer to the SPI_DEVICE struct. - param[in] Cmd Pointer to caller-allocated buffer - containing the command to send. - param[in] CmdSize Size of command (in bytes). - param[in] DataOut Pointer to caller-allocated buffer - containing the data to send. - param[out] DataIn Pointer to caller-allocated buffer - where received data will be placed. - param[in] DataSize Number of bytes in the data portio= n of - the SPI cycle. diff --git a/Platform/Marvell/Documentation/PortingGuide/ComPhy.txt b/Platf= orm/Marvell/Documentation/PortingGuide/ComPhy.txt deleted file mode 100644 index a96015e..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/ComPhy.txt +++ /dev/null @@ -1,45 +0,0 @@ -COMPHY configuration ---------------------------- -In order to configure ComPhy library, following PCDs are available: - - gMarvellTokenSpaceGuid.PcdComPhyDevices - -This array indicates, which ones of the ComPhy chips defined in -MVHW_COMPHY_DESC template will be configured. - -Every ComPhy PCD has part where stands for chip ID (order is n= ot -important, but configuration will be set for first PcdComPhyChipCount chip= s). - -Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes -settings for this chip. Their format is unicode string, containing settings -for up to 10 lanes. Setting for each one is separated with semicolon. -These PCDs together describe outputs of PHY integrated in simple cihp. -Below is example for the first chip (Chip0). - - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes - -Unicode string indicating PHY types. Currently supported are: - -{ L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", -L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", -L"SGMII1", L"SGMII2", L"SGMII3", -L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", -L"RXAUI0", L"RXAUI1", L"SFI" } - - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds - -Indicates PHY speeds in MHz. Currently supported are: - -{ 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 10310 } - - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags - -Indicates lane polarity invert. - -Example -------- - #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1= ;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;= 5000" - diff --git a/Platform/Marvell/Documentation/PortingGuide/I2c.txt b/Platform= /Marvell/Documentation/PortingGuide/I2c.txt deleted file mode 100644 index 020ffb4..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/I2c.txt +++ /dev/null @@ -1,20 +0,0 @@ -1. Porting I2C driver to a new SOC ----------------------------------- -In order to enable driver on a new platform, following steps need to be ta= ken: - - add following line to .dsc file: - Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf - - add following line to .fdf file: - INF Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf - - add PCDs with relevant values to .dsc file: - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } - (addresses of I2C slave devices on bus) - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } - (buses to which accoring slaves are attached) - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 - (number of SoC's I2C buses) - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" - (base addresses of I2C controller buses) - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 - (I2C host controller clock frequency) - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 - (baud rate used in I2C transmission) diff --git a/Platform/Marvell/Documentation/PortingGuide/Mdio.txt b/Platfor= m/Marvell/Documentation/PortingGuide/Mdio.txt deleted file mode 100644 index c341d9e..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Mdio.txt +++ /dev/null @@ -1,7 +0,0 @@ -MDIO driver configuration -------------------------- -MDIO driver provides access to network PHYs' registers via MARVELL_MDIO_RE= AD and -MARVELL_MDIO_WRITE functions (MARVELL_MDIO_PROTOCOL). Following PCD is req= uired: - - gMarvellTokenSpaceGuid.PcdMdioBaseAddress - (base address of SMI management register) diff --git a/Platform/Marvell/Documentation/PortingGuide/Mpp.txt b/Platform= /Marvell/Documentation/PortingGuide/Mpp.txt deleted file mode 100644 index 68f0e9d..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Mpp.txt +++ /dev/null @@ -1,48 +0,0 @@ -MPP configuration ------------------ -Multi-Purpose Ports (MPP) are configurable through platform PCDs. -In order to set desired pin multiplexing, .dsc file needs to be modified. -(Platform/Marvell/Armada/{platform_name}.dsc - please refer to -Documentation/Build.txt for currently supported {platftorm_name} ) -Following PCDs are available: - - gMarvellTokenSpaceGuid.PcdMppChipCount - -Indicates how many different chips are placed on board. So far up to 4 chi= ps -are supported. - -Every MPP PCD has part where - stands for chip ID (order is not important, but configuration will = be - set for first PcdMppChipCount chips). - -Below is example for the first chip (Chip0). - - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag - -Indicates that register order is reversed. (Needs to be used only for AP80= 6-Z1) - - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress - -This is base address for MPP configuration register. - - gMarvellTokenSpaceGuid.PcdChip0MppPinCount - -Defines how many MPP pins are available. - - gMarvellTokenSpaceGuid.PcdChip0MppSel0 - gMarvellTokenSpaceGuid.PcdChip0MppSel1 - gMarvellTokenSpaceGuid.PcdChip0MppSel2 - -This registers defines functions of 10 pins in ascending order. - -Examples --------- -#APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x= 1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x= 0, 0x0, 0x0, 0x0 } - -Set pin 6 and 7 to 0xa function: - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x= a, 0xa, 0x0, 0x0 } diff --git a/Platform/Marvell/Documentation/PortingGuide/PciEmulation.txt b= /Platform/Marvell/Documentation/PortingGuide/PciEmulation.txt deleted file mode 100644 index ec1afbc..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/PciEmulation.txt +++ /dev/null @@ -1,31 +0,0 @@ -PciEmulation configuration --------------------------- -Installation of various NonDiscoverable devices via PciEmulation driver is= performed -via set of PCDs. Following are available: - - gMarvellTokenSpaceGuid.PcdPciEXhci - -Indicates, which Xhci devices are used. - - gMarvellTokenSpaceGuid.PcdPciEAhci - -Indicates, which Ahci devices are used. - - gMarvellTokenSpaceGuid.PcdPciESdhci - -Indicates, which Sdhci devices are used. - -All above PCD's correspond to hardware description in a dedicated structur= e: - -STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate - -in Platforms/Marvell/PciEmulation/PciEmulation.c file. It comprises device -count, base addresses, register region size and DMA-coherency type. - -Examples --------- -Assuming we want to enable second XHCI port and one SDHCI port on Armada -70x0 board, following needs to be declared: - - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } diff --git a/Platform/Marvell/Documentation/PortingGuide/Phy.txt b/Platform= /Marvell/Documentation/PortingGuide/Phy.txt deleted file mode 100644 index 69dae02..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Phy.txt +++ /dev/null @@ -1,45 +0,0 @@ -PHY driver configuration ------------------------- -MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. -Currently only 1512 series PHYs are supported. Following PCDs are required: - - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes - (list of values corresponding to PHY_CONNECTION enum) - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg - (boolean - if true, driver waits for autonegotiation on startup) - gMarvellTokenSpaceGuid.PcdPhyDeviceIds - (list of values corresponding to MV_PHY_DEVICE_ID enum) - -PHY_CONNECTION enum type is defined as follows: - - typedef enum { -0 PHY_CONNECTION_RGMII, -1 PHY_CONNECTION_RGMII_ID, -2 PHY_CONNECTION_RGMII_TXID, -3 PHY_CONNECTION_RGMII_RXID, -4 PHY_CONNECTION_SGMII, -5 PHY_CONNECTION_RTBI, -6 PHY_CONNECTION_XAUI, -7 PHY_CONNECTION_RXAUI - } PHY_CONNECTION; - -MV_PHY_DEVICE_ID: - - typedef enum { -0 MV_PHY_DEVICE_1512, - } MV_PHY_DEVICE_ID; - -It should be extended when adding support for other PHY -models. - -Thus in order to set RGMII for 1st PHY and SGMII for 2nd, PCD should be: - - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x4 } - -with disabled autonegotiation: - - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE - -assuming, that PHY models are 1512: - - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform= /Marvell/Documentation/PortingGuide/Pp2.txt deleted file mode 100644 index f05ba27..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt +++ /dev/null @@ -1,35 +0,0 @@ -Pp2Dxe porting guide --------------------- -Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs -are required to operate: - -Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled: - gMarvellTokenSpaceGuid.PcdPp2Controllers - -Array specifying, to which controller the port belongs to: - gMarvellTokenSpaceGuid.PcdPp2Port2Controller - -Addresses of PHY devices: - gMarvellTokenSpaceGuid.PcdPhySmiAddresses - -Identificators of PP2 ports: - gMarvellTokenSpaceGuid.PcdPp2PortIds - -Indexes used in GOP operation: - gMarvellTokenSpaceGuid.PcdPp2GopIndexes - -Set to 0x1 for always-up interface, 0x0 otherwise: - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp - -Values corresponding to PHY_SPEED enum: - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed - -PHY_SPEED (in Mbps) is defined as follows: - typedef enum { - 0 NO_SPEED, - 1 SPEED_10, - 2 SPEED_100, - 3 SPEED_1000, - 4 SPEED_2500, - 5 SPEED_10000 - } PHY_SPEED; diff --git a/Platform/Marvell/Documentation/PortingGuide/Reset.txt b/Platfo= rm/Marvell/Documentation/PortingGuide/Reset.txt deleted file mode 100644 index 30dec86..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Reset.txt +++ /dev/null @@ -1,7 +0,0 @@ -MarvellResetSystemLib configuration ------------------------------------ -This simple library allows to mask given bits in given reg at UEFI 'reset' -command call. These variables are configurable through PCDs: - - gMarvellTokenSpaceGuid.PcdResetRegAddress - gMarvellTokenSpaceGuid.PcdResetRegMask diff --git a/Platform/Marvell/Documentation/PortingGuide/Spi.txt b/Platform= /Marvell/Documentation/PortingGuide/Spi.txt deleted file mode 100644 index be498a6..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Spi.txt +++ /dev/null @@ -1,16 +0,0 @@ -Spi driver configuration ------------------------- -Following PCDs are available for configuration of spi driver: - - gMarvellTokenSpaceGuid.PcdSpiClockFrequency - -Frequency (in Hz) of SPI clock - - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency - -Max SCLK line frequency (in Hz) (max transfer frequency) - - gMarvellTokenSpaceGuid.PcdSpiDefaultMode - -default SCLK mode (see SPI_MODE enum in file -Platform/Marvell/Drivers/Spi/MvSpi.h) diff --git a/Platform/Marvell/Documentation/PortingGuide/SpiFlash.txt b/Pla= tform/Marvell/Documentation/PortingGuide/SpiFlash.txt deleted file mode 100644 index 226db40..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/SpiFlash.txt +++ /dev/null @@ -1,23 +0,0 @@ -SpiFlash driver configuration ------------------------------ -Folowing PCDs for spi flash driver configuration must be set properly: - - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles - -Size of SPI flash address in bytes (3 or 4) - - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize - -Size of minimal erase block in bytes - - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize - -Size of SPI flash page - - gMarvellTokenSpaceGuid.PcdSpiFlashId - -Id of SPI flash - - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd - -Spi flash polling flag diff --git a/Platform/Marvell/Documentation/PortingGuide/Utmi.txt b/Platfor= m/Marvell/Documentation/PortingGuide/Utmi.txt deleted file mode 100644 index cff4843..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Utmi.txt +++ /dev/null @@ -1,35 +0,0 @@ -UTMI PHY configuration ----------------------- -In order to configure UTMI, following PCDs are available: - - gMarvellTokenSpaceGuid.PcdUtmiPhyCount - -Indicates how many UTMI PHYs are available on platform. - -Next four PCDs are in unicode string format containing settings for all de= vices -separated with semicolon. - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit - -Indicates base address of the UTMI unit. - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg - -Indicates address of USB Configuration register. - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg - -Indicates address of external UTMI configuration. - - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort - -Indicates type of the connected USB port. - -Example -------- -#UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444" - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" diff --git a/Silicon/Marvell/Documentation/Drivers/EepromDriver.txt b/Silic= on/Marvell/Documentation/Drivers/EepromDriver.txt new file mode 100644 index 0000000..d3b3b9f --- /dev/null +++ b/Silicon/Marvell/Documentation/Drivers/EepromDriver.txt @@ -0,0 +1,96 @@ +1. Introduction +--------------- +**MvEeprom** driver creates MARVELL_EEPROM_PROTOCOL, which ++is used for managing eeprom. + +2. MvEeprom driver design +------------------------- +Every I2C device driver should implement EFI_DRIVER_BINDING_PROTOCOL and +consume EFI_I2C_IO_PROTOCOL for transactions on I2C bus. MvEeprom driver +additionally implements MARVELL_EEPROM_PROTOCOL. + + 2.1 EFI_DRIVER_BINDING_PROTOCOL + ------------------------------- + Driver Binding protocol is extensively covered in UEFI documentation, as + it is not specific to I2C stack. The only difference is that Supported() + function should check if EFI_I2C_IO_PROTOCOL provides valid EFI_GUID and + DeviceIndex values. + Excerpt from MvEepromSupported(): + + Status =3D gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &TmpI2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR(Status)) { + return EFI_UNSUPPORTED; + } + + /* get EEPROM devices' addresses from PCD */ + EepromAddresses =3D PcdGetPtr (PcdEepromI2cAddresses); + if (EepromAddresses =3D=3D 0) { + Status =3D EFI_UNSUPPORTED; + goto out; + } + + Status =3D EFI_UNSUPPORTED; + for (i =3D 0; EepromAddresses[i] !=3D '\0'; i++) { + /* I2C guid must fit and valid DeviceIndex must be provided */ + if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) && + TmpI2cIo->DeviceIndex =3D=3D EepromAddresses[i]) { + DEBUG((DEBUG_INFO, "A8kEepromSupported: attached to EEPROM device\= n")); + Status =3D EFI_SUCCESS; + break; + } + } + + 2.2 EFI_I2C_IO_PROTOCOL + ----------------------- + This protocol is provided by generic I2C stack. Multiple drivers can use= IO + protocol at once, as queueing is implemented. + + QueueRequest is a routine that queues an I2C transaction to the I2C + controller for execution on the I2C bus. + + 2.3 MARVELL_EEPROM_PROTOCOL + ----------------------- + typedef struct _MARVELL_EEPROM_PROTOCOL MARVELL_EEPROM_PROTOCOL; + + #define EEPROM_READ 0x1 + #define EEPROM_WRITE 0x0 + typedef + EFI_STATUS + (EFIAPI *EFI_EEPROM_TRANSFER) ( + IN CONST MARVELL_EEPROM_PROTOCOL *This, + IN UINT16 Address, + IN UINT32 Length, + IN UINT8 *Buffer, + IN UINT8 Operation + ); + + struct _MARVELL_EEPROM_PROTOCOL { + EFI_EEPROM_TRANSFER Transfer; + UINT8 Identifier; + }; + +3. Adding new I2C slave device drivers +-------------------------------------- +In order to support I2C slave device other than EEPROM, new driver should +be created. Required steps follow. + + 1. Create driver directory (Platform/Marvell/Drivers/I2c/Devices/...). + 2. Create stubs of .inf and .c files (MvEeprom files are a reference), + include .inf file in platform .dsc and .fdf files. + 3. Implement EFI_DRIVER_BINDING_PROTOCOL - Start(), Stop(), Supported() + functions' implementation is a must. EFI_DRIVER_BINDING_PROTOCOL + should be installed at driver's entry point. + 4. Add I2C address of device to PcdI2cSlaveAddresses in .dsc file. + 5. Test available EFI_I2C_IO_PROTOCOLs in Supported() - find instance + with valid GUID and DeviceIndex (I2C slave address). + 6. Open EFI_I2C_IO_PROTOCOL for usage in Start(). After that, QueueReque= st + function should be available. + 7. Implement core functionality of driver (using QueueRequest to access = I2C). + 8. (not mandatory) Produce/consume additional protocols. diff --git a/Silicon/Marvell/Documentation/Drivers/I2cDriver.txt b/Silicon/= Marvell/Documentation/Drivers/I2cDriver.txt new file mode 100644 index 0000000..2f890de --- /dev/null +++ b/Silicon/Marvell/Documentation/Drivers/I2cDriver.txt @@ -0,0 +1,64 @@ +1. Introduction +--------------- +**MvI2cDxe** is a driver supporting I2C controller on Marvell SOCs boards. +It is connected through protocols to generic UEFI I2C stack, which exposes +IO functionality to drivers of specific devices on I2C bus. + +2. MvI2cDxe driver design +-------------------------- +MvI2cDxe produces several protocols from generic I2C stack: + - EFI_I2C_MASTER_PROTOCOL, + - EFI_I2C_ENUMERATE_PROTOCOL, + - EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL + - general-purpose EFI_DRIVER_BINDING_PROTOCOL. + + 2.1 EFI_I2C_MASTER_PROTOCOL + --------------------------- + This is the most important protocol produced by MvI2cDxe. Following func= tions + are implemented: + + /// + /// Reset the I2C host controller. + /// + EFI_I2C_MASTER_PROTOCOL_RESET Reset; + + /// + /// Start an I2C transaction in master mode on the host controller. + /// + EFI_I2C_MASTER_PROTOCOL_START_REQUEST StartRequest; + + StartRequest and Reset functions are used by I2cHost. + These should **not** be used by I2C device drivers - required + synchronization is not provided. Instead, members of EFI_I2C_IO_PROTOC= OL + should be used. + + 2.2 EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL + ------------------------------------------------- + The only function exposed via this protocol is MvI2cEnableConf. It is + required by I2C stack in order to allow changing I2C bus configuration f= rom + device drivers. + + 2.3 EFI_I2C_ENUMERATE_PROTOCOL + ------------------------------ + Provides Enumerate function, which is used by I2cBus code as an iterator= over + devices on I2C bus. + + typedef + EFI_STATUS + (EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE) ( + IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This, + IN OUT CONST EFI_I2C_DEVICE **Device + ); + + /// + /// Traverse the set of I2C devices on an I2C bus. This routine + /// returns the next I2C device on an I2C bus. + /// + EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE Enumerate; + + MvI2cDevice creates EFI_I2C_DEVICE structure for every device on the bus. + Due to the fact that hardware-based I2C enumeration isn't safe, informat= ion + about attached devices should be provided through PCDs. After EFI_I2C_DE= VICE + structure is created and filled properly, it is returned to I2cBus. It is + followed by attachment of I2C device driver. + diff --git a/Silicon/Marvell/Documentation/Drivers/SpiDriver.txt b/Silicon/= Marvell/Documentation/Drivers/SpiDriver.txt new file mode 100644 index 0000000..42b5e3c --- /dev/null +++ b/Silicon/Marvell/Documentation/Drivers/SpiDriver.txt @@ -0,0 +1,116 @@ +1. Introduction +--------------- +**SpiDxe** driver implements MARVELL_SPI_MASTER_PROTOCOL in order to manag= e SPI +controller on Marvell A8k boards. It exposes below functionalities: + - create and setup SPI slaves + - raw transfer over SPI bus + +2. SpiDxe driver design +----------------------- + + 2.1 MARVELL_SPI_MASTER_PROTOCOL + ----------------------- + First member of SPI_MASTER protocol is Init function, implemented for SPI + master controller initialization. + + ->Init() + + // + //Initializes the host controller to execute SPI commands. + // + + param[IN] This Pointer to the MARVELL_SPI_MASTER_PROTOCOL instance + + return EFI_SUCCESS Opcode initialization on the SPI h= ost + controller completed. + return EFI_ACCESS_DENIED The SPI configuration interface is + locked. + return EFI_OUT_OF_RESOURCES Not enough resource available to + initialize the device. + return EFI_DEVICE_ERROR Device error, operation failed. + + ******** + + SPI devices (slaves) do not support any kind of automatic discovery or + enumaration, so every device needs manual configuration, which may be do= ne + with SetupDevice function. + + ->SetupDevice() + + // + //Allocate and zero all fields in the SPI_DEVICE struct. Set the chip + //select, max frequency and transfer mode supported by slave device. + // + + param[IN] Cs Chip select ID of the slave chip. + param[IN] MaxFreq Maximum SCK rate in Hz. + param[IN] Mode Clock polarity and clock phase. + + return *SPI_DEVICE Pointer to new allocated struct SPI_DEVICE. + return NULL NULL pointer if any eroor occured. + + ******** + + Developers have to destroy all created SPI device structs (with FreeDevi= ce + function) in order to prevent from memory leak. + + ->FreeDevice() + + // + //Free any memory associated with a SPI device. + // + + param[in] SpiDev Pointer to the SPI_DEVICE struct. + + return EFI_SUCCESS Memory fried succesfully. + return EFI_DEVICE_ERROR Device error, operation failed. + + ******** + + Transfer function allows write/read raw bytes over SPI bus. + + ->Transfer() + + // + //Perform transfer over SPI bus + // + param[in] This Pointer to the MARVELL_SPI_MASTER_= PROTOCOL + instance. + param[in] Slave Pointer to the SPI_DEVICE struct. + param[in] DataByteCount Number of bytes in the data portio= n of + the SPI cycle. + param[in] DataOut Pointer to caller-allocated buffer + containing the data to send. + param[out] DataIn Pointer to caller-allocated buffer + where received data will be placed. + param[in] Flag Flags which indicate state of CS l= ine + during/after transfer (see file + Drivers/Spi/Devices/A8kSpiFlash.h) + + return EFI_SUCCESS Memory fried succesfully. + return EFI_DEVICE_ERROR Device error, operation failed. + + ********* + + When working with SPI devices it is often necessary to perform "command = and + address" transactions. It may be done via ReadWrite function. + + ->ReadWrite() + + // + //Perform two steps transactions. First write Command, then read/write + //buffer + // + + param[in] This Pointer to the MARVELL_SPI_MASTER_= PROTOCOL + instance. + param[in] Slave Pointer to the SPI_DEVICE struct. + param[in] Cmd Pointer to caller-allocated buffer + containing the command to send. + param[in] CmdSize Size of command (in bytes). + param[in] DataOut Pointer to caller-allocated buffer + containing the data to send. + param[out] DataIn Pointer to caller-allocated buffer + where received data will be placed. + param[in] DataSize Number of bytes in the data portio= n of + the SPI cycle. diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt new file mode 100644 index 0000000..aa53329 --- /dev/null +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -0,0 +1,373 @@ +UEFI Porting Guide +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This document provides instructions for adding support for new Marvell Arm= ada +board. For the sake of simplicity new Marvell board will be called "new_bo= ard". + +1. Create configuration files for new target + 1.1 Create FDF file for new board + + - Copy and rename edk2-platforms/Platform/Marvell/Armada/Armada70x0.fdf = to + edk2-platforms/Platform/Marvell/Armada/new_board.fdf + - Change the first no-comment line: + [FD.Armada70x0_EFI] to [FD.{new_board}_EFI] + + 1.2 Create DSC file for new board + + - Add new_board.dsc file to edk2-platforms/Platform/Marvell/Armada direc= tory + - Insert following [Defines] section to new_board.dsc: + + [Defines] + PLATFORM_NAME =3D {new_board} + PLATFORM_GUID =3D {newly_generated_GUID} + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010019 + OUTPUT_DIRECTORY =3D {output_directory} + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D {path_to_fdf_file} + + - Add "!include Armada.dsc.inc" entry to new_board.dsc + +2. Driver support + - According to content of files from + edk2-platforms/Silicon/Marvell/Documentation/PortingGuide.txt + insert PCD entries into new_board.dsc for every needed interface (as li= sted below). + +3. Compilation + - Refer to edk2-platforms/Platform/Marvell/Readme.md. Remember to change + {platform} to new_board in order to point build system to newly created= DSC file. + +4. Output file + - Output files (and among others FD file, which may be used by ATF) are + generated under directory pointed by "OUTPUT_DIRECTORY" entry (see poin= t 1.2). + + +COMPHY configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to configure ComPhy library, following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdComPhyDevices + +This array indicates, which ones of the ComPhy chips defined in +MVHW_COMPHY_DESC template will be configured. + +Every ComPhy PCD has part where stands for chip ID (order is n= ot +important, but configuration will be set for first PcdComPhyChipCount chip= s). + +Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes +settings for this chip. Their format is unicode string, containing settings +for up to 10 lanes. Setting for each one is separated with semicolon. +These PCDs together describe outputs of PHY integrated in simple cihp. +Below is example for the first chip (Chip0). + + - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + (Unicode string indicating PHY types. Currently supported are: + + { L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", + L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", + L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", + L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", + L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0", + L"RXAUI1", L"KR" } ) + + - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds + (Indicates PHY speeds in MHz. Currently supported are: + { 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 1031 } ) + + - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags + (Indicates lane polarity invert) + +Example +------- + + #ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SAT= A1;USB3_HOST1;PCIE2" + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;500= 0;5000" + + +PHY Driver configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. +Currently only 1518 series PHYs are supported. Following PCDs are required: + + - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes + (list of values corresponding to PHY_CONNECTION enum) + - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + (boolean - if true, driver waits for autonegotiation on startup) + - gMarvellTokenSpaceGuid.PcdPhyDeviceIds + (list of values corresponding to MV_PHY_DEVICE_ID enum) + +PHY_CONNECTION enum type is defined as follows: + + typedef enum { + 0 PHY_CONNECTION_RGMII, + 1 PHY_CONNECTION_RGMII_ID, + 2 PHY_CONNECTION_RGMII_TXID, + 3 PHY_CONNECTION_RGMII_RXID, + 4 PHY_CONNECTION_SGMII, + 5 PHY_CONNECTION_RTBI, + 6 PHY_CONNECTION_XAUI, + 7 PHY_CONNECTION_RXAUI + } PHY_CONNECTION; + +MV_PHY_DEVICE_ID: + + typedef enum { + 0 MV_PHY_DEVICE_1512, + } MV_PHY_DEVICE_ID; + +It should be extended when adding support for other PHY models. +Thus in order to set RGMII for 1st PHY and SGMII for 2nd, PCD should be: + + gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x4 } + +with disabled autonegotiation: + + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + +assuming, that PHY models are 1512: + + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + + +MDIO configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ a= nd +EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required: + + - gMarvellTokenSpaceGuid.PcdMdioBaseAddress + (base address of SMI management register) + + +I2C configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to enable driver on a new platform, following steps need to be ta= ken: + - add following line to .dsc file: + edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf + - add following line to .fdf file: + INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf + - add PCDs with relevant values to .dsc file: + - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } + (addresses of I2C slave devices on bus) + - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } + (buses to which accoring slaves are attached) + - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + (number of SoC's I2C buses) + - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" + (base addresses of I2C controller buses) + - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 + (I2C host controller clock frequency) + - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + (baud rate used in I2C transmission) + + +PciEmulation configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +Installation of various NonDiscoverable devices via PciEmulation driver is= performed +via set of PCDs. Following are available: + + - gMarvellTokenSpaceGuid.PcdPciEXhci + (Indicates, which Xhci devices are used) + + - gMarvellTokenSpaceGuid.PcdPciEAhci + (Indicates, which Ahci devices are used) + + - gMarvellTokenSpaceGuid.PcdPciESdhci + (Indicates, which Sdhci devices are used) + +All above PCD's correspond to hardware description in a dedicated structur= e: + +STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate + +in Platform/Marvell/PciEmulation/PciEmulation.c file. It comprises device +count, base addresses, register region size and DMA-coherency type. + +Example +------- + +Assuming we want to enable second XHCI port and one SDHCI port on Armada +70x0 board, following needs to be declared: + + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } + + +SATA configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +There is one additional PCD for AHCI: + + - gMarvellTokenSpaceGuid.PcdSataBaseAddress + (Base address of SATA controller register space - used in SATA ComPhy init + sequence) + + +Pp2Dxe configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs +are required to operate: + + - gMarvellTokenSpaceGuid.PcdPp2Controllers + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) + + - gMarvellTokenSpaceGuid.PcdPp2Port2Controller + (Array specifying, to which controller the port belongs to) + + - gMarvellTokenSpaceGuid.PcdPhySmiAddresses + (Addresses of PHY devices) + + - gMarvellTokenSpaceGuid.PcdPp2PortIds + (Identificators of PP2 ports) + + - gMarvellTokenSpaceGuid.PcdPp2GopIndexes + (Indexes used in GOP operation) + + - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp + (Set to 0x1 for always-up interface, 0x0 otherwise) + + - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed + (Values corresponding to PHY_SPEED enum. + PHY_SPEED is defined as follows: + + typedef enum { + 0 NO_SPEED, + 1 SPEED_10, + 2 SPEED_100, + 3 SPEED_1000, + 4 SPEED_2500, + 5 SPEED_10000 + } PHY_SPEED; + + +UTMI PHY configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to configure UTMI, following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdUtmiPhyCount + (Indicates how many UTMI PHYs are available on platform) + +Next four PCDs are in unicode string format containing settings for all de= vices +separated with semicolon. + + - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit + (Indicates base address of the UTMI unit) + + - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg + (Indicates address of USB Configuration register) + + - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg + (Indicates address of external UTMI configuration) + + - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort + (Indicates type of the connected USB port) + +Example +------- + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 + gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" + gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420" + gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444" + gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" + + +SPI driver configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Following PCDs are available for configuration of spi driver: + + - gMarvellTokenSpaceGuid.PcdSpiClockFrequency + (Frequency (in Hz) of SPI clock) + + - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency + (Max SCLK line frequency (in Hz) (max transfer frequency) ) + + - gMarvellTokenSpaceGuid.PcdSpiDefaultMode + (default SCLK mode (see SPI_MODE enum in file + edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h) ) + + +SpiFlash configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Folowing PCDs for spi flash driver configuration must be set properly: + + - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles + (Size of SPI flash address in bytes (3 or 4) ) + + - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize + (Size of minimal erase block in bytes) + + - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize + (Size of SPI flash page) + + - gMarvellTokenSpaceGuid.PcdSpiFlashId + (Id of SPI flash) + + - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd + (Spi flash polling flag) + + +MPP configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Multi-Purpose Ports (MPP) are configurable through platform PCDs. +In order to set desired pin multiplexing, .dsc file needs to be modified. +(edk2-platforms/Platform/Marvell/Armada/{platform_name}.dsc - please refer= to +Documentation/Build.txt for currently supported {platftorm_name} ) +Following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdMppChipCount + (Indicates how many different chips are placed on board. So far up to 4 c= hips + are supported) + +Every MPP PCD has part where + stands for chip ID (order is not important, but configuration will = be + set for first PcdMppChipCount chips). + +Below is example for the first chip (Chip0). + + - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag + (Indicates that register order is reversed. (Needs to be used only for AP= 806-Z1) ) + + - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress + (This is base address for MPP configuration register) + + - gMarvellTokenSpaceGuid.PcdChip0MppPinCount + (Defines how many MPP pins are available) + + - gMarvellTokenSpaceGuid.PcdChip0MppSel0 + - gMarvellTokenSpaceGuid.PcdChip0MppSel1 + - gMarvellTokenSpaceGuid.PcdChip0MppSel2 + (This registers defines functions of 10 pins in ascending order) + +Examples +-------- + + # APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, = 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, = 0x0, 0x0, 0x0, 0x0 } + +Set pin 6 and 7 to 0xa function: + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, = 0xa, 0xa, 0x0, 0x0 } + + +MarvellResetSystemLib configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +This simple library allows to mask given bits in given reg at UEFI 'reset' +command call. These variables are configurable through PCDs: + + - gMarvellTokenSpaceGuid.PcdResetRegAddress + - gMarvellTokenSpaceGuid.PcdResetRegMask + + +Ramdisk configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +There is one PCD available for Ramdisk configuration + + - gMarvellTokenSpaceGuid.PcdRamDiskSize + (Defines size of Ramdisk) --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 00:48:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506303969791236.4111271686685; Sun, 24 Sep 2017 18:46:09 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3815D21E2BE37; Sun, 24 Sep 2017 18:42:56 -0700 (PDT) Received: from mail-wr0-x231.google.com (mail-wr0-x231.google.com [IPv6:2a00:1450:400c:c0c::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 526D920945B97 for ; Sun, 24 Sep 2017 18:42:54 -0700 (PDT) Received: by mail-wr0-x231.google.com with SMTP id o42so5214131wrb.3 for ; Sun, 24 Sep 2017 18:46:05 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f16sm809520lfe.66.2017.09.24.18.46.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Sep 2017 18:46:02 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c0c::231; helo=mail-wr0-x231.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vxVLv+gZbRrpa9WIppz1hoh0fkwXNW8TVs3K8zPq9ns=; b=s7J5mXr7nUan2NeaU15Smbm0ZJHL7lEj5KaP0xN59omRMQdDTUXtf/EqDXdM5fPobI 3UE9f0ywbVWbr17OLwlv00C1Zq4tcP7MXgtyr157jwIRybwmjuC30hCZxOdAWcu6h4Aw YYLnI9E7vNEJ65fGxLmUzvcxix2qV9mQwaFjwC5C+NmQ/BBwLt4WVS9KFq0QKYBqpbcL 15Te12UqiCUnMvWiba+ZRkgv5Zl36xDX7ZgsUZvh0ii1kk/q8nOCZ2XRzoi9YnzG4fTj GQeaKkKMN3UFfwVQzbppusnV8gcg99N2l6hbp/toJyqLZm75fK3u3FQOGha+7p1C2Ot4 CgsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vxVLv+gZbRrpa9WIppz1hoh0fkwXNW8TVs3K8zPq9ns=; b=JLvSwmn+z/YcQs4IORPa3+7w+/1e8/LNkai3hjWch+enGrEDL/wzxr6JM+OODG3r7Y igYDkuqLAEOT9Q9qSRzx+PsOSu/rNIVFJ21PCE1J2kXbtpGb5qzn7W7AiJaKrGyihnTJ KvitGswhCM5iuUWbr9AJNqaYOkfxKQHzoAx5+5MQjLDW+/PlMp/91+AaiFfHx5leytGj WmSl7PWF0YGSrKMq2BGsyd4rEOJwuJ1iISPveWG6TVygPbZd42ahxnVcen44zM+sWk6E tKiMZishmR65iLmqhzwzvOB2pOn6czLrtLhAIRp2ro22iZ+DQmuRPyeHDjupzYlwGGkR jvNQ== X-Gm-Message-State: AHPjjUinuZOc/G6zJR0rUboWxlUHdslszh++iVKV/Gf4GA+IkPvO0L9i xtaxo8o1xE1NY1DRhCa3+CEGQpkXZ9s= X-Google-Smtp-Source: AOwi7QBHtOYyUtOYBQjXuC4lS7UydT2ZB+1YrAl1fYxYF8GWTaPSGRLTjZHiiQ9ZNmFqWoxYi4CUGA== X-Received: by 10.25.72.16 with SMTP id v16mr1600106lfa.72.1506303963425; Sun, 24 Sep 2017 18:46:03 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 25 Sep 2017 03:51:51 +0200 Message-Id: <1506304319-8620-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506304319-8620-1-git-send-email-mw@semihalf.com> References: <1506304319-8620-1-git-send-email-mw@semihalf.com> MIME-Version: 1.0 Subject: [edk2] [platforms: PATCH 02/10] Marvell/Drivers: MvSpiDxe: Log and return correct error X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, =?UTF-8?q?Piotr=20Kr=C3=B3l?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 From: Piotr Kr=C3=B3l Make log information clear where it came from and return correct code to be interpreted by caller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Piotr Kr=C3=B3l Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index aab20fc..0c6b624 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -240,7 +240,8 @@ MvSpiTransfer ( } =20 if (Iterator >=3D SPI_TIMEOUT) { - DEBUG ((DEBUG_ERROR, "Timeout\n")); + DEBUG ((DEBUG_ERROR, "%s: Timeout\n", __FUNCTION__)); + return EFI_TIMEOUT; } } =20 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 00:48:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506303973960462.5485725873385; Sun, 24 Sep 2017 18:46:13 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BA6B121E43B4C; Sun, 24 Sep 2017 18:42:56 -0700 (PDT) Received: from mail-wr0-x22d.google.com (mail-wr0-x22d.google.com [IPv6:2a00:1450:400c:c0c::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 875A420945B97 for ; Sun, 24 Sep 2017 18:42:55 -0700 (PDT) Received: by mail-wr0-x22d.google.com with SMTP id m18so5213552wrm.2 for ; Sun, 24 Sep 2017 18:46:06 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f16sm809520lfe.66.2017.09.24.18.46.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Sep 2017 18:46:04 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c0c::22d; helo=mail-wr0-x22d.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0MAN6YwS410x5Uda5bJHvW5m5TU3HXk+AGpdMd6Fhkw=; b=zhF1jkYUPmsrNnQhj7GtHHBesqHavj9324IC9FBD51p76H1OZDU+1RCu7MtaFIhJxV kp4rLTYvURlDJHN0VgAmZhHvAIrgnk3LDLZB2aG6XEYgzFTfxYL+LtsbIQK0qRJgRPpN 5Gnwd3BwPKtDbCZrysmCeeNI1saV4LgVQCSiLXt9JPklkjt3gsqG6W/22sCDD2YoOLdm QCORoJNEP2EmuLdFadSqhRDmuJZJqngppXV8EWOf4pVdgA1zz7s6w3oGAim5aLMekq3o A/bTdNoQYop7670LDu0K03Iym5aIZ4On02mXSQUwz1MmdssqcAKOL8yTONb1aPo1jPRf CUBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0MAN6YwS410x5Uda5bJHvW5m5TU3HXk+AGpdMd6Fhkw=; b=E/fD18d93ItoNY2fPTX+qVpDILjyqYCAehoZA8Rr4PMFJN9cs6xKfzfWwPRUHrTkDK 3wBpPBJrkTiWBAup9YrjiAFZCqPVs+jSa+oB+MDR9RbT3MQqDhN68DgDNLCdXc4fP+Pw 3Z3rxM42FJRT5MlD1CG6+ECMtecCTXvNOUu3GxEn7yEI7WMXg3WhUtS8pyqMBPlqoT9R znL9267GuVh20oeSzMUBf/TFg+DgUanPC/VlfqKXCgzgcLByI8qBR9agUEFthFdP79U+ sZQLd3PlIYJLLSQaEopd877lTXnaq3+G7nUFZXE3JcSbI7QTegQcNrRabEOry5Nh5v+n ZoZw== X-Gm-Message-State: AHPjjUjoEi+2F5oYkcDPlCfIsVOGD8aHszQ4S3aEpDH92u059BM/X0db w1G6kTSYcwoHBftNWslOqDAnakwm9R8= X-Google-Smtp-Source: AOwi7QBYenrMY6O4ppM076esXWJUUZM/ingvEAKdZubodEjxLOpeh6Quf5v3QwoE09XBKwl0iWRu/Q== X-Received: by 10.25.129.196 with SMTP id c187mr1727821lfd.107.1506303964736; Sun, 24 Sep 2017 18:46:04 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 25 Sep 2017 03:51:52 +0200 Message-Id: <1506304319-8620-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506304319-8620-1-git-send-email-mw@semihalf.com> References: <1506304319-8620-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 03/10] Marvell/Drivers: MvSpiDxe: Fix write bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, Joe Zhou , ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Joe Zhou This patch prevents possible NULL pointer dereference during SPI transfers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Joe Zhou Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index 0c6b624..29e1379 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -226,9 +226,8 @@ MvSpiTransfer ( // Wait for memory ready for (Iterator =3D 0; Iterator < SPI_TIMEOUT; Iterator++) { if (MmioRead32 (SpiRegBase + SPI_INT_CAUSE_REG)) { - *DataInPtr =3D MmioRead32 (SpiRegBase + SPI_DATA_IN_REG); - if (DataInPtr !=3D NULL) { + *DataInPtr =3D MmioRead32 (SpiRegBase + SPI_DATA_IN_REG); DataInPtr++; } if (DataOutPtr !=3D NULL) { --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 00:48:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150630397856226.476682966091857; Sun, 24 Sep 2017 18:46:18 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 051D521E43B49; Sun, 24 Sep 2017 18:43:01 -0700 (PDT) Received: from mail-wr0-x235.google.com (mail-wr0-x235.google.com [IPv6:2a00:1450:400c:c0c::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B7CCA20945B97 for ; Sun, 24 Sep 2017 18:42:56 -0700 (PDT) Received: by mail-wr0-x235.google.com with SMTP id o42so5214207wrb.3 for ; Sun, 24 Sep 2017 18:46:07 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f16sm809520lfe.66.2017.09.24.18.46.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Sep 2017 18:46:05 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c0c::235; helo=mail-wr0-x235.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6ez1chFyWGPdQHjnS9+SHPS9EYc5nWsONZk4QGL9Tfc=; b=WypGc4Ybb7g6CmP3DIXN0kqnvQynw0GDJ5up6tOnwAgMlxwO5ErvJUT9KFJUR+PqGJ NsKBjmF1ez1gv0466o9cbXyECpyh9gU67HkrtYqD+HxSvWSvQ4xrnvyzmr2r2cYWKSwC mwhpt+3yFEn6wrAPArOxgarQjP8UAyN/s9RPIOACWkfNV0PCZ24piMeD+WcaCrPlW1fC q1gq8BMJhNmlsbpGoMIlgQsK3yn0peGXa5un7oTLYF2n6QqGN/cnUuJbuBhzGv+zcSZb OqSj8E3IB8Iq4u+2Ku53JRWEZnonJCK/achHtQjj1uqIrz2dyAa7qV/+LWiAYZ6QnwZW N7Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6ez1chFyWGPdQHjnS9+SHPS9EYc5nWsONZk4QGL9Tfc=; b=D3QLhXafT4BoT1AIRUoLmb4r+phG9gq/++SrNUBdqBDpPm3KA/ONGZu3HMeQE4xopi qMZtmrevgPV8bqB7ZqpU9v+/U9FYgn4UTmvEFatZDOwTA4lvQ7J1ujGc03SJnfDF07jt nl7akXX/YHbcRRqOY4a7vzIe5v46jZhddn21fSwbBiFwSuDiJd9cKP0X1gllGnzX6MDw QWXx+aSPBeGWUvHo+mO2x/CizVjldRs+iH+/VOClj2f10yEN9jI9lzQc242FCp2qaJ2A xs/9OIikY7a+hZsJDKonCWRwiS/KQLNLLEdNSMUcZ7hRUpzg2P2v+TDGTHNtsCKHYTgd vLXw== X-Gm-Message-State: AHPjjUiNA8TiHLOSvzKTaZckdwGaYPzuvBMB6vZH/z3LkNN1BFIfayYn k/7iOa5PtygFAX7yNpnOF956useKzQo= X-Google-Smtp-Source: AOwi7QCX1qTfiuJ1PPyDndWQFIBbJLSnlSamLzYMDruEf3qg4v5MQT1arQ5so4KnHTjVmm4vNo0aiA== X-Received: by 10.25.142.215 with SMTP id a84mr1952447lfl.25.1506303965944; Sun, 24 Sep 2017 18:46:05 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 25 Sep 2017 03:51:53 +0200 Message-Id: <1506304319-8620-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506304319-8620-1-git-send-email-mw@semihalf.com> References: <1506304319-8620-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 04/10] Marvell/Applications/SpiTool: Enable configurable CS and SCLK mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Until now transfer SCLK mode and CS were fixed, when using shell 'sf' command. This patch enables their configuration. Update porting guide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 6 +++++- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf | 2 ++ Platform/Marvell/Marvell.dec | 2 ++ Silicon/Marvell/Documentation/PortingGuide.txt | 11 ++++++----- 4 files changed, 15 insertions(+), 6 deletions(-) diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index 184e3d7..b6dc54f 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -218,6 +218,7 @@ EFI_STATUS Status; CONST CHAR16 *LengthStr =3D NULL, *FileStr =3D NULL; BOOLEAN AddrFlag =3D FALSE, LengthFlag =3D TRUE, FileFlag = =3D FALSE; UINT8 Flag =3D 0, CheckFlag =3D 0; + UINT8 Mode, Cs; =20 Status =3D gBS->LocateProtocol ( &gMarvellSpiFlashProtocolGuid, @@ -283,8 +284,11 @@ EFI_STATUS Status; } } =20 + Mode =3D PcdGet32 (PcdSpiFlashMode); + Cs =3D PcdGet32 (PcdSpiFlashCs); + // Setup new spi device - Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, 0, 0); + Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, Cs, Mode); if (Slave =3D=3D NULL) { Print(L"sf: Cannot allocate SPI device!\n"); return SHELL_ABORTED; diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf b/Platfo= rm/Marvell/Applications/SpiTool/SpiFlashCmd.inf index 41b7b7c..887b9a5 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf @@ -65,7 +65,9 @@ FileHandleLib =20 [Pcd] + gMarvellTokenSpaceGuid.PcdSpiFlashCs gMarvellTokenSpaceGuid.PcdSpiFlashId + gMarvellTokenSpaceGuid.PcdSpiFlashMode =20 [Protocols] gMarvellSpiFlashProtocolGuid diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 4e2dd6d..869e376 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -128,6 +128,8 @@ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 + gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 =20 #ComPhy gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x0 }|VOID*|0x30000098 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index aa53329..2be658e 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -285,11 +285,6 @@ Following PCDs are available for configuration of spi = driver: - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency (Max SCLK line frequency (in Hz) (max transfer frequency) ) =20 - - gMarvellTokenSpaceGuid.PcdSpiDefaultMode - (default SCLK mode (see SPI_MODE enum in file - edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h) ) - - SpiFlash configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Folowing PCDs for spi flash driver configuration must be set properly: @@ -309,6 +304,12 @@ Folowing PCDs for spi flash driver configuration must = be set properly: - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd (Spi flash polling flag) =20 + - gMarvellTokenSpaceGuid.PcdSpiFlashMode + (Default SCLK mode (see SPI_MODE enum in file + edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h)) + + - gMarvellTokenSpaceGuid.PcdSpiFlashCs + (Chip select used for communication with the Flash) =20 MPP configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 00:48:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150630398011419.62500696698055; Sun, 24 Sep 2017 18:46:20 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 431DA21E43B51; Sun, 24 Sep 2017 18:43:01 -0700 (PDT) Received: from mail-wr0-x22f.google.com (mail-wr0-x22f.google.com [IPv6:2a00:1450:400c:c0c::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0509421E43B4E for ; Sun, 24 Sep 2017 18:42:57 -0700 (PDT) Received: by mail-wr0-x22f.google.com with SMTP id g29so5209571wrg.11 for ; Sun, 24 Sep 2017 18:46:08 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f16sm809520lfe.66.2017.09.24.18.46.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Sep 2017 18:46:06 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c0c::22f; helo=mail-wr0-x22f.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/aEgiFkLLj0NiOZnHLobS4uSgwGOIrMUeyWXC0yExr0=; b=BsSkFYFP7eWMAzooTGT1AP28++G6cTQ/Prz1Z+eysVVz8rGiqVEQEiGGise6VUrFuL vHMVb5TVapIO8YMtNUhKJte71U6TXJgkfuZfqEAQ+1hWK4iHSOaHTQ1MhNjklMPJ8wfM QHBIYOZ6vouS9mUH3BSBobEu+ok0g5++G38kfcR8bLVTSd6ZVL/lu/ENF520Z4/hTZBx hGagyi/JLvCfLhdx0A3JsZROtzVboRE7VACg9iTjeYNo4NcB28E/ehhE88VFOU5kWgrF 0s6LYv2Du3QUQk6rxaiZZbBW4mKncX99pjRfecFROWNbVHirMWLLR1JwDXeiUhzwtvyw Hbtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/aEgiFkLLj0NiOZnHLobS4uSgwGOIrMUeyWXC0yExr0=; b=G6YeCefQf2lCE3vEnrs8IlQSXbiz5PUTYX9fdx1bDApJBNSGcpRMCqeJMw3r+OCRy6 H0nYKcVgihnSLW7RG9yk+aTpyDeECLoHzP3Q83hWH3d9hQiZcs29xfSSaotcE4D+VWek RoruHIgBGC4ZGFFn+2eCTAf2en0LZzJkw/0ATBU4geqqb5FJrIALzUD2TH089bK5eZ9J 07g9GUOC9OYuzmiNxPInsrOkySyjrJwp8SkkVZIXfy8CRrfktqCfDhFSRRRIHGA2OaKr uI1j42rNVULuQVxeAx6vzUC0KaiqTNLu1gfQPMP0ATUrdO67N+JlTz/k0Zwo89BkHmSQ ySvA== X-Gm-Message-State: AHPjjUjt4NEwx97W6Sv2q16Cdalw0C3+uc4PMLnLneq9i+PyV4FuMkiA BnVw6x4UZx6Z9X1IZpHA8TIUZSARq2w= X-Google-Smtp-Source: AOwi7QASt1oNHS/5OjoTbK6ts+WfZsR76UJRizzCDOFJ3aRbShFfeZkiDEEDuTd+yF37v957BQBiPw== X-Received: by 10.46.69.5 with SMTP id s5mr966433lja.26.1506303967258; Sun, 24 Sep 2017 18:46:07 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 25 Sep 2017 03:51:54 +0200 Message-Id: <1506304319-8620-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506304319-8620-1-git-send-email-mw@semihalf.com> References: <1506304319-8620-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 05/10] Platform/Marvell/Armada70x0: set CS and SCLK Mode for SPI flash X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch makes use of recently added SPI configuration PCDs and sets CS with SCLK mode on Armada 7040 DB. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada70x0.dsc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index caf3840..467dfa3 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -95,6 +95,8 @@ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|65536 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|256 gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18 + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 =20 #ComPhy gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 00:48:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506303983432124.64313969693819; Sun, 24 Sep 2017 18:46:23 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7DDAE21E43B5C; Sun, 24 Sep 2017 18:43:01 -0700 (PDT) Received: from mail-wr0-x22d.google.com (mail-wr0-x22d.google.com [IPv6:2a00:1450:400c:c0c::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 35E9921E43B4E for ; Sun, 24 Sep 2017 18:42:59 -0700 (PDT) Received: by mail-wr0-x22d.google.com with SMTP id 108so5233157wra.5 for ; Sun, 24 Sep 2017 18:46:10 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f16sm809520lfe.66.2017.09.24.18.46.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Sep 2017 18:46:07 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c0c::22d; helo=mail-wr0-x22d.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uqJpvjrOOSyYcnagMvKkRjOCmPLv71Ofcl2VUYLrWM8=; b=LaozhhWKtp4XbJcObqrOncJhHwTaRU1rKIa2uwJHHl0rwT31rWhitt7gU+p1tFQQnf eJYA4fP0rM7tZVmBn3WUubKFC43Pt06y5eyODTqvRNN8utE6um6u9mxoBhiLDzc2t64G 9NDA97Q0ZZG553e8Epi8v966tslPuyOCNnwbTlPE4mqSA6rYC6Wwbe7mLPPzph/6eMPF zbzTpOMixR1kCKyZjmBORPrauw3B9yczO+uiTYns29lmuiXg69YDvBd7anD7XYrn+QGp Og5z4lef2CmhykX0OLxJdr7zN+6bRZXps76sqFwcsq3XwOuK7PTV8nqTJc7XMcW+Gef3 tDeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uqJpvjrOOSyYcnagMvKkRjOCmPLv71Ofcl2VUYLrWM8=; b=ODqpVD7MuuuCOWmVUKxX9LknqcfSOeS8vFGWGWAE0lMuynqeqTlFqDbvPnMhaOEt4R t3eHotH56cruO4DZBWtbw2np7xSwU/j2Fc/Lh2NKhg2ZT6fkoYK4Ep0abh4E6SEHmn8Y GJ6MoDrcGrR981BeS8xzaU7mwaVqvRZFuMZ4lpq58/nBGMlH997S0b7yyBWQmAFW3WvQ Y2ok5gRQC9byhMjQWhQJXW4WG4WkdbHxH636oRLl/h8EVYQfNny46lAeuRoeZQcZHm1h PjZSd4SWecmXadmxeBGmhm9Jkh2PVxyewrwsmYRcvWu73sy8t51+XDi4V9PXM3f2vzr6 ezzg== X-Gm-Message-State: AHPjjUghD8XeQdSrhnvXAbEZDEFqldbAjAa/sj/oHH6+H/74mrpUwK3k t1Oql8ZS2vEU2EPPDHRFrvfOOeDMJM4= X-Google-Smtp-Source: AOwi7QBORHJdY/B1Ls5UFq0tLgrf685KrWTOEns14jan30RxZvXR14olS2FaVPTPBcTZtI3qRHO3+A== X-Received: by 10.46.15.26 with SMTP id 26mr178312ljp.69.1506303968519; Sun, 24 Sep 2017 18:46:08 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 25 Sep 2017 03:51:55 +0200 Message-Id: <1506304319-8620-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506304319-8620-1-git-send-email-mw@semihalf.com> References: <1506304319-8620-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 06/10] Marvell/Applications/SpiTool: Fix bug in error test X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Fix a misplaced closing parenthesis. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index b6dc54f..e6e1007 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -378,7 +378,7 @@ EFI_STATUS Status; FilePath =3D (CHAR16 *) FileStr; Status =3D ShellIsFile (FilePath); // When read file into flash, file doesn't have to exist - if (EFI_ERROR(Status && !(Flag & READ_FILE))) { + if (EFI_ERROR (Status) && !(Flag & READ_FILE)) { Print (L"sf: Wrong FilePath parameter!\n"); return SHELL_ABORTED; } --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 00:48:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506303992089991.2645238519179; Sun, 24 Sep 2017 18:46:32 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B561821E74920; Sun, 24 Sep 2017 18:43:05 -0700 (PDT) Received: from mail-wr0-x22b.google.com (mail-wr0-x22b.google.com [IPv6:2a00:1450:400c:c0c::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7B8A121E43B49 for ; Sun, 24 Sep 2017 18:43:00 -0700 (PDT) Received: by mail-wr0-x22b.google.com with SMTP id c23so5205618wrg.9 for ; Sun, 24 Sep 2017 18:46:11 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f16sm809520lfe.66.2017.09.24.18.46.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Sep 2017 18:46:09 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c0c::22b; helo=mail-wr0-x22b.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1//VL5mBW5jm8XEx4gE9ikWDIwbkP/HicJgHS5QOD4k=; b=a/JlMr/xdPYRULR9Xq3Bcdb9I+lKrUeiQbyAeH3fy+PF35FdJAX3n7w4E5h3pQN1de 9T3fg1kRseohbLOhNvyujEKQLa4d1noDeLbU2q/q6HLoHZkxcCcy0LY5vjU3gTbqrxs3 BDhhSmdn/qc2yceNcj14133eqUuknbMr8HAZucwNwGyiq3hl9R3Q5WO9E1z2at6j4EB+ VumleqKnamXmHw2sO769wKyhvGN+OHZryYwS4CEl2mn4QtfAEwxlK4Uwz2nzvcPJMX/o QWS7eQaHhcMPmUrtIDf1XT02AUlRPmCdUrXuv2fWDWe7WxMn/zGpgnHEDzU96gzeY0qM KBcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1//VL5mBW5jm8XEx4gE9ikWDIwbkP/HicJgHS5QOD4k=; b=FPAkRQO8b6RyAxuOK2TxETJIA0n+DBWoSXEsTTj+szfKLi07GLMU8RePc10I0Rka2b +qD4fJsBZ6T7maeGlzs1fOwWEirYr+8zL63lrSADQMnJiITdJloid9o341DyvW/UN5yL AjSf/tPQE7RX/o1zX0IdaiKGh5cz110DqlMamB1qVGG4V8pNAHbxKhBRYBY0wRiOxgg+ lGijE26gLdHbEMmuoUvBdFcDTYCqrBDWI433QQvGHjQPgrACVoaTQCui182gvYhbf4QF AoDLPw9cTD6DWRqemaBs/Xw24nz8c2cCQU7OvtafkH/n3c9vOXwcXqrKWj4Rs6pih+pa WxJw== X-Gm-Message-State: AHPjjUhVovbzuUk+cbW1bVIoa6AySOy2hS4etgzmPoqNNhuO+dThs9Dm A6/zgkM3sjWYvkX7Apsi28LzE7ub4mw= X-Google-Smtp-Source: AOwi7QD+pm4iIUeX1mnHdiizJ/VQ5CjuVozDTB8saLsGqXDAkqdnQeC/qqyzyEO8MZEe4FXLzvqefQ== X-Received: by 10.46.77.9 with SMTP id a9mr2065788ljb.127.1506303969817; Sun, 24 Sep 2017 18:46:09 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 25 Sep 2017 03:51:56 +0200 Message-Id: <1506304319-8620-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506304319-8620-1-git-send-email-mw@semihalf.com> References: <1506304319-8620-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 07/10] Marvell/Applications/FirmwareUpdate: Fix 32-bit issues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Fix casting and related issues to make this code build for 32-bit ARM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c b/Platf= orm/Marvell/Applications/FirmwareUpdate/FUpdate.c index edb6986..664411a 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c @@ -165,7 +165,7 @@ PrepareFirmwareImage ( IN LIST_ENTRY *CheckPackage, IN OUT SHELL_FILE_HANDLE *FileHandle, IN OUT UINTN **FileBuffer, - IN OUT UINTN *FileSize + IN OUT UINT64 *FileSize ) { CONST CHAR16 *FileStr; @@ -203,7 +203,7 @@ PrepareFirmwareImage ( // Read Image header into buffer Buffer =3D AllocateZeroPool (*FileSize); =20 - Status =3D FileHandleRead (*FileHandle, FileSize, Buffer); + Status =3D FileHandleRead (*FileHandle, (UINTN *)FileSize, Buffer); if (EFI_ERROR (Status)) { Print (L"%s: Cannot read Image file header\n", CMD_NAME_STRING); ShellCloseFile (FileHandle); @@ -256,7 +256,7 @@ ShellCommandRunFUpdate ( { IN SHELL_FILE_HANDLE FileHandle; SPI_DEVICE *Slave; - UINTN FileSize; + UINT64 FileSize; UINTN *FileBuffer =3D NULL; CHAR16 *ProblemParam; LIST_ENTRY *CheckPackage; --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 00:48:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150630399516091.31121365256911; Sun, 24 Sep 2017 18:46:35 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 009F721E87996; Sun, 24 Sep 2017 18:43:06 -0700 (PDT) Received: from mail-wr0-x22f.google.com (mail-wr0-x22f.google.com [IPv6:2a00:1450:400c:c0c::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B017321E43B6C for ; Sun, 24 Sep 2017 18:43:01 -0700 (PDT) Received: by mail-wr0-x22f.google.com with SMTP id 108so5233236wra.5 for ; Sun, 24 Sep 2017 18:46:12 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f16sm809520lfe.66.2017.09.24.18.46.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Sep 2017 18:46:10 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c0c::22f; helo=mail-wr0-x22f.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Mjk40BeVBzX2BPKw5ESD5R/yILPybKxgifQJsGCHarg=; b=kPk0zMbhzXjtViHwNbeOPmooJNzvDrFt9e/4pnxMruljABkAa5pWnZn1oLmmAvBBde 41YcaDEj3JLplB1cOWrCC6j9hpTwOmbh7U5YGBYG8zs/YBT+fE9hlHfC2V6+irZ7eFdk glh/h+dQE75R3ell3lze88CIKsrRF57pPR+nRrT8o37SDqHg7dOz87iDdwjVnI6EBXbU 7Lqv9IHMD0uTPC8LjgBmki64N3+ai/bXsahacgwIQqbdi+3D/QH68130aS2yQSv1Bai9 T7L9iNPjnGq3ht+7i2FAMeoGwjSj4cfwSrO9UcWpEYvenuDK5BjcSf4Vt+DnfEjTCGLY 4qLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Mjk40BeVBzX2BPKw5ESD5R/yILPybKxgifQJsGCHarg=; b=eQO2eQCW3buchzXENZ6FKblNGIqaNbOQ7tRsfvOfBJ9wQK6t8fgrJ9C3946vPxQn0O xPdPn2vS9bCIcSXcgK3IyX16rz4nLel8YC3FcjMF58IomVstHhOD8Itp17k1xgZainlz dra+1iSxDZnhWO+uMzRqa9QoAjxKtx1exHnZq/fNYwo4TtSz5Ei0uTNF8bukdfgnxb7/ fa3+es4FxvfHF/TejMA3LoVeqxhw6RMglyjpdOrW7p3jPROOOWe+2PNmnCPmDlydOEYV +IZUbxVzZlkAdP0E+rwUlBcJcwrftd2AuH9MPc3xTnkjHTJ1JqT5W1peSQ/WtznMicrB Lo9g== X-Gm-Message-State: AHPjjUjupvdv//okuZwPJ/zt+s0gsNsWYVMowEVfkIXR6qNkbvjACz9x 7LPjv3Ntu5BABvjWraGMUbkJ/BOhcBw= X-Google-Smtp-Source: AOwi7QCKDx9LjAHMEkbVP7jyhx5B8u3XwqjkKjVR40Vc86XyrpBtWGcZ0i2z7XACOEwRYtLYeb76ow== X-Received: by 10.46.71.193 with SMTP id u184mr2240078lja.166.1506303970967; Sun, 24 Sep 2017 18:46:10 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 25 Sep 2017 03:51:57 +0200 Message-Id: <1506304319-8620-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506304319-8620-1-git-send-email-mw@semihalf.com> References: <1506304319-8620-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 08/10] Marvell/Applications/SpiTool: Fix 32-bit issues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Fix casting and related issues to make this code build for 32-bit ARM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index e6e1007..9321f6b 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -211,7 +211,8 @@ EFI_STATUS Status; LIST_ENTRY *CheckPackage; EFI_PHYSICAL_ADDRESS Address =3D 0, Offset =3D 0; SHELL_FILE_HANDLE FileHandle =3D NULL; - UINTN ByteCount, FileSize, I; + UINTN ByteCount, I; + UINT64 FileSize; UINT8 *Buffer =3D NULL, *FileBuffer =3D NULL; CHAR16 *ProblemParam, *FilePath; CONST CHAR16 *AddressStr =3D NULL, *OffsetStr =3D NULL; @@ -418,7 +419,7 @@ EFI_STATUS Status; } } =20 - Buffer =3D (UINT8 *) Address; + Buffer =3D (UINT8 *)(UINTN)Address; if (FileFlag) { Buffer =3D FileBuffer; } --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 00:48:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506303999103850.9114215357924; Sun, 24 Sep 2017 18:46:39 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3E3DA21E945F7; Sun, 24 Sep 2017 18:43:06 -0700 (PDT) Received: from mail-wr0-x230.google.com (mail-wr0-x230.google.com [IPv6:2a00:1450:400c:c0c::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1FB3F20945B97 for ; Sun, 24 Sep 2017 18:43:03 -0700 (PDT) Received: by mail-wr0-x230.google.com with SMTP id k20so5227989wre.4 for ; Sun, 24 Sep 2017 18:46:13 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f16sm809520lfe.66.2017.09.24.18.46.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Sep 2017 18:46:11 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c0c::230; helo=mail-wr0-x230.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QCwW3rZSM1dOWY8FlOHhCZjhxrDch85DTk1L0U6ZBis=; b=zTrIyIY5BAKsL6Qu+kffoptoFaN4ipG5QqBksahl53AE0m4N4OyTVRJtJc8NqpXDlz BGnQgYzr/qC0Fao6NfgbTBz+kFeeQQkUnN30h+C1H1W/uaqtqMuHw9XicniKF0HokuQT ZkP5R9VUpV6ugbec21byGySdotEbcUOJFiKuHeZE6pNiLKty7XqVGEW/F7A4bohwJyhf RaUm20yoftwV4ieHRJvcMNEFkRnWiTbbz3xXW/zh/vcEyl7hujrIwUePF71Rrb/1zdWo 6fBkMZKYZrCC34LfCODmJBpIugu2cYEBLq+BH27CYRKaZLCnIoXU+WXz3ZzgDu3hBF8G zkHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QCwW3rZSM1dOWY8FlOHhCZjhxrDch85DTk1L0U6ZBis=; b=fKKlZrX9Xd8IL6Ms1UN+R1VYncZxKXAnwmt465juiiujucGerb9rYnPbcWKgnmP8+F hPTfK0ETNen5MErFJpgcvEpNCIp0Q6YgI2vlYq+z63AZmYLXyM1QbMbtAXAXSjufiF39 RYhfYMd1Q4b+8agebot8sRHPMEi6LuAbNCoUYsURfT4k/DCLXFHXOTbLRoPJFh2r/ni1 UdxvYIir6siMDnDnFqVUUzyNqj1VM2+ZpIOsWnPdVdO6IlwNtHqiNX7JrYO992wOPY7i 4udBZOyXwdJI5R3QzAk7lxw0KxjU6tQIV8u6r4RiPJfixRQKF+dFQ0XYGDMuxXA63I0R 4XtQ== X-Gm-Message-State: AHPjjUgPIsRWkrxnJNvDYQKcS4zrIHdCJoerPvYX7Abz5R+EvIbJqB2A sHuN5EjAoRRlblVnYIKHw6RrejP/ap8= X-Google-Smtp-Source: AOwi7QCBhkjXTztsnDfQnKy0lSXqoaG9zndqIAfHuAGCmxcbvZe4OyPaqk0Oxk6ADvGm0Sz+Q6Eing== X-Received: by 10.46.21.81 with SMTP id 17mr2269756ljv.68.1506303972213; Sun, 24 Sep 2017 18:46:12 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 25 Sep 2017 03:51:58 +0200 Message-Id: <1506304319-8620-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506304319-8620-1-git-send-email-mw@semihalf.com> References: <1506304319-8620-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 09/10] Marvell/Drivers: MvSpiFlash: Fix usage of erase size parameter X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Although, hitherto support allowed for using configurable EraseSize, the erase command was fixed to CMD_ERASE_64K. Also it was assumed that EraseSize equals SectorSize, which is not true for some flash devices. Fix both issues by adding new PCD (gMarvellTokenSpaceGuid.PcdSpiFlashPageSize) and using this parameter properly in MvSpiFlashUpdate routine instead of the EraseSize. Also erase command is adjusted to the settings. Update PortingGuide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 26 +++++++++++++++--= --- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 6 +++++ Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf | 1 + Platform/Marvell/Marvell.dec | 1 + Silicon/Marvell/Documentation/PortingGuide.txt | 3 +++ 5 files changed, 31 insertions(+), 6 deletions(-) diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index 9a04493..c411296 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -191,7 +191,21 @@ MvSpiFlashErase ( return EFI_DEVICE_ERROR; } =20 - Cmd[0] =3D CMD_ERASE_64K; + switch (EraseSize) { + case SIZE_4K: + Cmd[0] =3D CMD_ERASE_4K; + break; + case SIZE_32K: + Cmd[0] =3D CMD_ERASE_32K; + break; + case SIZE_64K: + Cmd[0] =3D CMD_ERASE_64K; + break; + default: + DEBUG ((DEBUG_ERROR, "MvSpiFlash: Invalid EraseSize parameter\n")); + return EFI_INVALID_PARAMETER; + } + while (Length) { EraseAddr =3D Offset; =20 @@ -353,14 +367,14 @@ MvSpiFlashUpdate ( ) { EFI_STATUS Status; - UINT64 EraseSize, ToUpdate, Scale =3D 1; + UINT64 SectorSize, ToUpdate, Scale =3D 1; UINT8 *TmpBuf, *End; =20 - EraseSize =3D PcdGet64 (PcdSpiFlashEraseSize); + SectorSize =3D PcdGet64 (PcdSpiFlashSectorSize); =20 End =3D Buf + ByteCount; =20 - TmpBuf =3D (UINT8 *)AllocateZeroPool (EraseSize); + TmpBuf =3D (UINT8 *)AllocateZeroPool (SectorSize); if (TmpBuf =3D=3D NULL) { DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); return EFI_OUT_OF_RESOURCES; @@ -370,9 +384,9 @@ MvSpiFlashUpdate ( Scale =3D (End - Buf) / 100; =20 for (; Buf < End; Buf +=3D ToUpdate, Offset +=3D ToUpdate) { - ToUpdate =3D MIN((UINT64)(End - Buf), EraseSize); + ToUpdate =3D MIN((UINT64)(End - Buf), SectorSize); Print (L" \rUpdating, %d%%", 100 - (End - Buf) / Scale); - Status =3D MvSpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buf, TmpBuf= , EraseSize); + Status =3D MvSpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buf, TmpBuf= , SectorSize); =20 if (EFI_ERROR (Status)) { DEBUG((DEBUG_ERROR, "SpiFlash: Error while updating\n")); diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.h index 3889643..49cce43 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h @@ -57,6 +57,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_READ_ARRAY_FAST 0x0b #define CMD_PAGE_PROGRAM 0x02 #define CMD_BANK_WRITE 0xc5 +#define CMD_ERASE_4K 0x20 +#define CMD_ERASE_32K 0x52 #define CMD_ERASE_64K 0xd8 #define CMD_4B_ADDR_ENABLE 0xb7 =20 @@ -66,6 +68,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #define SPI_TRANSFER_BEGIN 0x01 // Assert CS before transfer #define SPI_TRANSFER_END 0x02 // Deassert CS after transfe= rs =20 +#define SIZE_4K 4096 +#define SIZE_32K 32768 +#define SIZE_64K 65536 + #define SPI_FLASH_16MB_BOUN 0x1000000 =20 typedef enum { diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf b/Platform= /Marvell/Drivers/Spi/Devices/MvSpiFlash.inf index d035d47..4519b02 100644 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf @@ -58,6 +58,7 @@ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize gMarvellTokenSpaceGuid.PcdSpiFlashPageSize gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd + gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize =20 [Protocols] gMarvellSpiMasterProtocolGuid diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 869e376..fc00f1a 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -127,6 +127,7 @@ gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|0|UINT32|0x3000053 gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 + gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize|65536|UINT64|0x3000059 gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 2be658e..83ebe9d 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -298,6 +298,9 @@ Folowing PCDs for spi flash driver configuration must b= e set properly: - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize (Size of SPI flash page) =20 + - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize + (Size of SPI flash sector, 65536 bytes by default) + - gMarvellTokenSpaceGuid.PcdSpiFlashId (Id of SPI flash) =20 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 00:48:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506304001460837.4719958241435; Sun, 24 Sep 2017 18:46:41 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7B2AC21E945FA; Sun, 24 Sep 2017 18:43:06 -0700 (PDT) Received: from mail-wr0-x231.google.com (mail-wr0-x231.google.com [IPv6:2a00:1450:400c:c0c::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2725A20945B97 for ; Sun, 24 Sep 2017 18:43:04 -0700 (PDT) Received: by mail-wr0-x231.google.com with SMTP id a43so5221785wrc.0 for ; Sun, 24 Sep 2017 18:46:15 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f16sm809520lfe.66.2017.09.24.18.46.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Sep 2017 18:46:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c0c::231; helo=mail-wr0-x231.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K8mX5xoTyZpcFnGe6cpXlZfOu/Ml+lzDUmNcqKweFLc=; b=WVNtUAKzeRkWXn/YbVwimTcANbvDPWv13Jl5/cmJxelRMC3GUXb6PrykmdkZAeoHl/ jC47GnBtGnbGz/aTFF3L6T0/xAey4I8HMh7ZlCvF/Nu4dXBmNKHG9n9hxuPkYpJFKdVC kO/pnELWxMvsytgwmap4alzufDQEdt/2M+/H1F6AQSPolmupGZxmpoqlIOAbH2cIf0eA tIffops6O7J+v0PYLnBTASuWfstG88bQpcPmYPWiMA8pCOg2TE52HgJGeSKrdTx8rRUZ Cf6S+cTiWT/oCGxfsTkorVVhcvlRiMZmXeU7zHUkA91b9YoPeHVR2sRUVtKpN3bCQfp3 ZFkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K8mX5xoTyZpcFnGe6cpXlZfOu/Ml+lzDUmNcqKweFLc=; b=UCnRQ0F9UCf7rbGs8DFz/2mn/L/3/1ixC/YbephwVHskelQBPBKyh2NAAKnQSwjahu FKn+GRgSzU5ebo14MSH++hkbDCyNDyuTDHsTFE/QTIiC+LOMCVvv7A0Cz72FXk0Y9k5V suI2ghCKs+Pr5u70dtnm/6yXgD2g2Mm3JaaWbCjPClAtdT7TvEqgEZxD54vZCumrTezl t8vbcztzhDN4xsJUF8UF28WdQMbiNJWCzXOYNXvhsufa4NgjA7LiisN6fJhUm37XPgmp JuYIS7T/iaJjTI4OxvUo+qTQ9d6mSHE3GZN+2cgoL81RW8P9wk5AP9rh8eahLAahjNQI ammg== X-Gm-Message-State: AHPjjUiQLszU7i6BX0pL5rlb6OlRWCXv/loDo9rPJ9fKfUa4EZ4Z3mOP 0XC9FsDGrdpUKMVmouICqnIx41AlYzk= X-Google-Smtp-Source: AOwi7QBRSzRvHXneaG9HJ0jsvZ9gN2NGIWJL1250tzAmUeyZhwLv6MS4Fib38K/bqPHPl8b50usTig== X-Received: by 10.46.21.84 with SMTP id 20mr1764095ljv.168.1506303973481; Sun, 24 Sep 2017 18:46:13 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 25 Sep 2017 03:51:59 +0200 Message-Id: <1506304319-8620-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506304319-8620-1-git-send-email-mw@semihalf.com> References: <1506304319-8620-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 10/10] Marvell/Drivers: MvSpiFlash: Minor style fix X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch correct style of two variables to the camel-case version. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index c411296..c7e0221 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -104,13 +104,13 @@ MvSpiFlashWriteCommon ( UINT8 CmdStatus =3D CMD_READ_STATUS; UINT8 State; UINT32 Counter =3D 0xFFFFF; - UINT8 poll_bit =3D STATUS_REG_POLL_WIP; - UINT8 check_status =3D 0x0; + UINT8 PollBit =3D STATUS_REG_POLL_WIP; + UINT8 CheckStatus =3D 0x0; =20 CmdStatus =3D (UINT8)PcdGet32 (PcdSpiFlashPollCmd); if (CmdStatus =3D=3D CMD_FLAG_STATUS) { - poll_bit =3D STATUS_REG_POLL_PEC; - check_status =3D poll_bit; + PollBit =3D STATUS_REG_POLL_PEC; + CheckStatus =3D PollBit; } =20 // Send command @@ -127,7 +127,7 @@ MvSpiFlashWriteCommon ( SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 1, NULL, &State, 0); Counter--; - if ((State & poll_bit) =3D=3D check_status) + if ((State & PollBit) =3D=3D CheckStatus) break; } while (Counter > 0); if (Counter =3D=3D 0) { --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel