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charset="utf-8" Introduce a couple of FixedPCDs to replace Intel-specific macros. The new PCDs will allow SMM support on AMD-based x86 systems. 1) PcdCpuSmmSmramSaveStateMapOffset - SMRAM Save State Map Offset. 2) PcdCpuSmmPSDOffset - Processor SMM Descriptor Offset in SMRAM. Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/UefiCpuPkg.dec | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 3bd8740..c92c56e 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -2,6 +2,7 @@ # This Package provides UEFI compatible CPU modules and libraries. # # Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials are licensed and made availa= ble under # the terms and conditions of the BSD License which accompanies this distr= ibution. @@ -204,6 +205,14 @@ # @Prompt If CPU features will be initialized during S3 resume. gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0= 000001D =20 + ## Specifies the Offset of SMRAM Save State Map from SMBASE. + # @Prompt SMRAM Save State Map Offset. + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSmramSaveStateMapOffset|0xFC00|UINT16= |0x32132113 + + ## Specifies the PROCESSOR SMM DESCRIPTOR Offset in SMRAM. + # @Prompt SMRAM PSD Offset. + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmPSDOffset|0xFB00|UINT16|0x32132114 + [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## Specifies max supported number of Logical Processors. # @Prompt Configure max supported number of Logical Processors --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:59:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Jeff Fan , Liming Gao Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce a couple of FixedPCDs to replace Intel-specific macros. The new PCDs will allow SMM support on AMD-based x86 systems. 1) PcdCpuSmmSmramSaveStateMapOffset - SMRAM Save State Map Offset. 2) PcdCpuSmmPSDOffset - Processor SMM Descriptor Offset in SMRAM. Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index 099792e..bf237f7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -147,6 +147,10 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock ## CONS= UMES =20 +[FixedPcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSmramSaveStateMapOffset ## CONS= UMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmPSDOffset ## CONS= UMES + [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize ## SOME= TIMES_CONSUMES --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:59:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Jeff Fan , Liming Gao Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce a couple of FixedPCDs to replace Intel-specific macros. The new PCDs will allow SMM support on AMD-based x86 systems. 1) PcdCpuSmmSmramSaveStateMapOffset - SMRAM Save State Map Offset. 2) PcdCpuSmmPSDOffset - Processor SMM Descriptor Offset in SMRAM. Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 5 +++++ UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/U= efiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 77908b0..1be2671 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -2,6 +2,8 @@ # The CPU specific programming for PiSmmCpuDxeSmm module. # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -36,5 +38,8 @@ MemoryAllocationLib DebugLib =20 +[FixedPcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSmramSaveStateMapOffset ## CONS= UMES + [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf index db8dcdc..b1937de 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf @@ -3,6 +3,8 @@ # is included. # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -78,6 +80,10 @@ gEfiAcpi20TableGuid ## SOMETIMES_CONSUMES ## System= Table gEfiAcpi10TableGuid ## SOMETIMES_CONSUMES ## System= Table =20 +[FixedPcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSmramSaveStateMapOffset ## CONS= UMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmPSDOffset ## CONS= UMES + [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize ## SOME= TIMES_CONSUMES --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:59:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507068536859281.8386662530164; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcel Apfelbaum , Laszlo Ersek , Ruiyu Ni , Jordan Justen Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce a FixedPCD to replace an Intel-specific macro. PcdCpuSmmSmramSaveStateMapOffset - SMRAM Save State Map Offset. The new PCD allows for SMM support on AMD-based x86 systems, and it is declared here just to resolve the macro that will be replaced by the shared Library/SmmCpuFeaturesLib.h file. Cc: Laszlo Ersek Cc: Jordan Justen Cc: Marcel Apfelbaum Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/Ovmf= Pkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 31edf3a..f6c2c4c 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -2,6 +2,8 @@ # The CPU specific programming for PiSmmCpuDxeSmm module. # # Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -36,3 +38,6 @@ PcdLib DebugLib SmmServicesTableLib + +[FixedPcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSmramSaveStateMapOffset ## CONS= UMES --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:59:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507068540422780.267377588798; Tue, 3 Oct 2017 15:09:00 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7F71521F2AF8F; Tue, 3 Oct 2017 15:05:30 -0700 (PDT) Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02on0077.outbound.protection.outlook.com [104.47.37.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A657D2095E537 for ; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce a FixedPCD to replace an Intel-specific macro. PcdCpuSmmSmramSaveStateMapOffset - SMRAM Save State Map Offset. The new PCD allows for SMM support on AMD-based x86 systems, and it is declared here just to resolve the macro that will be replaced by the shared Library/SmmCpuFeaturesLib.h file. Cc: Michael D Kinney Cc: Kelly Steele Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 5 += ++++ 1 file changed, 5 insertions(+) diff --git a/QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/SmmCpu= FeaturesLib.inf b/QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/S= mmCpuFeaturesLib.inf index 267ac84..ef9c113 100644 --- a/QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/SmmCpuFeature= sLib.inf +++ b/QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/SmmCpuFeature= sLib.inf @@ -2,6 +2,8 @@ # The CPU specific programming for PiSmmCpuDxeSmm module. # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -34,3 +36,6 @@ DebugLib QNCAccessLib =20 +[FixedPcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSmramSaveStateMapOffset ## CONS= UMES + --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:59:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507068543568816.366976530566; Tue, 3 Oct 2017 15:09:03 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C074621E78215; Tue, 3 Oct 2017 15:05:32 -0700 (PDT) Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02on0076.outbound.protection.outlook.com [104.47.37.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2AD1321E78215 for ; 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charset="utf-8" Add a FixedPCD to replace an Intel-specific hard-coded macro. The new PCD allows SMM support on AMD-based x86 systems. PcdCpuSmmSmramSaveStateMapOffset - SMRAM Save State Map Offset. Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/Include/Register/SmramSaveStateMap.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Include/Register/SmramSaveStateMap.h b/UefiCpuPkg/I= nclude/Register/SmramSaveStateMap.h index a7c7562..2167f33 100644 --- a/UefiCpuPkg/Include/Register/SmramSaveStateMap.h +++ b/UefiCpuPkg/Include/Register/SmramSaveStateMap.h @@ -8,6 +8,8 @@ Intel(R) 64 and IA-32 Architectures Software Developer's Ma= nual Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs =20 Copyright (c) 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -34,7 +36,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. /// /// Offset of SMRAM Save State Map from SMBASE /// -#define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00 +#define SMRAM_SAVE_STATE_MAP_OFFSET (FixedPcdGet16 (PcdCpuSmmSmramSaveSta= teMapOffset)) =20 #pragma pack (1) =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:59:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507068546996311.16608373820327; Tue, 3 Oct 2017 15:09:06 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1255321F303FF; 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charset="utf-8" Add a FixedPCD to replace an Intel-specific hard-coded macro. The new PCD allows SMM support on AMD-based x86 systems. PcdCpuSmmPSDOffset - Processor SMM Descriptor Offset in SMRAM. Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 1cf85c1..06b9767 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -360,7 +360,7 @@ typedef struct { UINT32 MsrIndex; } MP_MSR_LOCK; =20 -#define SMM_PSD_OFFSET 0xfb00 +#define SMM_PSD_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) =20 /// /// All global semaphores' pointer --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:59:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507068550869862.4027783012427; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Jeff Fan , Liming Gao Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a FixedPCD to replace an Intel-specific hard-coded macro. The new PCD allows SMM support on AMD-based x86 systems. PcdCpuSmmPSDOffset - Processor SMM Descriptor Offset in SMRAM. Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 4 +++- 6 files changed, 18 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCp= uDxeSmm/Ia32/SmiEntry.S index 3243a91..25af6e7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -35,7 +37,7 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 +.equ DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset)) .equ DSC_GDTPTR, 0x30 .equ DSC_GDTSIZ, 0x38 .equ DSC_CS, 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmm= CpuDxeSmm/Ia32/SmiEntry.asm index 8296f36..f526778 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,7 +31,7 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h +DSC_OFFSET EQU (FixedPcdGet16 (PcdCpuSmmPSDOffset)) DSC_GDTPTR EQU 30h DSC_GDTSIZ EQU 38h DSC_CS EQU 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index 4d2383f..9092dcc 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -25,7 +27,7 @@ ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 +%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) %define DSC_GDTPTR 0x30 %define DSC_GDTSIZ 0x38 %define DSC_CS 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpu= DxeSmm/X64/SmiEntry.S index 600d862..ebea477 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -34,7 +36,7 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 +.equ DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset)) .equ DSC_GDTPTR, 0x30 .equ DSC_GDTSIZ, 0x38 .equ DSC_CS, 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/SmiEntry.asm index c74f82a..ff46838 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -39,7 +41,7 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h +DSC_OFFSET EQU (FixedPcdGet16 (PcdCpuSmmPSDOffset)) DSC_GDTPTR EQU 30h DSC_GDTSIZ EQU 38h DSC_CS EQU 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index c3c094f..f55da9b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,7 +31,7 @@ ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 +%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) %define DSC_GDTPTR 0x30 %define DSC_GDTSIZ 0x38 %define DSC_CS 14 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:59:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507068554479673.6227616433209; Tue, 3 Oct 2017 15:09:14 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8DDCB21F322B4; Tue, 3 Oct 2017 15:05:36 -0700 (PDT) Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02on0071.outbound.protection.outlook.com [104.47.37.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8620121F303F9 for ; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Jeff Fan , Liming Gao Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a FixedPCD to replace an Intel-specific hard-coded macro. The new PCD allows SMM support on AMD-based x86 systems. PcdCpuSmmPSDOffset - Processor SMM Descriptor Offset in SMRAM. Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 4 +++- UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 4 +++- UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 4 +++- UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 4 +++- UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 4 +++- UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 4 +++- 6 files changed, 18 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S b/UefiCpu= Pkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S index 4c0f8c8..d3c291e 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -36,7 +38,7 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # # Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 +.equ DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset)) .equ DSC_GDTPTR, 0x48 .equ DSC_GDTSIZ, 0x50 .equ DSC_CS, 0x14 diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm b/UefiC= puPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm index 91dc1eb..096f353 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,7 +31,7 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h +DSC_OFFSET EQU (FixedPcdGet16 (PcdCpuSmmPSDOffset)) DSC_GDTPTR EQU 48h DSC_GDTSIZ EQU 50h DSC_CS EQU 14h diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm b/Uefi= CpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm index 00c0f067..696af46 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -25,7 +27,7 @@ ; ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 +%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) %define DSC_GDTPTR 0x48 %define DSC_GDTSIZ 0x50 %define DSC_CS 0x14 diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S b/UefiCpuP= kg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S index 1f9f91c..de0f71b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -35,7 +37,7 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # # Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 +.equ DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset)) .equ DSC_GDTPTR, 0x48 .equ DSC_GDTSIZ, 0x50 .equ DSC_CS, 0x14 diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm b/UefiCp= uPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm index ad51e07..3e4e080 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -40,7 +42,7 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h +DSC_OFFSET EQU (FixedPcdGet16 (PcdCpuSmmPSDOffset)) DSC_GDTPTR EQU 48h DSC_GDTSIZ EQU 50h DSC_CS EQU 14h diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm b/UefiC= puPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm index bcac643..8425499 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,7 +31,7 @@ ; ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 +%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) %define DSC_GDTPTR 0x48 %define DSC_GDTSIZ 0x50 %define DSC_CS 0x14 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel