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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jordan Justen , Liming Gao , Jiewen Yao , Michael D Kinney Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a FixedPCD to replace an Intel-specific hard-coded macro. The new PCD allows SMM support on AMD-based x86 systems. PcdCpuSmmPSDOffset - Processor SMM Descriptor Offset in SMRAM. Cc: Jiewen Yao Cc: Ruiyu Ni Cc: Michael D Kinney Cc: Jordan Justen Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 4 +++- 6 files changed, 18 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCp= uDxeSmm/Ia32/SmiEntry.S index 3243a91..25af6e7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -35,7 +37,7 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 +.equ DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset)) .equ DSC_GDTPTR, 0x30 .equ DSC_GDTSIZ, 0x38 .equ DSC_CS, 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmm= CpuDxeSmm/Ia32/SmiEntry.asm index 8296f36..f526778 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,7 +31,7 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h +DSC_OFFSET EQU (FixedPcdGet16 (PcdCpuSmmPSDOffset)) DSC_GDTPTR EQU 30h DSC_GDTSIZ EQU 38h DSC_CS EQU 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index 4d2383f..9092dcc 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -25,7 +27,7 @@ ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 +%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) %define DSC_GDTPTR 0x30 %define DSC_GDTSIZ 0x38 %define DSC_CS 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpu= DxeSmm/X64/SmiEntry.S index 600d862..ebea477 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -34,7 +36,7 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 +.equ DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset)) .equ DSC_GDTPTR, 0x30 .equ DSC_GDTSIZ, 0x38 .equ DSC_CS, 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/SmiEntry.asm index c74f82a..ff46838 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -39,7 +41,7 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h +DSC_OFFSET EQU (FixedPcdGet16 (PcdCpuSmmPSDOffset)) DSC_GDTPTR EQU 30h DSC_GDTSIZ EQU 38h DSC_CS EQU 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index c3c094f..f55da9b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,7 +31,7 @@ ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 +%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) %define DSC_GDTPTR 0x30 %define DSC_GDTSIZ 0x38 %define DSC_CS 14 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel