From nobody Thu Dec 26 01:22:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507143376533425.61835881863556; Wed, 4 Oct 2017 11:56:16 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E64E620945BC4; Wed, 4 Oct 2017 11:52:50 -0700 (PDT) Received: from NAM03-CO1-obe.outbound.protection.outlook.com (mail-co1nam03on0060.outbound.protection.outlook.com [104.47.40.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A6E1520945BC4 for ; Wed, 4 Oct 2017 11:52:49 -0700 (PDT) Received: from leduran-Precision-WorkStation-T5400.amd.com (165.204.77.1) by CY4PR12MB1237.namprd12.prod.outlook.com (10.168.167.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.77.7; Wed, 4 Oct 2017 18:56:08 +0000 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=helo; client-ip=104.47.40.60; helo=nam03-co1-obe.outbound.protection.outlook.com; envelope-from=leo.duran@amd.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=x8UcfJP35nBVmlD1Vk7waL3cU103mtuWx/5F9ZGSjKI=; b=tRJv6ShB80m0KWP5su8tzkJOn5mJ/n9/ccyRaR4nujTSwsUNN0u10tBIHM31MaMvdg1G/T51ocJ6txZBDywHWQo8LfRYVpJRcn1KPiNZaMGURqpvnzhdGVzcVL8IbY4heuQ9bYU/+egepJK5L4O4UAaQcoCx97vEThJUNleUS70= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=leo.duran@amd.com; From: Leo Duran To: edk2-devel@lists.01.org Date: Wed, 4 Oct 2017 13:55:55 -0500 Message-Id: <1507143357-18181-4-git-send-email-leo.duran@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507143357-18181-1-git-send-email-leo.duran@amd.com> References: <1507143357-18181-1-git-send-email-leo.duran@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BN6PR03CA0062.namprd03.prod.outlook.com (10.173.137.24) To CY4PR12MB1237.namprd12.prod.outlook.com (10.168.167.12) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 95bd7e09-0a6f-414e-6cbf-08d50b599354 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(2017030254152)(48565401081)(2017052603199)(201703131423075)(201703031133081)(201702281549075); SRVR:CY4PR12MB1237; X-Microsoft-Exchange-Diagnostics: 1; CY4PR12MB1237; 3:jUHWaNf3ll0IGRZYGFomnw4btMVmZkNDVoxPtBD+/mhuxX3Ym6jX5rPECIZ1JxX/dvyH4xUvfbYCpXWsME1x46fWgqGU+Dij52CbHmeMUofcB7M6RCHEepyOysz+cFTjY+eRhpRBCMm3GEy5bO1Ls6jKictx5LIE0aomCiz3+zWOwLVL4CMO2lOoesBNJ/6Aw8sVL/t1DyS7dG3nf9fKpiqvIEKwWAAaqL4OFc7IV/Td+YPD2ci0ZJyAhWY9gMLl; 25:7JT/Bi8yd94t9UXPco1K5qAJtykTOi7j5TsZZnKCps826dV4JsFyFkyTaRFT7I0MOg4REz+/Xd//WsgodljeKz7Lt5T2MvlGxPq+xGkf+TX5iixVnG8mOJDNF/O1Z0VQR6ZpEUv5R/Jl/3rYb8p39bmQOI0pPsrHlN8amOkc5sz8udwsys5UzlSoR2/3JE15B5ZF5JXYgTYmbQj4/9tKI4crx6i/Rl1KyCxO+5ZA4NSlNUxGGfAY4WaDUbjfJqd7pa3QmLxiIts49vCP3UQ3GhTRjXxRqXubLdYnr9d/ebIKVFHLwAfcHY0UJLHsEOKe6/zYLImNk348f1JB2HfTWA==; 31:1Jz6isXLTN9CuOe9ZXIcUh8tFlcq0dr/f/TDHKpZF8A39Vl5rCTgn7oP5ch+9kDPgx81c7kQQf8o71O4tJNpCaiSh3+FQ0eV/MOBJdJMHwIBdSyrd2XDzWAad/EjJ0JTWxBu9xlwS8b8e7f7Z+M/QIctk+DnoqCBSimluwGYOHnfrj0e28n0+EHgjMGy9dba6FWwFlgOyNioqWc+y1OhR+hPEJUBCGCW6ZTpgFtqmUM= X-MS-TrafficTypeDiagnostic: CY4PR12MB1237: X-Microsoft-Exchange-Diagnostics: 1; CY4PR12MB1237; 20:/cDmnnI5q+6twfmGoJ1sh4uDHz7HghVS4oBFlg94P5xlZzTDE5jFVD1caE4a0ivO8tzh2aInaxrMmjCT9y+v7Z6t/ryrW8osSnYQveRekg6tyV2R+IYpcuPTZxTHs7YFAfjQUiI+tZc4nxrbCjwn7PZsj2DrEY+yszusOJ8Is/mw2saQC/Hv1ts3ORXPrp+6lv+EAhJHwipHtsGOt18g6C3B4wRntyFX9XeENEG7jafIJMH8SAOsIU5rpkdisNOkRaftP7Sd0NflBR5Dlh5Z5ZBxTGtOj/phajeLvPepmiEoEwcFnPKYBdhyy2hhxD9fmjmPV8NwkyrOBWNFMh/tI8CpIYc9s0SAH/7ttdelwbJw0WOnw7UX8ZE3ECLtDDgDcdPgctGFJYvaG7B3LOzzEuSnr5Qd+CTgcb1ohyUGDP8MtLX0nWCL02xwmdEzzvifoGMWd6XlL4GEfj5uLQTnnXivxuToUpfDsFnXnGkrgRFz0k61tKo3AZONqyQTvE7k; 4:VRt832FBbbSl6s5ua8XAd5L7RvjiTc3ZLeYuomI8XUrrSTWE4NZ+hiSFO5pXRLhkxc76DxOwo+Q1y3IaYqxqS2xzultXDp+10PyMePRlGr4Ud7izKc8nl5qHSOxt0wKK7UxivKD2hvtS7vMe4JXOgVBHomyE1ElJNj36SpchKsJqnzIIPTlkhJnKPFBEc7y9PbyhPnJMpZ3JgcG/We75/xz9KJaFyOiJN0FND9lSyzbQMC4VQTCF8+9cW52CBc3ijBnIA/4EB6BrYMsvbZ3OBZGEK6s2LjiAEELYP3O8/wKq9FeP6P60OcdAYRPR+NU10w7gZjJxT56YgcDCpaqBZt7yUGjl9DtS6XeONTbVKy4= X-Exchange-Antispam-Report-Test: UriScan:(767451399110)(788757137089)(228905959029699); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(8121501046)(5005006)(100000703101)(100105400095)(93006095)(93001095)(10201501046)(3002001)(6055026)(6041248)(20161123560025)(20161123562025)(20161123555025)(20161123564025)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:CY4PR12MB1237; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:CY4PR12MB1237; X-Forefront-PRVS: 0450A714CB X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(6029001)(6009001)(376002)(39860400002)(346002)(199003)(189002)(478600001)(66066001)(16586007)(316002)(97736004)(6486002)(47776003)(50226002)(305945005)(36756003)(6666003)(2906002)(54906003)(189998001)(86362001)(53936002)(5003940100001)(101416001)(68736007)(50986999)(2950100002)(81166006)(50466002)(8676002)(48376002)(8936002)(53416004)(25786009)(2361001)(2351001)(33646002)(5660300001)(7736002)(6916009)(106356001)(6116002)(105586002)(3846002)(81156014)(4326008)(76176999)(16526018)(19627235001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR12MB1237; H:leduran-Precision-WorkStation-T5400.amd.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; CY4PR12MB1237; 23:DDCtP7TBByQgq7/jy0YxIiHUwlsAuBipo0eHcf2Fc?= =?us-ascii?Q?TJ5PuzYMkQyuqbROhNaj98zyAps5kSsxoud/hwoM0xHMn/im9JQgbxdFLsqR?= =?us-ascii?Q?0yL15cGZjCcnOWYZZmw+LqwNbim/KtTxG57K3Xx1YtVxqO639KAFn6JMVN17?= =?us-ascii?Q?rtvo0vZXSodoow/Qc82RWHzIbIT7PiZ1kb+RVzkcOJWCFZy6VcW4GQIW2ayS?= =?us-ascii?Q?85HMPEc4DjmUkicbVDSLx16v0dPe40JUwVHvmQqp+JjPB3qY+f33Bxb3/jLf?= =?us-ascii?Q?hI6F5BAkzA3PwUh4jO+QrP2OrJ9t7k/fcP4tMAktCXsF5WN1prQKCCkgkg8I?= =?us-ascii?Q?tw1dA+scLC3z8Zzr0dNwzahXu9EpZBTqOU1jT+5CkhYZ8pISUhsdoo+6Mt+Y?= =?us-ascii?Q?6eDl0Oe23ywV+/KqQyl6yf/SVwgAZOXeAHnhuFrAXBk3oG6TXti6xQPIbaRq?= =?us-ascii?Q?i14XGElbyhokthEhx7SwC8oM6xCe5AoSqpq7HwmjODKxE9CNJS8dcg9sO5eA?= =?us-ascii?Q?mcNLHHyo/PLrneJNpwpanfjYR7zdXTRzBpoxAVbAoIBpRlLU5nOlYSc+hEmd?= =?us-ascii?Q?MwyYiZidZ1bc/+NJ/+C1kSJ0BuEcjG0uYXwk/rEif5rj1vSE/ffh3HHs88ch?= =?us-ascii?Q?HyLzPhFTpb0WovYt03XBYNMviQSlYRj1ii84dtsv/8AXMOOHVjmvGd4KZDNc?= =?us-ascii?Q?ZTTrNuusZnsyg/dCAlataiTZhL4h5tM87Qk7dCZ7dypcKx5H6KaM2J8veEdK?= =?us-ascii?Q?jQD0Bohai3qCc6AZHGGI0SZNB1+TpQbh/Ui1ayh7ww4mmx9AglNyQVv57EDN?= =?us-ascii?Q?i/efwbv3nS/xIFXMNWWoTYgTUqCwLw+JrywKQGxSO0/tItpV0SHzetuUj9KK?= =?us-ascii?Q?/nkdJoj7Pm+aXrJEeHFBP4PIeO++i0bC9zDUSIQ1ehld9Wo+6h90k5QAcLME?= =?us-ascii?Q?ebYWV+nYPSFxGzFfZRYM9i6aTN+qHRDGwffQFzbBJLPXU3GqijxJgk1XLp+l?= =?us-ascii?Q?RyI0DvNfihvPSGeSJwsALaVsk+NDju7Inl/SxeTV+gGw8GK2mwbJxsPrIWhF?= =?us-ascii?Q?xFEwCcaL9i7y9f99dpqEnmjBhPx0fmylL8JjesX4c31QM7vAS2AWPcLBtsRs?= =?us-ascii?Q?TJSloiWH4CxwTMRUPtB1tyh54AJ8whk2hUO3mYoiYR9XIgfq8e0/3XYaZINI?= =?us-ascii?Q?gf+UN5IPN0ppkA=3D?= X-Microsoft-Exchange-Diagnostics: 1; CY4PR12MB1237; 6:hlBxxicdcrPk/Np5sIlqK5pqF3xqwVVBwjNd3ifH+qHZdJP6OVbFBPztqrAINbcvP0jSJ1m0BkpxB4WPNl3lgL/e9nlJqYNGhwdGe5TV6Vu6yV6T/581YGwxP4JlOc1q+6kyfNyFx37IZlincp205UCM65kZGogmkN5T6uCHefI6WCM5p0iZ4BxuHaT3yBHAJYkPOUaPpfAXpfbR9BYEYdDugMVCaCukojbcNnJrofIWFy2r1V8ABHnMb9SwVx91wWJe22dwx0bq3/IULymzD3IPBdAnHa351FFqiA5B8tH4MHqxBrAk4SX0Am+wEcAPEdPPEhapnzE1FaVFIRV5vw==; 5:wKXVgPc63IAhwSFPjudatAb1DkCf9CMGj/u9yqy0QSI9IqvI2vsJyITYA8LTho6e+6V8mcRxngirVtI23stfWDmASNG659TQUXhfWY/HZStXbf3Iw7IhjyPIU4P6SG/6N++x1diABABRMAm4IkvjvA==; 24:xF3Uc5GIcIvYM8PwTSZY0K9NKrHUb/eC2+XJ/9ee0AFTiaXcxybT6chTNGKk4yG6aOZhcOxk15RjPGZnclawYg7joQwaBrtY/n8/iMOv0TE=; 7:0pS+cJZq4/C0vP8C4fC272KZcuXjiNuKvRRRIJtVySpCNAl0wslUMqcH8dwH7jvKbbCR0ZRfgY3JjNdLoOHQYGrIaS9DlkgRQrpxv5ZXskMtGNV2Ss7ONoFkrK0GiamkoMpZfNuJtjxUFuuFpXUwqh11hvnzynm8PZCKsc/NuK8QmNjYlAVl7ZghGHJ4jw9tVnKB7/P49XaZKw3izX+b7YFgbocMOs+8xgfnMTAbzWo= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; CY4PR12MB1237; 20:kN+GWnU1gqgExFmGGtNinHCXzi2lnzGr7Gz5db8ZoIDuuo/q6699lnAtnER1pdGRvRltzP5w5Mq4VKedzIfhhNjQ1WaxpetC4q4RWZjx6xH7lJjAHzjKKKWz5ngtCaby2uUZssreHPaY8w06ZFF+l0+n4pGCN58JVvg9QEYhJQKG8wkzVHr9uWC+/tKXxaTzkG0jtcXG78toZ9GVVUSlK4nw4VK5QSdT2NpvqNtFwN3QKI2WCUdjnd1vOZY6HD8c X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2017 18:56:08.5977 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1237 Subject: [edk2] [PATCH v3 3/5] UefiCpuPkg/PiSmmCpuDxeSmm: Use FixedPCDs to enhance SMM support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jordan Justen , Liming Gao , Jiewen Yao , Michael D Kinney Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Consume a couple of FixedPCDs to replace Intel-specific macros. The new PCDs will allow SMM support on AMD-based x86 systems. 1) PcdCpuSmmSmramSaveStateMapOffset - SMRAM Save State Map Offset. 2) PcdCpuSmmPSDOffset - Processor SMM Descriptor Offset in SMRAM. Cc: Jiewen Yao Cc: Ruiyu Ni Cc: Michael D Kinney Cc: Jordan Justen Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 10 +++++----- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 2 -- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 4 +++- 12 files changed, 35 insertions(+), 17 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c b/UefiCpuPkg/PiSmmC= puDxeSmm/Ia32/Semaphore.c index 02a866b..cc2624e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c @@ -3,6 +3,8 @@ Semaphore mechanism to indicate to the BSP that an AP has e= xited SMM after SMBASE relocation. =20 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -38,7 +40,7 @@ SemaphoreHook ( =20 mRebasedFlag =3D RebasedFlag; =20 - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_= SAVE_STATE_MAP_OFFSET); + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + FixedP= cdGet16 (PcdCpuSmmSmramSaveStateMapOffset)); mSmmRelocationOriginalAddress =3D (UINTN)HookReturnFromSmm ( CpuIndex, CpuState, diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCp= uDxeSmm/Ia32/SmiEntry.S index 3243a91..25af6e7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -35,7 +37,7 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 +.equ DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset)) .equ DSC_GDTPTR, 0x30 .equ DSC_GDTSIZ, 0x38 .equ DSC_CS, 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmm= CpuDxeSmm/Ia32/SmiEntry.asm index 8296f36..f526778 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,7 +31,7 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h +DSC_OFFSET EQU (FixedPcdGet16 (PcdCpuSmmPSDOffset)) DSC_GDTPTR EQU 30h DSC_GDTSIZ EQU 38h DSC_CS EQU 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index 4d2383f..9092dcc 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -25,7 +27,7 @@ ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 +%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) %define DSC_GDTPTR 0x30 %define DSC_GDTSIZ 0x38 %define DSC_CS 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 282d2e6..b2a941e 100755 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -407,7 +407,7 @@ SmmRelocateBases ( gcSmiInitGdtr.Limit =3D gcSmiGdtr.Limit; =20 U8Ptr =3D (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET); - CpuStatePtr =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMR= AM_SAVE_STATE_MAP_OFFSET); + CpuStatePtr =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + Fix= edPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset)); =20 // // Backup original contents at address 0x38000 @@ -707,12 +707,12 @@ PiCpuSmmEntry ( =20 // // Compute tile size of buffer required to hold the CPU SMRAM Save State= Map, extra CPU - // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI= entry point. + // specific context start starts at SMBASE + PcdCpuSmmPSDOffset, and the= SMI entry point. // This size is rounded up to nearest power of 2. // TileCodeSize =3D GetSmiHandlerSize (); TileCodeSize =3D ALIGN_VALUE(TileCodeSize, SIZE_4KB); - TileDataSize =3D (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof= (SMRAM_SAVE_STATE_MAP); + TileDataSize =3D (FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset) - Fix= edPcdGet16 (PcdCpuSmmPSDOffset)) + sizeof (SMRAM_SAVE_STATE_MAP); TileDataSize =3D ALIGN_VALUE(TileDataSize, SIZE_4KB); TileSize =3D TileDataSize + TileCodeSize - 1; TileSize =3D 2 * GetPowerOfTwo32 ((UINT32)TileSize); @@ -725,7 +725,7 @@ PiCpuSmmEntry ( // the SMI Handler size must be reduced or the size of the extra CPU spe= cific // context must be reduced. // - ASSERT (TileSize <=3D (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_= STATE_MAP) - SMM_HANDLER_OFFSET)); + ASSERT (TileSize <=3D (FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset) = + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET)); =20 // // Allocate buffer for all of the tiles. @@ -783,7 +783,7 @@ PiCpuSmmEntry ( for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { mCpuHotPlugData.SmBase[Index] =3D (UINTN)Buffer + Index * Til= eSize - SMM_HANDLER_OFFSET; gSmmCpuPrivate->CpuSaveStateSize[Index] =3D sizeof(SMRAM_SAVE_STATE_MA= P); - gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); + gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset)); gSmmCpuPrivate->Operation[Index] =3D SmmCpuNone; =20 if (Index < mNumberOfCpus) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 1cf85c1..31e4f53 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -360,8 +360,6 @@ typedef struct { UINT32 MsrIndex; } MP_MSR_LOCK; =20 -#define SMM_PSD_OFFSET 0xfb00 - /// /// All global semaphores' pointer /// diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 3ad5256..147b694 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -1,6 +1,8 @@ /** @file =20 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -703,7 +705,7 @@ PatchSmmSaveStateMap ( =20 TileCodeSize =3D GetSmiHandlerSize (); TileCodeSize =3D ALIGN_VALUE(TileCodeSize, SIZE_4KB); - TileDataSize =3D (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof= (SMRAM_SAVE_STATE_MAP); + TileDataSize =3D (FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset) - Fix= edPcdGet16 (PcdCpuSmmPSDOffset)) + sizeof (SMRAM_SAVE_STATE_MAP); TileDataSize =3D ALIGN_VALUE(TileDataSize, SIZE_4KB); TileSize =3D TileDataSize + TileCodeSize - 1; TileSize =3D 2 * GetPowerOfTwo32 ((UINT32)TileSize); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmC= puDxeSmm/SmramSaveState.c index 3188d43..d59b9a0 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -2,6 +2,8 @@ Provides services to access SMRAM Save State Map =20 Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -690,7 +692,7 @@ InstallSmiHandler ( // // Initialize PROCESSOR_SMM_DESCRIPTOR // - Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFF= SET); + Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + FixedPcdGet= 16 (PcdCpuSmmPSDOffset)); CopyMem (Psd, &gcPsd, sizeof (gcPsd)); Psd->SmmGdtPtr =3D (UINT64)GdtBase; Psd->SmmGdtSize =3D (UINT32)GdtSize; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c b/UefiCpuPkg/PiSmmCp= uDxeSmm/X64/Semaphore.c index 6dbcb08..e74bb69 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c @@ -3,6 +3,8 @@ Semaphore mechanism to indicate to the BSP that an AP has e= xited SMM after SMBASE relocation. =20 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -51,7 +53,7 @@ SemaphoreHook ( mRebasedFlag =3D RebasedFlag; mRebasedFlagAddr32 =3D (UINT32)(UINTN)mRebasedFlag; =20 - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_= SAVE_STATE_MAP_OFFSET); + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + FixedP= cdGet16 (PcdCpuSmmSmramSaveStateMapOffset)); mSmmRelocationOriginalAddress =3D HookReturnFromSmm ( CpuIndex, CpuState, diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpu= DxeSmm/X64/SmiEntry.S index 600d862..ebea477 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -34,7 +36,7 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 +.equ DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset)) .equ DSC_GDTPTR, 0x30 .equ DSC_GDTSIZ, 0x38 .equ DSC_CS, 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/SmiEntry.asm index c74f82a..ff46838 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -39,7 +41,7 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h +DSC_OFFSET EQU (FixedPcdGet16 (PcdCpuSmmPSDOffset)) DSC_GDTPTR EQU 30h DSC_GDTSIZ EQU 38h DSC_CS EQU 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index c3c094f..f55da9b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,7 +31,7 @@ ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 +%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) %define DSC_GDTPTR 0x30 %define DSC_GDTSIZ 0x38 %define DSC_CS 14 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel