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charset="utf-8" Consume a couple of FixedPCDs to replace Intel-specific macros. The new PCDs will allow SMM support on AMD-based x86 systems. 1) PcdCpuSmmSmramSaveStateMapOffset - SMRAM Save State Map Offset. 2) PcdCpuSmmPSDOffset - Processor SMM Descriptor Offset in SMRAM. Cc: Jiewen Yao Cc: Ruiyu Ni Cc: Michael D Kinney Cc: Jordan Justen Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 10 +++++----- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 2 -- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 4 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 4 +++- 12 files changed, 35 insertions(+), 17 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c b/UefiCpuPkg/PiSmmC= puDxeSmm/Ia32/Semaphore.c index 02a866b..cc2624e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c @@ -3,6 +3,8 @@ Semaphore mechanism to indicate to the BSP that an AP has e= xited SMM after SMBASE relocation. =20 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -38,7 +40,7 @@ SemaphoreHook ( =20 mRebasedFlag =3D RebasedFlag; =20 - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_= SAVE_STATE_MAP_OFFSET); + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + FixedP= cdGet16 (PcdCpuSmmSmramSaveStateMapOffset)); mSmmRelocationOriginalAddress =3D (UINTN)HookReturnFromSmm ( CpuIndex, CpuState, diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCp= uDxeSmm/Ia32/SmiEntry.S index 3243a91..25af6e7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -35,7 +37,7 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 +.equ DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset)) .equ DSC_GDTPTR, 0x30 .equ DSC_GDTSIZ, 0x38 .equ DSC_CS, 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmm= CpuDxeSmm/Ia32/SmiEntry.asm index 8296f36..f526778 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,7 +31,7 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h +DSC_OFFSET EQU (FixedPcdGet16 (PcdCpuSmmPSDOffset)) DSC_GDTPTR EQU 30h DSC_GDTSIZ EQU 38h DSC_CS EQU 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index 4d2383f..9092dcc 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -25,7 +27,7 @@ ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 +%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) %define DSC_GDTPTR 0x30 %define DSC_GDTSIZ 0x38 %define DSC_CS 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 282d2e6..b2a941e 100755 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -407,7 +407,7 @@ SmmRelocateBases ( gcSmiInitGdtr.Limit =3D gcSmiGdtr.Limit; =20 U8Ptr =3D (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET); - CpuStatePtr =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMR= AM_SAVE_STATE_MAP_OFFSET); + CpuStatePtr =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + Fix= edPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset)); =20 // // Backup original contents at address 0x38000 @@ -707,12 +707,12 @@ PiCpuSmmEntry ( =20 // // Compute tile size of buffer required to hold the CPU SMRAM Save State= Map, extra CPU - // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI= entry point. + // specific context start starts at SMBASE + PcdCpuSmmPSDOffset, and the= SMI entry point. // This size is rounded up to nearest power of 2. // TileCodeSize =3D GetSmiHandlerSize (); TileCodeSize =3D ALIGN_VALUE(TileCodeSize, SIZE_4KB); - TileDataSize =3D (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof= (SMRAM_SAVE_STATE_MAP); + TileDataSize =3D (FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset) - Fix= edPcdGet16 (PcdCpuSmmPSDOffset)) + sizeof (SMRAM_SAVE_STATE_MAP); TileDataSize =3D ALIGN_VALUE(TileDataSize, SIZE_4KB); TileSize =3D TileDataSize + TileCodeSize - 1; TileSize =3D 2 * GetPowerOfTwo32 ((UINT32)TileSize); @@ -725,7 +725,7 @@ PiCpuSmmEntry ( // the SMI Handler size must be reduced or the size of the extra CPU spe= cific // context must be reduced. // - ASSERT (TileSize <=3D (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_= STATE_MAP) - SMM_HANDLER_OFFSET)); + ASSERT (TileSize <=3D (FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset) = + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET)); =20 // // Allocate buffer for all of the tiles. @@ -783,7 +783,7 @@ PiCpuSmmEntry ( for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { mCpuHotPlugData.SmBase[Index] =3D (UINTN)Buffer + Index * Til= eSize - SMM_HANDLER_OFFSET; gSmmCpuPrivate->CpuSaveStateSize[Index] =3D sizeof(SMRAM_SAVE_STATE_MA= P); - gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); + gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset)); gSmmCpuPrivate->Operation[Index] =3D SmmCpuNone; =20 if (Index < mNumberOfCpus) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 1cf85c1..31e4f53 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -360,8 +360,6 @@ typedef struct { UINT32 MsrIndex; } MP_MSR_LOCK; =20 -#define SMM_PSD_OFFSET 0xfb00 - /// /// All global semaphores' pointer /// diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 3ad5256..147b694 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -1,6 +1,8 @@ /** @file =20 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -703,7 +705,7 @@ PatchSmmSaveStateMap ( =20 TileCodeSize =3D GetSmiHandlerSize (); TileCodeSize =3D ALIGN_VALUE(TileCodeSize, SIZE_4KB); - TileDataSize =3D (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof= (SMRAM_SAVE_STATE_MAP); + TileDataSize =3D (FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset) - Fix= edPcdGet16 (PcdCpuSmmPSDOffset)) + sizeof (SMRAM_SAVE_STATE_MAP); TileDataSize =3D ALIGN_VALUE(TileDataSize, SIZE_4KB); TileSize =3D TileDataSize + TileCodeSize - 1; TileSize =3D 2 * GetPowerOfTwo32 ((UINT32)TileSize); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmC= puDxeSmm/SmramSaveState.c index 3188d43..d59b9a0 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -2,6 +2,8 @@ Provides services to access SMRAM Save State Map =20 Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -690,7 +692,7 @@ InstallSmiHandler ( // // Initialize PROCESSOR_SMM_DESCRIPTOR // - Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFF= SET); + Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + FixedPcdGet= 16 (PcdCpuSmmPSDOffset)); CopyMem (Psd, &gcPsd, sizeof (gcPsd)); Psd->SmmGdtPtr =3D (UINT64)GdtBase; Psd->SmmGdtSize =3D (UINT32)GdtSize; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c b/UefiCpuPkg/PiSmmCp= uDxeSmm/X64/Semaphore.c index 6dbcb08..e74bb69 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c @@ -3,6 +3,8 @@ Semaphore mechanism to indicate to the BSP that an AP has e= xited SMM after SMBASE relocation. =20 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -51,7 +53,7 @@ SemaphoreHook ( mRebasedFlag =3D RebasedFlag; mRebasedFlagAddr32 =3D (UINT32)(UINTN)mRebasedFlag; =20 - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_= SAVE_STATE_MAP_OFFSET); + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + FixedP= cdGet16 (PcdCpuSmmSmramSaveStateMapOffset)); mSmmRelocationOriginalAddress =3D HookReturnFromSmm ( CpuIndex, CpuState, diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpu= DxeSmm/X64/SmiEntry.S index 600d862..ebea477 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -34,7 +36,7 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 +.equ DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset)) .equ DSC_GDTPTR, 0x30 .equ DSC_GDTSIZ, 0x38 .equ DSC_CS, 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/SmiEntry.asm index c74f82a..ff46838 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -39,7 +41,7 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h +DSC_OFFSET EQU (FixedPcdGet16 (PcdCpuSmmPSDOffset)) DSC_GDTPTR EQU 30h DSC_GDTSIZ EQU 38h DSC_CS EQU 14 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index c3c094f..f55da9b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,7 +31,7 @@ ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 +%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset)) %define DSC_GDTPTR 0x30 %define DSC_GDTSIZ 0x38 %define DSC_CS 14 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel