From nobody Wed Dec 25 13:53:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507459795845553.3245474807575; Sun, 8 Oct 2017 03:49:55 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8321C2095B073; Sun, 8 Oct 2017 03:46:28 -0700 (PDT) Received: from mail-lf0-x231.google.com (mail-lf0-x231.google.com [IPv6:2a00:1450:4010:c07::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 488DC2095B070 for ; Sun, 8 Oct 2017 03:46:27 -0700 (PDT) Received: by mail-lf0-x231.google.com with SMTP id b127so24477568lfe.9 for ; Sun, 08 Oct 2017 03:49:53 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id y17sm930370lfj.0.2017.10.08.03.49.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 08 Oct 2017 03:49:50 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::231; helo=mail-lf0-x231.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uGfBw4HminSdXGovi0RmbYEgBI1Oy/8SoyXNyfCkU44=; b=zlwDD1Yg35I4x67CQV9LGsVRUdjwt0R+v7heixwA04522nVbf9eg8ad348Gldfkf2O Hj1YLwfBqC83CJelMQAb8ognhv36yPyjMmfl9pokd2Bx27Tsao7iyn6ZfRHUl7ZSGOGT 0UWsfdvFOUdu2nV07jtFfIYsMtOLuz1rnAP26G94pjlSSBP9hZ8iUkIRcw3tOgIZStUt R+xwBmNDUukWz+aMXz1Cev7uNQZCWwIumTh95gRMgZtkJhv8K556t0aQVk4gkC16I3ep iPtUoQsYlUkupQk9ArduefXS+yu2hrRvijzpGEbA186St8FY7sJ0fuF50x5tFW7BiTd0 Ut3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uGfBw4HminSdXGovi0RmbYEgBI1Oy/8SoyXNyfCkU44=; b=YZUYmahIF2SUNS2F8hQIQzhU1wtts3o2V9DKNenEv375045w7J0q5q0Nvz0CGigID1 t5KJeoUKl2xFJPhoLblek0/Ng+iCIR7Z4Irx5muO7bcMThRkHXDbjoJ2RPIRguaTveuW qqCTHS7TbE+ghJxog/zW0hURB7tU36JSCblWt/U2b91CXT1GfOEniYDXfDvK2EK16GHx cQrECetE/q3CqFWXcFu1JaxsRBZ+jzbCnw58TFWToOLykAlvUJF++Plk4UqtjI8n5bA/ Kg8syhI4yuIpsm7mISKdRdcFsSD2rzcX2+oJDPz4EMIxFfq/SztEV9so8WURZgExR8nj rJIw== X-Gm-Message-State: AMCzsaW4uaU3851IfLCITVLj8OMnKrydwxDT6lGR3CfiDNT250bEafX/ E23TEMzI8k+KTiQtpXg4wz5d553ETw8= X-Google-Smtp-Source: AOwi7QBzrDCu1l8AG72/aExtDr+h5kLnRQmjizRYwhF1ZeWozp2dBwXwvesxQDXsQbhrjjQfgoOrcg== X-Received: by 10.25.143.156 with SMTP id s28mr2798698lfk.236.1507459790964; Sun, 08 Oct 2017 03:49:50 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 8 Oct 2017 12:56:48 +0200 Message-Id: <1507460212-10323-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507460212-10323-1-git-send-email-mw@semihalf.com> References: <1507460212-10323-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 1/5] Marvell/Library: ComPhyLib: Remove PCD string parsing X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Simplify obtaining lane data, using arrays with direct enum values, rather than strings. This is another step to completely remove ParsePcdLib. This patch replaces string-based description of ComPhy lanes on Armada 70x0 DB with the enum values of type and speed - for that purpose new [Defines] section was added to Armada.dsc.inc file in order to increase readability. PortingGuide is updated accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 44 +++++++++++++ Platform/Marvell/Armada/Armada70x0.dsc | 11 +++- Platform/Marvell/Library/ComPhyLib/ComPhyLib.c | 65 ++++--------------- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 25 +++----- Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 - Silicon/Marvell/Documentation/PortingGuide.txt | 67 +++++++++++++++----- 6 files changed, 124 insertions(+), 89 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 9549091..cd26506 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -479,3 +479,47 @@ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 } + +##########################################################################= ###### +# +# Defines - platform description macros +# +##########################################################################= ###### +[Defines] + # ComPhy speed + DEFINE CP_1_25G =3D 0x1 + DEFINE CP_1_5G =3D 0x2 + DEFINE CP_2_5G =3D 0x3 + DEFINE CP_3G =3D 0x4 + DEFINE CP_3_125G =3D 0x5 + DEFINE CP_5G =3D 0x6 + DEFINE CP_5_15625G =3D 0x7 + DEFINE CP_6G =3D 0x8 + DEFINE CP_6_25G =3D 0x9 + DEFINE CP_10_3125G =3D 0xA + + # ComPhy type + DEFINE CP_UNCONNECTED =3D 0x0 + DEFINE CP_PCIE0 =3D 0x1 + DEFINE CP_PCIE1 =3D 0x2 + DEFINE CP_PCIE2 =3D 0x3 + DEFINE CP_PCIE3 =3D 0x4 + DEFINE CP_SATA0 =3D 0x5 + DEFINE CP_SATA1 =3D 0x6 + DEFINE CP_SATA2 =3D 0x7 + DEFINE CP_SATA3 =3D 0x8 + DEFINE CP_SGMII0 =3D 0x9 + DEFINE CP_SGMII1 =3D 0xA + DEFINE CP_SGMII2 =3D 0xB + DEFINE CP_SGMII3 =3D 0xC + DEFINE CP_QSGMII =3D 0xD + DEFINE CP_USB3_HOST0 =3D 0xE + DEFINE CP_USB3_HOST1 =3D 0xF + DEFINE CP_USB3_DEVICE =3D 0x10 + DEFINE CP_XAUI0 =3D 0x11 + DEFINE CP_XAUI1 =3D 0x12 + DEFINE CP_XAUI2 =3D 0x13 + DEFINE CP_XAUI3 =3D 0x14 + DEFINE CP_RXAUI0 =3D 0x15 + DEFINE CP_RXAUI1 =3D 0x16 + DEFINE CP_SFI =3D 0x17 diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 467dfa3..dae9715 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -100,8 +100,15 @@ =20 #ComPhy gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1= ;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;= 5000" + # ComPhy0 + # 0: SGMII1 1.25 Gbps + # 1: USB3_HOST0 5 Gbps + # 2: SFI 10.31 Gbps + # 3: SATA1 5 Gbps + # 4: USB3_HOST1 5 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOS= T0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(C= P_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 #UtmiPhy gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.c index 3eb5d9f..bf21dca 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -113,47 +113,6 @@ RegSetSilent16( MmioWrite16 (Addr, RegData); } =20 -/* This function returns enum with SerDesType */ -UINT32 -ParseSerdesTypeString ( - CHAR16* String - ) -{ - UINT32 i; - - if (String =3D=3D NULL) - return COMPHY_TYPE_INVALID; - - for (i =3D 0; i < COMPHY_TYPE_MAX; i++) { - if (StrCmp (String, TypeStringTable[i]) =3D=3D 0) { - return i; - } - } - - /* PCD string doesn't match any supported SerDes Type */ - return COMPHY_TYPE_INVALID; -} - -/* This function converts SerDes speed in MHz to enum with SerDesSpeed */ -UINT32 -ParseSerdesSpeed ( - UINT32 Value - ) -{ - UINT32 i; - UINT32 ValueTable [] =3D {0, 1250, 1500, 2500, 3000, 3125, - 5000, 5156, 6000, 6250, 10310}; - - for (i =3D 0; i < COMPHY_SPEED_MAX; i++) { - if (Value =3D=3D ValueTable[i]) { - return i; - } - } - - /* PCD SerDes speed value doesn't match any supported SerDes speed */ - return COMPHY_SPEED_INVALID; -} - CHAR16 * GetTypeString ( UINT32 Type @@ -182,7 +141,8 @@ GetSpeedString ( =20 VOID ComPhyPrint ( - IN CHIP_COMPHY_CONFIG *PtrChipCfg + IN CHIP_COMPHY_CONFIG *PtrChipCfg, + IN UINT8 Index ) { UINT32 Lane; @@ -191,7 +151,7 @@ ComPhyPrint ( for (Lane =3D 0; Lane < PtrChipCfg->LanesCount; Lane++) { SpeedStr =3D GetSpeedString(PtrChipCfg->MapData[Lane].Speed); TypeStr =3D GetTypeString(PtrChipCfg->MapData[Lane].Type); - DEBUG((DEBUG_ERROR, "Comphy-%d: %-13s %-10s\n", Lane, TypeStr, SpeedSt= r)); + DEBUG ((DEBUG_ERROR, "Comphy%d-%d: %-13s %-10s\n", Index, Lane, TypeSt= r, SpeedStr)); } =20 DEBUG((DEBUG_ERROR, "\n")); @@ -238,16 +198,16 @@ InitComPhyConfig ( */ switch (Id) { case 0: - GetComPhyPcd (ChipConfig, LaneData, 0); + GetComPhyPcd (LaneData, 0); break; case 1: - GetComPhyPcd (ChipConfig, LaneData, 1); + GetComPhyPcd (LaneData, 1); break; case 2: - GetComPhyPcd (ChipConfig, LaneData, 2); + GetComPhyPcd (LaneData, 2); break; case 3: - GetComPhyPcd (ChipConfig, LaneData, 3); + GetComPhyPcd (LaneData, 3); break; } } @@ -288,12 +248,9 @@ MvComPhyInit ( /* Get the count of the SerDes of the specific chip */ MaxComphyCount =3D PtrChipCfg->LanesCount; for (Lane =3D 0; Lane < MaxComphyCount; Lane++) { - /* Parse PCD with string indicating SerDes Type */ - PtrChipCfg->MapData[Lane].Type =3D - ParseSerdesTypeString (LaneData[Index].TypeStr[Lane]); - PtrChipCfg->MapData[Lane].Speed =3D - ParseSerdesSpeed (LaneData[Index].SpeedValue[Lane]); - PtrChipCfg->MapData[Lane].Invert =3D (UINT32)LaneData[Index].InvFlag= [Lane]; + PtrChipCfg->MapData[Lane].Type =3D LaneData[Index].Type[Lane]; + PtrChipCfg->MapData[Lane].Speed =3D LaneData[Index].SpeedValue[Lane]; + PtrChipCfg->MapData[Lane].Invert =3D LaneData[Index].InvFlag[Lane]; =20 if ((PtrChipCfg->MapData[Lane].Speed =3D=3D COMPHY_SPEED_INVALID) || (PtrChipCfg->MapData[Lane].Speed =3D=3D COMPHY_SPEED_ERROR) || @@ -311,7 +268,7 @@ MvComPhyInit ( return Status; } =20 - ComPhyPrint (PtrChipCfg); + ComPhyPrint (PtrChipCfg, Index); =20 /* PHY power UP sequence */ PtrChipCfg->Init (PtrChipCfg); diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.h index 3898978..5899a4a 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -43,7 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include =20 #define MAX_LANE_OPTIONS 10 =20 @@ -52,14 +51,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define GET_LANE_SPEED(id) PcdGetPtr(PcdChip##id##ComPhySpeeds) #define GET_LANE_INV(id) PcdGetPtr(PcdChip##id##ComPhyInvFlags) =20 -#define FillLaneMap(chip_struct, lane_struct, id) { \ - ParsePcdString((CHAR16 *) GET_LANE_TYPE(id), chip_struct[id].LanesCount,= NULL, lane_struct[id].TypeStr); \ - ParsePcdString((CHAR16 *) GET_LANE_SPEED(id), chip_struct[id].LanesCount= , lane_struct[id].SpeedValue, NULL); \ - ParsePcdString((CHAR16 *) GET_LANE_INV(id), chip_struct[id].LanesCount, = lane_struct[id].InvFlag, NULL); \ -} - -#define GetComPhyPcd(chip_struct, lane_struct, id) { \ - FillLaneMap(chip_struct, lane_struct, id); \ +#define GetComPhyPcd(lane_struct, id) { \ + lane_struct[id].Type =3D (UINT8 *)GET_LANE_TYPE(id); \ + lane_struct[id].SpeedValue =3D (UINT8 *)GET_LANE_SPEED(id); \ + lane_struct[id].InvFlag =3D (UINT8 *)GET_LANE_SPEED(id); \ } =20 /***** ComPhy *****/ @@ -573,15 +568,15 @@ typedef struct { } COMPHY_MUX_DATA; =20 typedef struct { - UINT32 Type; - UINT32 Speed; - UINT32 Invert; + UINT8 Type; + UINT8 Speed; + UINT8 Invert; } COMPHY_MAP; =20 typedef struct { - CHAR16 *TypeStr[MAX_LANE_OPTIONS]; - UINTN SpeedValue[MAX_LANE_OPTIONS]; - UINTN InvFlag[MAX_LANE_OPTIONS]; + UINT8 *Type; + UINT8 *SpeedValue; + UINT8 *InvFlag; } PCD_LANE_MAP; =20 typedef diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyLib.inf index e0f4634..c223fe5 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -51,7 +51,6 @@ MemoryAllocationLib PcdLib IoLib - ParsePcdLib =20 [Sources.common] ComPhyLib.c diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 83ebe9d..25cb66b 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -57,35 +57,68 @@ Every ComPhy PCD has part where stands for = chip ID (order is not important, but configuration will be set for first PcdComPhyChipCount chip= s). =20 Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes -settings for this chip. Their format is unicode string, containing settings -for up to 10 lanes. Setting for each one is separated with semicolon. -These PCDs together describe outputs of PHY integrated in simple cihp. -Below is example for the first chip (Chip0). +settings for this chip. Their format is array of up to 10 values reflecting +defined numbers for SPEED/TYPE/INVERT, whose description can be found in: =20 - - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes - (Unicode string indicating PHY types. Currently supported are: + OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h =20 - { L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", - L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", - L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", - L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", - L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0", - L"RXAUI1", L"KR" } ) + - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + (Array of types - currently supported are: + + CP_UNCONNECTED 0x0 + CP_PCIE0 0x1 + CP_PCIE1 0x2 + CP_PCIE2 0x3 + CP_PCIE3 0x4 + CP_SATA0 0x5 + CP_SATA1 0x6 + CP_SATA2 0x7 + CP_SATA3 0x8 + CP_SGMII0 0x9 + CP_SGMII1 0xA + CP_SGMII2 0xB + CP_SGMII3 0xC + CP_QSGMII 0xD + CP_USB3_HOST0 0xE + CP_USB3_HOST1 0xF + CP_USB3_DEVICE 0x10 + CP_XAUI0 0x11 + CP_XAUI1 0x12 + CP_XAUI2 0x13 + CP_XAUI3 0x14 + CP_RXAUI0 0x15 + CP_RXAUI1 0x16 + CP_SFI 0x17 ) =20 - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds - (Indicates PHY speeds in MHz. Currently supported are: - { 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 1031 } ) + (Array of speeds - currently supported are: + + CP_1_25G 0x1 + CP_1_5G 0x2 + CP_2_5G 0x3 + CP_3G 0x4 + CP_3_125G 0x5 + CP_5G 0x6 + CP_5_15625G 0x7 + CP_6G 0x8 + CP_6_25G 0x9 + CP_10_3125G 0xA ) =20 - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags - (Indicates lane polarity invert) + (Array of lane inversion types - currently supported are: + + CP_NO_INVERT 0x0 + CP_TXD_INVERT 0x1 + CP_RXD_INVERT 0x2 + CP_ALL_INVERT 0x3 ) =20 Example ------- =20 #ComPhy gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SAT= A1;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;500= 0;5000" + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_H= OST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $= (CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 =20 PHY Driver configuration --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:53:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507459799013919.8473940844559; Sun, 8 Oct 2017 03:49:59 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C81C02095B07E; Sun, 8 Oct 2017 03:46:30 -0700 (PDT) Received: from mail-lf0-x229.google.com (mail-lf0-x229.google.com [IPv6:2a00:1450:4010:c07::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9344D2095B07B for ; Sun, 8 Oct 2017 03:46:28 -0700 (PDT) Received: by mail-lf0-x229.google.com with SMTP id l196so24508649lfl.1 for ; Sun, 08 Oct 2017 03:49:54 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id y17sm930370lfj.0.2017.10.08.03.49.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 08 Oct 2017 03:49:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::229; helo=mail-lf0-x229.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qp3VpATz0S8pFa0uG6qFN3IDOYT82eism9o8oDMCXbg=; b=XHka3KRGXxxtcl7myhDnrnkP8Y5FETqBRZKmJ0aB8mPgFhjELXAHSJw5L7xaz1ikcQ p/ZPnCuHWGz47U7kCcv1ON/UJeXMKfPVuHJWgjSGEPPjYN5qClTkow0VqoeZlBiHATse hxI+6mbJmVVvZq7wpN5RkwzOxTwvD+LXn4bGy9yfQvYiNaAk+ubfd2KwCFz7yxCUaPQP 4MUh4WAUTHyZtwJ1eAXraonfKBGeKcmq/6imlll8zd2W6X3TyzZXAxDIwaeNaTBkcLae 6/iBMTHF+8d6fkA4YIUC86xLEmRMX+Vs4BI3TKzAavi5rtzk6E7qSxXUhC3e590HhBwd 7ajQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qp3VpATz0S8pFa0uG6qFN3IDOYT82eism9o8oDMCXbg=; b=mF9l0z5Aapa1FzY8lrgsz0qbSmHpzATTZTgvgv+CgtZEEOjX4moDojGzEQIE8aYKoq XjByvTw1oW50kjchOw2dYKEGvnedbq3N4pAemGkhVGqqI3MkyvcCL+ci8wSrq9hDW6f/ zd7u8ICdmdJm93sUypa78aMqg7oVStfQ1FyhPvqqjttFhaz4CiWayD3bTrWzxLIyhaMf BMREiTYLg4BIX7ecWTya6Y2FL3A3R4fEGBRHssghQS7Vz9UOxAEb5hyRGDwyXVru4Dcx CKpNKWsUyGGD/7W67jfiOiA2gb9PD3e3gtRwGFN6vyJk1ICritKdJb8M4quXF81xm4Rp q5kQ== X-Gm-Message-State: AMCzsaVZL16KwiWTGir4nkg/36hPeiokL/s/KSu+62Hn+vAmzLUaH7jH 8EsraCnpv+o2lJbr/tN9u+8bK6CvxzI= X-Google-Smtp-Source: AOwi7QDJTqpwsXWAQ4Ec5NHFAododPe1dRgMGXvuhf8hHkeP0FtH9DkBGEA/zB5aE/GxiXJpxhUoHg== X-Received: by 10.25.165.212 with SMTP id o203mr945193lfe.204.1507459792481; Sun, 08 Oct 2017 03:49:52 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 8 Oct 2017 12:56:49 +0200 Message-Id: <1507460212-10323-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507460212-10323-1-git-send-email-mw@semihalf.com> References: <1507460212-10323-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 2/5] Marvell/Drivers: MvI2cDxe: Move devices description to MvHwDescLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces I2c description, using the new structures and template in MvHwDescLib. This change enables more flexible addition of multiple I2c controllers and also allows for removal of string PCD parsing. Update Armada 70x0 DB description and PortingGuide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada70x0.dsc | 2 +- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 42 +++++++++++-------= -- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 3 +- Platform/Marvell/Include/Library/MvHwDescLib.h | 25 ++++++++++++ Platform/Marvell/Marvell.dec | 2 +- Silicon/Marvell/Documentation/PortingGuide.txt | 4 +- 6 files changed, 54 insertions(+), 24 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index dae9715..c11a973 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -78,7 +78,7 @@ # I2C gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60 } gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 } gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 } gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index fa79ebc..d85ee0b 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -42,12 +42,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include #include #include -#include #include +#include #include =20 #include "MvI2cDxe.h" =20 +DECLARE_A7K8K_I2C_TEMPLATE; + STATIC MV_I2C_BAUD_RATE baud_rate; =20 STATIC MV_I2C_DEVICE_PATH MvI2cDevicePathProtocol =3D { @@ -172,35 +174,39 @@ MvI2cInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { + MVHW_I2C_DESC *Desc =3D &mA7k8kI2cDescTemplate; + UINT8 *I2cDeviceTable, Index; EFI_STATUS Status; - UINT32 BusCount; - EFI_PHYSICAL_ADDRESS I2cBaseAddresses[PcdGet32 (PcdI2cBusCount)]; - INTN i; =20 - BusCount =3D PcdGet32 (PcdI2cBusCount); - if (BusCount =3D=3D 0) - return EFI_SUCCESS; + /* Obtain table with enabled I2c devices */ + I2cDeviceTable =3D (UINT8 *)PcdGetPtr (PcdI2cControllersEnabled); + if (I2cDeviceTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Missing PcdI2cControllersEnabled\n")); + return EFI_INVALID_PARAMETER; + } =20 - Status =3D ParsePcdString ( - (CHAR16 *) PcdGetPtr (PcdI2cBaseAddresses), - BusCount, - I2cBaseAddresses, - NULL - ); - if (EFI_ERROR(Status)) - return Status; + if (PcdGetSize (PcdI2cControllersEnabled) > MVHW_MAX_I2C_DEVS) { + DEBUG ((DEBUG_ERROR, "Wrong PcdI2cControllersEnabled format\n")); + return EFI_INVALID_PARAMETER; + } + + /* Initialize enabled chips */ + for (Index =3D 0; Index < PcdGetSize (PcdI2cControllersEnabled); Index++= ) { + if (!MVHW_DEV_ENABLED (I2c, Index)) { + DEBUG ((DEBUG_ERROR, "Skip I2c chip %d\n", Index)); + continue; + } =20 - for (i =3D 0; i < BusCount; i++) { Status =3D MvI2cInitialiseController( ImageHandle, SystemTable, - I2cBaseAddresses[i] + Desc->I2cBaseAddresses[Index] ); if (EFI_ERROR(Status)) return Status; } =20 - return Status; + return EFI_SUCCESS; } =20 STATIC diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf b/Platform/= Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf index 16374ef..80655f1 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf @@ -55,7 +55,6 @@ UefiLib UefiDriverEntryPoint UefiBootServicesTableLib - ParsePcdLib =20 [Protocols] gEfiI2cMasterProtocolGuid @@ -66,7 +65,7 @@ [Pcd] gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses gMarvellTokenSpaceGuid.PcdI2cSlaveBuses - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled gMarvellTokenSpaceGuid.PcdI2cClockFrequency gMarvellTokenSpaceGuid.PcdI2cBaudRate gMarvellTokenSpaceGuid.PcdI2cBusCount diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marv= ell/Include/Library/MvHwDescLib.h index 6a86865..e029b50 100644 --- a/Platform/Marvell/Include/Library/MvHwDescLib.h +++ b/Platform/Marvell/Include/Library/MvHwDescLib.h @@ -60,6 +60,16 @@ typedef struct { } MVHW_COMPHY_DESC; =20 // +// I2C devices description template definition +// +#define MVHW_MAX_I2C_DEVS 4 + +typedef struct { + UINT8 I2cDevCount; + UINTN I2cBaseAddresses[MVHW_MAX_I2C_DEVS]; +} MVHW_I2C_DESC; + +// // NonDiscoverable devices description template definition // #define MVHW_MAX_XHCI_DEVS 4 @@ -130,6 +140,21 @@ MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate =3D {\ } =20 // +// Platform description of I2C devices +// +#define MVHW_CP0_I2C0_BASE 0xF2701000 +#define MVHW_CP0_I2C1_BASE 0xF2701100 +#define MVHW_CP1_I2C0_BASE 0xF4701000 +#define MVHW_CP1_I2C1_BASE 0xF4701100 + +#define DECLARE_A7K8K_I2C_TEMPLATE \ +STATIC \ +MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ + 4,\ + { MVHW_CP0_I2C0_BASE, MVHW_CP0_I2C1_BASE, MVHW_CP1_I2C0_BASE, MVHW_CP1_I= 2C1_BASE }\ +} + +// // Platform description of NonDiscoverable devices // #define MVHW_CP0_XHCI0_BASE 0xF2500000 diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index fc00f1a..d2ab0a9 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -113,7 +113,7 @@ gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }|VOID*|0x3000184 gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x0 }|VOID*|0x3000050 gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0 }|VOID*|0x3000185 - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|{ 0x0 }|VOID*|0x3000047 + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }|VOID*|0x3000047 gMarvellTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x3000048 gMarvellTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x3000049 gMarvellTokenSpaceGuid.PcdI2cBusCount|0|UINT32|0x3000183 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 25cb66b..b2bb595 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -189,8 +189,8 @@ In order to enable driver on a new platform, following = steps need to be taken: (buses to which accoring slaves are attached) - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 (number of SoC's I2C buses) - - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" - (base addresses of I2C controller buses) + - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 } + (array with used controllers) - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 (I2C host controller clock frequency) - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:53:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id y17sm930370lfj.0.2017.10.08.03.49.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 08 Oct 2017 03:49:53 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::232; helo=mail-lf0-x232.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n5YUNv5BiVULFYtT5tzR1WMWRVEz1B8cBZuhyHjYZD8=; b=ep993a/ROL8J1zYH98W3MRiJQlQifXawRN/6Lb9g14+f6HXL/Sj7KtJz2Vn/jEZm94 VJ+T1PnMJNPzmhDc3BY/EZlK64hxES55LW5ugUGR/OdB9WQnsNYOhI5etJv0BelQIB/H sqYFcUTNDG4N5R/FUR74yxEOMwjYMso02LQZpXR5PmQJtwA6+26VEs57DWrnW+XccFx8 oGXApolOizCpwreuopGWOB6M8LB7gSdmSrB33U+L6uA4Mi0UJ+ScaHpxZmN5J1RvXNOk CePyIyeWRO7GzOykTD6rP08uHrlUmxg+s3mk/82iGZNTfNPq0JN0bCX/x6Yc+pEYp5Ur VtUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n5YUNv5BiVULFYtT5tzR1WMWRVEz1B8cBZuhyHjYZD8=; b=nerVELjOZuMKwh7JgLREff24bEiZQJhCjteEtVDvpRmF4FWbm+cHW79F9myqNn0n28 GvWOh1kTm6oIJuWaiq3gyLHE8XJYjeuwekP618rXZOJ5YP4NNIj95hKnsOj8zDHpCn9v z/9uwi90tbmSifVB0g8rIE9Kf0QgK6q6HAXv3p6ovICk9i6eY+t8mIL34BEcRSjIQ2KL yzEdw3/8yZ+/0ttfb08nQ69pGFT3Hngtiz4PajhbJqA901sBRE80zeKmMQj7Urs400BW ElFubrb/fiDT6Z/hMZIdewjwuXRCTj+V6XsuIn4SwG/yUYXjcYdIT/DbJDiX4X12FirZ wq9g== X-Gm-Message-State: AMCzsaXLkPMN3uK3YDdvPaXw6bZu55iYpW38gGqHAUek8TYIBTqaE4tg Cc8PvLZFaK4ii0U3R/wvK4947zIEPMU= X-Google-Smtp-Source: AOwi7QB3tVB2KH7+x+y833UByOB5JazhMjGR8i+DqP0nRXBh56vmOtVqVDO7922b/ueOGsWlEfJGTA== X-Received: by 10.25.59.208 with SMTP id d77mr2523397lfl.189.1507459793759; Sun, 08 Oct 2017 03:49:53 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 8 Oct 2017 12:56:50 +0200 Message-Id: <1507460212-10323-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507460212-10323-1-git-send-email-mw@semihalf.com> References: <1507460212-10323-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 3/5] Marvell/Library: UtmiLib: Move devices description to MvHwDescLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces UTMI description, using the new structures and template in MvHwDescLib. This change enables more flexible addition of multiple CP with UTMI PHY's and also significantly reduces amount of used PCD's for that purpose. Update PortingGuide documentation accordingly. This patch replaces string-based description of Utmi on Armada 70x0 DB with new, reduced format, which uses macros in Armada.dsc.inc file for better readability. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 5 + Platform/Marvell/Armada/Armada70x0.dsc | 7 +- Platform/Marvell/Include/Library/MvHwDescLib.h | 47 ++++++ Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 150 ++++++++++-------= --- Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 1 - Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 11 +- Platform/Marvell/Marvell.dec | 7 +- Silicon/Marvell/Documentation/PortingGuide.txt | 30 ++-- 8 files changed, 148 insertions(+), 110 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index cd26506..7d0dc39 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -523,3 +523,8 @@ DEFINE CP_RXAUI0 =3D 0x15 DEFINE CP_RXAUI1 =3D 0x16 DEFINE CP_SFI =3D 0x17 + + #UTMI PHY connection type + DEFINE UTMI_USB_HOST0 =3D 0x0 + DEFINE UTMI_USB_HOST1 =3D 0x1 + DEFINE UTMI_USB_DEVICE0 =3D 0x2 diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index c11a973..b40766b 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -111,11 +111,8 @@ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(C= P_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 #UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) } =20 #MDIO gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200 diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marv= ell/Include/Library/MvHwDescLib.h index e029b50..6ad1bc2 100644 --- a/Platform/Marvell/Include/Library/MvHwDescLib.h +++ b/Platform/Marvell/Include/Library/MvHwDescLib.h @@ -117,6 +117,19 @@ typedef struct { } MVHW_RTC_DESC; =20 // +// UTMI PHY's description template definition +// + +typedef struct { + UINT8 UtmiDevCount; + UINT32 UtmiPhyId[MVHW_MAX_XHCI_DEVS]; + UINTN UtmiBaseAddresses[MVHW_MAX_XHCI_DEVS]; + UINTN UtmiConfigAddresses[MVHW_MAX_XHCI_DEVS]; + UINTN UtmiUsbConfigAddresses[MVHW_MAX_XHCI_DEVS]; + UINTN UtmiMuxBitCount[MVHW_MAX_XHCI_DEVS]; +} MVHW_UTMI_DESC; + +// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -217,4 +230,38 @@ MVHW_RTC_DESC mA7k8kRtcDescTemplate =3D {\ { SIZE_4KB, SIZE_4KB }\ } =20 +// +// Platform description of UTMI PHY's +// +#define MVHW_CP0_UTMI0_BASE 0xF2580000 +#define MVHW_CP0_UTMI0_CFG_BASE 0xF2440440 +#define MVHW_CP0_UTMI0_USB_CFG_BASE 0xF2440420 +#define MVHW_CP0_UTMI0_ID 0x0 +#define MVHW_CP0_UTMI1_BASE 0xF2581000 +#define MVHW_CP0_UTMI1_CFG_BASE 0xF2440444 +#define MVHW_CP0_UTMI1_USB_CFG_BASE 0xF2440420 +#define MVHW_CP0_UTMI1_ID 0x1 +#define MVHW_CP1_UTMI0_BASE 0xF4580000 +#define MVHW_CP1_UTMI0_CFG_BASE 0xF4440440 +#define MVHW_CP1_UTMI0_USB_CFG_BASE 0xF4440420 +#define MVHW_CP1_UTMI0_ID 0x0 +#define MVHW_CP1_UTMI1_BASE 0xF4581000 +#define MVHW_CP1_UTMI1_CFG_BASE 0xF4440444 +#define MVHW_CP1_UTMI1_USB_CFG_BASE 0xF4440420 +#define MVHW_CP1_UTMI1_ID 0x1 + +#define DECLARE_A7K8K_UTMI_TEMPLATE \ +STATIC \ +MVHW_UTMI_DESC mA7k8kUtmiDescTemplate =3D {\ + 4,\ + { MVHW_CP0_UTMI0_ID, MVHW_CP0_UTMI1_ID,\ + MVHW_CP1_UTMI0_ID, MVHW_CP1_UTMI1_ID },\ + { MVHW_CP0_UTMI0_BASE, MVHW_CP0_UTMI1_BASE,\ + MVHW_CP1_UTMI0_BASE, MVHW_CP1_UTMI1_BASE },\ + { MVHW_CP0_UTMI0_CFG_BASE, MVHW_CP0_UTMI1_CFG_BASE,\ + MVHW_CP1_UTMI0_CFG_BASE, MVHW_CP1_UTMI1_CFG_BASE },\ + { MVHW_CP0_UTMI0_USB_CFG_BASE, MVHW_CP0_UTMI1_USB_CFG_BASE,\ + MVHW_CP1_UTMI0_USB_CFG_BASE, MVHW_CP1_UTMI1_USB_CFG_BASE }\ +} + #endif /* __MVHWDESCLIB_H__ */ diff --git a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Platform/Ma= rvell/Library/UtmiPhyLib/UtmiPhyLib.c index 95b5698..f1819c4 100644 --- a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c +++ b/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c @@ -33,12 +33,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. **************************************************************************= *****/ =20 #include "UtmiPhyLib.h" +#include + +DECLARE_A7K8K_UTMI_TEMPLATE; =20 typedef struct { EFI_PHYSICAL_ADDRESS UtmiBaseAddr; EFI_PHYSICAL_ADDRESS UsbCfgAddr; EFI_PHYSICAL_ADDRESS UtmiCfgAddr; UINT32 UtmiPhyPort; + UINT32 PhyId; } UTMI_PHY_DATA; =20 STATIC @@ -236,48 +240,52 @@ UtmiPhyPowerUp ( STATIC VOID Cp110UtmiPhyInit ( - IN UINT32 UtmiPhyCount, IN UTMI_PHY_DATA *UtmiData ) { - UINT32 i; + EFI_STATUS Status; =20 - for (i =3D 0; i < UtmiPhyCount; i++) { - UtmiPhyPowerDown(i, UtmiData[i].UtmiBaseAddr, - UtmiData[i].UsbCfgAddr, UtmiData[i].UtmiCfgAddr, - UtmiData[i].UtmiPhyPort); - } + UtmiPhyPowerDown ( + UtmiData->PhyId, + UtmiData->UtmiBaseAddr, + UtmiData->UsbCfgAddr, + UtmiData->UtmiCfgAddr, + UtmiData->UtmiPhyPort + ); =20 /* Power down PLL */ DEBUG((DEBUG_INFO, "UtmiPhy: stage: PHY power down PLL\n")); - RegSet (UtmiData[0].UsbCfgAddr, 0x0 << UTMI_USB_CFG_PLL_OFFSET, - UTMI_USB_CFG_PLL_MASK); - - for (i =3D 0; i < UtmiPhyCount; i++) { - UtmiPhyConfig(i, UtmiData[i].UtmiBaseAddr, - UtmiData[i].UsbCfgAddr, UtmiData[i].UtmiCfgAddr, - UtmiData[i].UtmiPhyPort); + MmioAnd32 (UtmiData->UsbCfgAddr, ~UTMI_USB_CFG_PLL_MASK); + + UtmiPhyConfig ( + UtmiData->PhyId, + UtmiData->UtmiBaseAddr, + UtmiData->UsbCfgAddr, + UtmiData->UtmiCfgAddr, + UtmiData->UtmiPhyPort + ); + + Status =3D UtmiPhyPowerUp ( + UtmiData->PhyId, + UtmiData->UtmiBaseAddr, + UtmiData->UsbCfgAddr, + UtmiData->UtmiCfgAddr, + UtmiData->UtmiPhyPort + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UtmiPhy: Failed to initialize UTMI PHY %d\n", Ut= miData->PhyId)); + return; } =20 - for (i =3D 0; i < UtmiPhyCount; i++) { - if (EFI_ERROR(UtmiPhyPowerUp(i, UtmiData[i].UtmiBaseAddr, - UtmiData[i].UsbCfgAddr, UtmiData[i].UtmiCfgAddr, - UtmiData[i].UtmiPhyPort))) { - DEBUG((DEBUG_ERROR, "UtmiPhy: Failed to initialize UTMI PHY %d\n", i= )); - continue; - } - DEBUG((DEBUG_ERROR, "UTMI PHY %d initialized to ", i)); - - if (UtmiData[i].UtmiPhyPort =3D=3D UTMI_PHY_TO_USB_DEVICE0) - DEBUG((DEBUG_ERROR, "USB Device\n")); - else - DEBUG((DEBUG_ERROR, "USB Host%d\n", UtmiData[i].UtmiPhyPort)); - } + DEBUG ((DEBUG_ERROR, "UTMI PHY %d initialized to ", UtmiData->PhyId)); + if (UtmiData->UtmiPhyPort =3D=3D UTMI_PHY_TO_USB_DEVICE0) + DEBUG((DEBUG_ERROR, "USB Device\n")); + else + DEBUG((DEBUG_ERROR, "USB Host%d\n", UtmiData->UtmiPhyPort)); =20 /* Power up PLL */ DEBUG((DEBUG_INFO, "UtmiPhy: stage: PHY power up PLL\n")); - RegSet (UtmiData[0].UsbCfgAddr, 0x1 << UTMI_USB_CFG_PLL_OFFSET, - UTMI_USB_CFG_PLL_MASK); + MmioOr32 (UtmiData->UsbCfgAddr, UTMI_USB_CFG_PLL_MASK); } =20 EFI_STATUS @@ -285,69 +293,67 @@ UtmiPhyInit ( VOID ) { - EFI_STATUS Status; - UTMI_PHY_DATA UtmiData[PcdGet32 (PcdUtmiPhyCount)]; - EFI_PHYSICAL_ADDRESS RegUtmiUnit[PcdGet32 (PcdUtmiPhyCount)]; - EFI_PHYSICAL_ADDRESS RegUsbCfg[PcdGet32 (PcdUtmiPhyCount)]; - EFI_PHYSICAL_ADDRESS RegUtmiCfg[PcdGet32 (PcdUtmiPhyCount)]; - UINTN UtmiPort[PcdGet32 (PcdUtmiPhyCount)]; - UINTN i, Count; - - Count =3D PcdGet32 (PcdUtmiPhyCount); - if (Count =3D=3D 0) { + UTMI_PHY_DATA UtmiData; + UINT8 *UtmiDeviceTable, *XhciDeviceTable, *UtmiPortType, Index; + MVHW_UTMI_DESC *Desc =3D &mA7k8kUtmiDescTemplate; + + /* Obtain table with enabled Utmi PHY's*/ + UtmiDeviceTable =3D (UINT8 *)PcdGetPtr (PcdUtmiControllersEnabled); + if (UtmiDeviceTable =3D=3D NULL) { /* No UTMI PHY on platform */ return EFI_SUCCESS; } =20 - DEBUG((DEBUG_INFO, "UtmiPhy: Initialize USB UTMI PHYs\n")); - /* Parse UtmiPhy PCDs */ - Status =3D ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyRegUtmiUnit), - Count, RegUtmiUnit, NULL); - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyRegUtmiUnit format\n")); + if (PcdGetSize (PcdUtmiControllersEnabled) > MVHW_MAX_XHCI_DEVS) { + DEBUG ((DEBUG_ERROR, "UTMI: Wrong PcdUtmiControllersEnabled format\n")= ); return EFI_INVALID_PARAMETER; } =20 - Status =3D ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyRegUsbCfg), - Count, RegUsbCfg, NULL); - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyRegUsbCfg format\n")); + /* Make sure XHCI controllers table is present */ + XhciDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciEXhci); + if (XhciDeviceTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "UTMI: Missing PcdPciEXhci\n")); return EFI_INVALID_PARAMETER; } =20 - Status =3D ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyRegUtmiCfg), - Count, RegUtmiCfg, NULL); - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyRegUtmiCfg format\n")); + /* Obtain port type table */ + UtmiPortType =3D (UINT8 *)PcdGetPtr (PcdUtmiPortType); + if (UtmiPortType =3D=3D NULL || + PcdGetSize (PcdUtmiPortType) !=3D PcdGetSize (PcdUtmiControllersEnab= led)) { + DEBUG ((DEBUG_ERROR, "UTMI: Wrong PcdUtmiPortType format\n")); return EFI_INVALID_PARAMETER; } =20 - Status =3D ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyUtmiPort), - Count, UtmiPort, NULL); - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyUtmiPort format\n")); - return EFI_INVALID_PARAMETER; - } + /* Initialize enabled chips */ + for (Index =3D 0; Index < PcdGetSize (PcdUtmiControllersEnabled); Index+= +) { + if (!MVHW_DEV_ENABLED (Utmi, Index)) { + continue; + } + + /* UTMI PHY without enabled XHCI controller is useless */ + if (!MVHW_DEV_ENABLED (Xhci, Index)) { + DEBUG ((DEBUG_ERROR, "UTMI: Disabled Xhci controller %d\n", Index)); + return EFI_INVALID_PARAMETER; + } =20 - for (i =3D 0 ; i < Count ; i++) { /* Get base address of UTMI phy */ - UtmiData[i].UtmiBaseAddr =3D RegUtmiUnit[i]; + UtmiData.UtmiBaseAddr =3D Desc->UtmiBaseAddresses[Index]; =20 /* Get usb config address */ - UtmiData[i].UsbCfgAddr =3D RegUsbCfg[i]; + UtmiData.UsbCfgAddr =3D Desc->UtmiUsbConfigAddresses[Index]; =20 /* Get UTMI config address */ - UtmiData[i].UtmiCfgAddr =3D RegUtmiCfg[i]; + UtmiData.UtmiCfgAddr =3D Desc->UtmiConfigAddresses[Index]; =20 - /* - * Get the usb port number, which will be used to check if - * the utmi connected to host or device - */ - UtmiData[i].UtmiPhyPort =3D UtmiPort[i]; - } + /* Get UTMI PHY ID */ + UtmiData.PhyId =3D Desc->UtmiPhyId[Index]; =20 - /* Currently only Cp110 is supported */ - Cp110UtmiPhyInit (Count, UtmiData); + /* Get the usb port type */ + UtmiData.UtmiPhyPort =3D UtmiPortType[Index]; + + /* Currently only Cp110 is supported */ + Cp110UtmiPhyInit (&UtmiData); + } =20 return EFI_SUCCESS; } diff --git a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Platform/Ma= rvell/Library/UtmiPhyLib/UtmiPhyLib.h index f9b4933..0d7d72e 100644 --- a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h +++ b/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h @@ -42,7 +42,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include =20 #define UTMI_USB_CFG_DEVICE_EN_OFFSET 0 #define UTMI_USB_CFG_DEVICE_EN_MASK (0x1 << UTMI_USB_CFG_DEV= ICE_EN_OFFSET) diff --git a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf b/Platform/= Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf index f1e57f4..b56c43b 100644 --- a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf +++ b/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf @@ -50,15 +50,12 @@ DebugLib IoLib MemoryAllocationLib - ParsePcdLib PcdLib =20 [Sources.common] UtmiPhyLib.c =20 -[FixedPcd] - gMarvellTokenSpaceGuid.PcdUtmiPhyCount - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort +[Pcd] + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled + gMarvellTokenSpaceGuid.PcdUtmiPortType + gMarvellTokenSpaceGuid.PcdPciEXhci diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index d2ab0a9..e23607f 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -156,11 +156,8 @@ gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x30000177 =20 #UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiPhyCount|0|UINT32|0x30000205 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|{ 0x0 }|VOID*|0x30000206 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|{ 0x0 }|VOID*|0x30000207 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|{ 0x0 }|VOID*|0x30000208 - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|{ 0x0 }|VOID*|0x30000209 + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x0 }|VOID*|0x30000206 + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ 0x0 }|VOID*|0x30000207 =20 #MDIO gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0|UINT64|0x3000043 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index b2bb595..fa429d1 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -279,33 +279,23 @@ UTMI PHY configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D In order to configure UTMI, following PCDs are available: =20 - - gMarvellTokenSpaceGuid.PcdUtmiPhyCount - (Indicates how many UTMI PHYs are available on platform) - -Next four PCDs are in unicode string format containing settings for all de= vices -separated with semicolon. - - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit - (Indicates base address of the UTMI unit) - - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg - (Indicates address of USB Configuration register) + - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) =20 - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg - (Indicates address of external UTMI configuration) + - gMarvellTokenSpaceGuid.PcdUtmiPortType + (Indicates type of the connected USB port: =20 - - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort - (Indicates type of the connected USB port) + UTMI_USB_HOST0 0x0 + UTMI_USB_HOST1 0x1 + UTMI_USB_DEVICE0 0x2 ) =20 Example ------- =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444" - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB= _HOST1) } =20 =20 SPI driver configuration --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:53:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id y17sm930370lfj.0.2017.10.08.03.49.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 08 Oct 2017 03:49:54 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22c; helo=mail-lf0-x22c.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pxeabwQqipKB4HktFtszTRmHw0zVvWVCkcx5urgkT1w=; b=PgWngGIANFbX86QcVCrj7umm2T/XG0HasSTmYIvWJsDja6zmA7CEBAqaW+NPrv5jUp RaK3drbh62IBZZg7qFpqcLC4r3Pg98Q48usCPWY+QzkDBszyjVq1twSpDpqLKDYZtfSG 9/nFpPskWmaTuB4mlPJDYkceFtGQ6gVloHEE8kp7IUmAIEoOrFOrmyBu0stYllWmQwWC Nr8AlUtIuxzdHyWaoa472cOpmP1MNKX70ngjPd6qBN3O83bNm+3PBH1e8GpT3HpEDUVL Yru6S3rvCwH1b2S7htTDsh5ypP4fZSMvzmfU+3XG1d1xsNtZSpjr0uwDH4TApoVJAQX2 0Bwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pxeabwQqipKB4HktFtszTRmHw0zVvWVCkcx5urgkT1w=; b=f6Kejxsmpsfg5TMHpFRtyqfespf1YmQPhM72hXodz5I3+2SS+fOuVyJ8XCEjt6+yZ9 lGjbuKeU5ClewYBfsK8r67Q2wAf8uSPIXaanVRT6oqr53ymMrezxhRov41TuR8JwgoEt NRjH7OZ9e+fJDiK/PWGr4UdAMeOPkK5RdYDtTPTiW54JXZ+B0Dt6X3xYrl4O3+iHVvAQ WYo4okDY9TUuACVm4PX6i7c0JbO6C7SZaGQ0rSFM/iqmTSAfVk3tbVLtLKMmS8WxDfnx 53tzF6/uBLMCe3wUOFrJKRiAXCqkqf8wNsiZbS18pXhgjOJBHwCGpvUqBcaK2bUF1A6x hSgA== X-Gm-Message-State: AMCzsaWqPm/uswV+yVpfz8F0EHqDSdIGRhKpSHAGwWEwZLeMsM15OUOz 4BKyKgoYjxHjSuj0XRmzK7rAKVQBxcE= X-Google-Smtp-Source: AOwi7QB6y7uBuYKrcso8P16faA/p/y71ksWs8TWc7X34aLhQMpm/7zw7EwGq4v7gbIhsKdT0HrNj+Q== X-Received: by 10.25.234.195 with SMTP id y64mr2563195lfi.36.1507459795082; Sun, 08 Oct 2017 03:49:55 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 8 Oct 2017 12:56:51 +0200 Message-Id: <1507460212-10323-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507460212-10323-1-git-send-email-mw@semihalf.com> References: <1507460212-10323-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 4/5] Marvell/Drivers: Pp2Dxe: Rework PHY handling X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Hitherto PHY handling in Pp2Dxe was not flexible. It allowed for using only single MDIO controller, which may not be true on Armada 80x0 SoCs. For this purpose introduce the MDIO description, using the new structures and template in MvHwDescLib. This change enables addition of multiple CP110 hardware blocks with MDIO controllers. This change required different PHY handling and obtaining data over desired MDIO bus. Now given Pp2 port is matched with the PHY via its index in gMarvellTokenSpaceGuid.PcdPhyDeviceIds. The PHY itself is mapped to the MDIO controller, using gMarvellTokenSpaceGuid.PcdPhy2MdioController. Also obtaining SMI addresses was moved to the PHY initialization routine. All above allow for much cleaner and logical PHY description in the .dsc file, which now uses macros for connection type and speed. Update PortingGuide documentation accordingly and Armada 70x0 DB NIC/PHY description. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 18 +++ Platform/Marvell/Armada/Armada70x0.dsc | 10 +- Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c | 35 ++++-- Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 3 - Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 122 ++++++++++++-= ------- Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 2 - Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf | 4 +- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 16 +-- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 2 +- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 4 +- Platform/Marvell/Include/Library/MvHwDescLib.h | 23 ++++ Platform/Marvell/Include/Protocol/Mdio.h | 6 + Platform/Marvell/Include/Protocol/MvPhy.h | 1 + Platform/Marvell/Marvell.dec | 8 +- Silicon/Marvell/Documentation/PortingGuide.txt | 66 +++++------ 15 files changed, 203 insertions(+), 117 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 7d0dc39..7258017 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -524,6 +524,24 @@ DEFINE CP_RXAUI1 =3D 0x16 DEFINE CP_SFI =3D 0x17 =20 + #Network interface speed + DEFINE PHY_SPEED_10 =3D 0x1 + DEFINE PHY_SPEED_100 =3D 0x2 + DEFINE PHY_SPEED_1000 =3D 0x3 + DEFINE PHY_SPEED_2500 =3D 0x4 + DEFINE PHY_SPEED_10000 =3D 0x5 + + #Network PHY type + DEFINE PHY_RGMII =3D 0x0 + DEFINE PHY_RGMII_ID =3D 0x1 + DEFINE PHY_RGMII_TXID =3D 0x2 + DEFINE PHY_RGMII_RXID =3D 0x3 + DEFINE PHY_SGMII =3D 0x4 + DEFINE PHY_RTBI =3D 0x5 + DEFINE PHY_XAUI =3D 0x6 + DEFINE PHY_RXAUI =3D 0x7 + DEFINE PHY_SFI =3D 0x8 + #UTMI PHY connection type DEFINE UTMI_USB_HOST0 =3D 0x0 DEFINE UTMI_USB_HOST1 =3D 0x1 diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index b40766b..430803c 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -115,18 +115,20 @@ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) } =20 #MDIO - gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200 + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } =20 #PHY - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x8, 0x4, 0x0 } + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 #NET - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 } gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SGMI= I), $(PHY_RGMII) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } diff --git a/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c b/Platform/= Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c index ae466d7..12aabad 100644 --- a/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c +++ b/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c @@ -46,7 +46,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "MvMdioDxe.h" =20 -UINT64 MdioBase =3D 0; +DECLARE_A7K8K_MDIO_TEMPLATE; =20 STATIC EFI_STATUS @@ -70,7 +70,7 @@ MdioCheckParam ( STATIC EFI_STATUS MdioWaitReady ( - VOID + UINT32 MdioBase ) { UINT32 Timeout =3D MVEBU_SMI_TIMEOUT; @@ -92,7 +92,7 @@ MdioWaitReady ( STATIC EFI_STATUS MdioWaitValid ( - VOID + UINT32 MdioBase ) { UINT32 Timeout =3D MVEBU_SMI_TIMEOUT; @@ -116,11 +116,13 @@ EFI_STATUS MdioOperation ( IN CONST MARVELL_MDIO_PROTOCOL *This, IN UINT32 PhyAddr, + IN UINT32 MdioIndex, IN UINT32 RegOff, IN BOOLEAN Write, IN OUT UINT32 *Data ) { + UINT32 MdioBase =3D This->BaseAddresses[MdioIndex]; UINT32 MdioReg; EFI_STATUS Status; =20 @@ -131,7 +133,7 @@ MdioOperation ( } =20 /* wait till the SMI is not busy */ - Status =3D MdioWaitReady (); + Status =3D MdioWaitReady (MdioBase); if (EFI_ERROR(Status)) { DEBUG((DEBUG_ERROR, "MdioDxe: MdioWaitReady error\n")); return Status; @@ -151,7 +153,7 @@ MdioOperation ( MdioRegWrite32 (MdioReg, MdioBase); =20 /* make sure that the write transaction is over */ - Status =3D Write ? MdioWaitReady () : MdioWaitValid (); + Status =3D Write ? MdioWaitReady (MdioBase) : MdioWaitValid (MdioBase); if (EFI_ERROR(Status)) { DEBUG((DEBUG_ERROR, "MdioDxe: MdioWaitReady error\n")); return Status; @@ -169,6 +171,7 @@ EFI_STATUS MvMdioRead ( IN CONST MARVELL_MDIO_PROTOCOL *This, IN UINT32 PhyAddr, + IN UINT32 MdioIndex, IN UINT32 RegOff, IN UINT32 *Data ) @@ -178,6 +181,7 @@ MvMdioRead ( Status =3D MdioOperation ( This, PhyAddr, + MdioIndex, RegOff, FALSE, Data @@ -190,6 +194,7 @@ EFI_STATUS MvMdioWrite ( IN CONST MARVELL_MDIO_PROTOCOL *This, IN UINT32 PhyAddr, + IN UINT32 MdioIndex, IN UINT32 RegOff, IN UINT32 Data ) @@ -197,6 +202,7 @@ MvMdioWrite ( return MdioOperation ( This, PhyAddr, + MdioIndex, RegOff, TRUE, &Data @@ -210,18 +216,27 @@ MvMdioDxeInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { + MVHW_MDIO_DESC *Desc =3D &mA7k8kMdioDescTemplate; + UINT8 Index; MARVELL_MDIO_PROTOCOL *Mdio; EFI_STATUS Status; EFI_HANDLE Handle =3D NULL; =20 Mdio =3D AllocateZeroPool (sizeof (MARVELL_MDIO_PROTOCOL)); + if (Mdio =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "MdioDxe: Protocol allocation failed\n")); + return EFI_OUT_OF_RESOURCES; + } + + /* Obtain base addresses of all possible controllers */ + for (Index =3D 0; Index < Desc->MdioDevCount; Index++) { + Mdio->BaseAddresses[Index] =3D Desc->MdioBaseAddresses[Index]; + } + + Mdio->ControllerCount =3D Desc->MdioDevCount; Mdio->Read =3D MvMdioRead; Mdio->Write =3D MvMdioWrite; - MdioBase =3D PcdGet64 (PcdMdioBaseAddress); - if (MdioBase =3D=3D 0) { - DEBUG((DEBUG_ERROR, "MdioDxe: PcdMdioBaseAddress not set\n")); - return EFI_INVALID_PARAMETER; - } + Status =3D gBS->InstallMultipleProtocolInterfaces ( &Handle, &gMarvellMdioProtocolGuid, Mdio, diff --git a/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf b/Platfor= m/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf index faab1f7..d9878eb 100644 --- a/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf +++ b/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf @@ -62,8 +62,5 @@ [Protocols] gMarvellMdioProtocolGuid =20 -[Pcd] - gMarvellTokenSpaceGuid.PcdMdioBaseAddress - [Depex] TRUE diff --git a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c b/Platfor= m/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c index aeb6f7a..e776a91 100644 --- a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c +++ b/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include #include #include #include @@ -51,6 +52,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. =20 STATIC MARVELL_MDIO_PROTOCOL *Mdio; =20 +// +// Table with available Mdio controllers +// +STATIC UINT8 * CONST MdioDeviceTable =3D PcdGetPtr (PcdMdioControllersEnab= led); +// +// Table with PHY to Mdio controller mappings +// +STATIC UINT8 * CONST Phy2MdioController =3D PcdGetPtr (PcdPhy2MdioControll= er); +// +// Table with PHYs' SMI addresses +// +STATIC UINT8 * CONST PhySmiAddresses =3D PcdGetPtr (PcdPhySmiAddresses); + STATIC MV_PHY_DEVICE MvPhyDevices[] =3D { { MV_PHY_DEVICE_1512, MvPhyInit1512 }, { 0, NULL } @@ -64,18 +78,18 @@ MvPhyStatus ( =20 EFI_STATUS MvPhyReset ( - IN UINT32 PhyAddr + IN PHY_DEVICE *PhyDev ) { UINT32 Reg =3D 0; INTN timeout =3D TIMEOUT; =20 - Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); Reg |=3D BMCR_RESET; - Mdio->Write(Mdio, PhyAddr, MII_BMCR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, Reg); =20 while ((Reg & BMCR_RESET) && timeout--) { - Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); gBS->Stall(1000); } =20 @@ -99,7 +113,7 @@ MvPhyM88e1111sConfig ( (PhyDev->Connection =3D=3D PHY_CONNECTION_RGMII_ID) || (PhyDev->Connection =3D=3D PHY_CONNECTION_RGMII_RXID) || (PhyDev->Connection =3D=3D PHY_CONNECTION_RGMII_TXID)) { - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_CR, &Reg); =20 if ((PhyDev->Connection =3D=3D PHY_CONNECTION_RGMII) || (PhyDev->Connection =3D=3D PHY_CONNECTION_RGMII_ID)) { @@ -112,9 +126,9 @@ MvPhyM88e1111sConfig ( Reg |=3D MIIM_88E1111_TX_DELAY; } =20 - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_CR, Reg); =20 - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_SR, &Reg); =20 Reg &=3D ~(MIIM_88E1111_HWCFG_MODE_MASK); =20 @@ -123,50 +137,50 @@ MvPhyM88e1111sConfig ( else Reg |=3D MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; =20 - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_SR, Reg); } =20 if (PhyDev->Connection =3D=3D PHY_CONNECTION_SGMII) { - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_SR, &Reg); =20 Reg &=3D ~(MIIM_88E1111_HWCFG_MODE_MASK); Reg |=3D MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; Reg |=3D MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; =20 - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_SR, Reg); } =20 if (PhyDev->Connection =3D=3D PHY_CONNECTION_RTBI) { - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_CR, &Reg); Reg |=3D (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_CR, Reg); =20 - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_SR, &Reg); Reg &=3D ~(MIIM_88E1111_HWCFG_MODE_MASK | MIIM_88E1111_HWCFG_FIBER_COPPER_RES); Reg |=3D 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_SR, Reg); =20 /* Soft reset */ - MvPhyReset(PhyDev->Addr); + MvPhyReset (PhyDev); =20 - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_SR, &Reg); Reg &=3D ~(MIIM_88E1111_HWCFG_MODE_MASK | MIIM_88E1111_HWCFG_FIBER_COPPER_RES); Reg |=3D MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_SR, Reg); } =20 - Mdio->Read(Mdio, PhyDev->Addr, MII_BMCR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); Reg |=3D (BMCR_ANENABLE | BMCR_ANRESTART); Reg &=3D ~BMCR_ISOLATE; - Mdio->Write(Mdio, PhyDev->Addr, MII_BMCR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, Reg); =20 /* Soft reset */ - MvPhyReset(PhyDev->Addr); + MvPhyReset (PhyDev); =20 - MvPhyReset(PhyDev->Addr); + MvPhyReset (PhyDev); =20 return EFI_SUCCESS; } @@ -179,7 +193,7 @@ MvPhyParseStatus ( UINT32 Data; UINT32 Speed; =20 - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1xxx_PHY_STATUS, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1xxx_PHY_STAT= US, &Data); =20 if ((Data & MIIM_88E1xxx_PHYSTAT_LINK) && !(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { @@ -196,7 +210,7 @@ MvPhyParseStatus ( if ((i++ % 1000) =3D=3D 0) DEBUG((DEBUG_ERROR, ".")); gBS->Stall(1000); - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1xxx_PHY_STATUS, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1xxx_PHY_= STATUS, &Data); } DEBUG((DEBUG_ERROR," done\n")); gBS->Stall(500000); @@ -241,7 +255,7 @@ MvPhyParseStatus ( STATIC VOID MvPhy1512WriteBits ( - IN UINT32 PhyAddr, + IN PHY_DEVICE *PhyDev, IN UINT8 RegNum, IN UINT16 Offset, IN UINT16 Len, @@ -254,19 +268,18 @@ MvPhy1512WriteBits ( else Mask =3D (1 << (Len + Offset)) - (1 << Offset); =20 - Mdio->Read(Mdio, PhyAddr, RegNum, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, RegNum, &Reg); =20 Reg &=3D ~Mask; Reg |=3D Data << Offset; =20 - Mdio->Write(Mdio, PhyAddr, RegNum, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, RegNum, Reg); } =20 STATIC EFI_STATUS MvPhyInit1512 ( IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN UINT32 PhyAddr, IN OUT PHY_DEVICE *PhyDev ) { @@ -278,28 +291,28 @@ MvPhyInit1512 ( * Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 Rev A0, * Errata Section 3.1 - needed in SGMII mode. */ - Mdio->Write(Mdio, PhyAddr, 22, 0x00ff); - Mdio->Write(Mdio, PhyAddr, 17, 0x214B); - Mdio->Write(Mdio, PhyAddr, 16, 0x2144); - Mdio->Write(Mdio, PhyAddr, 17, 0x0C28); - Mdio->Write(Mdio, PhyAddr, 16, 0x2146); - Mdio->Write(Mdio, PhyAddr, 17, 0xB233); - Mdio->Write(Mdio, PhyAddr, 16, 0x214D); - Mdio->Write(Mdio, PhyAddr, 17, 0xCC0C); - Mdio->Write(Mdio, PhyAddr, 16, 0x2159); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x00ff); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0x214B); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2144); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0x0C28); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2146); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0xB233); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x214D); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0xCC0C); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2159); =20 /* Reset page selection and select page 0x12 */ - Mdio->Write(Mdio, PhyAddr, 22, 0x0000); - Mdio->Write(Mdio, PhyAddr, 22, 0x0012); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0000); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0012); =20 /* Write HWCFG_MODE =3D SGMII to Copper */ - MvPhy1512WriteBits(PhyAddr, 20, 0, 3, 1); + MvPhy1512WriteBits(PhyDev, 20, 0, 3, 1); =20 /* Phy reset - necessary after changing mode */ - MvPhy1512WriteBits(PhyAddr, 20, 15, 1, 1); + MvPhy1512WriteBits(PhyDev, 20, 15, 1, 1); =20 /* Reset page selection */ - Mdio->Write(Mdio, PhyAddr, 22, 0x0000); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0000); gBS->Stall(100); } =20 @@ -309,7 +322,7 @@ MvPhyInit1512 ( if (!PcdGetBool (PcdPhyStartupAutoneg)) return EFI_SUCCESS; =20 - Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); =20 if ((Data & BMSR_ANEGCAPABLE) && !(Data & BMSR_ANEGCOMPLETE)) { =20 @@ -322,12 +335,12 @@ MvPhyInit1512 ( } =20 gBS->Stall(1000); /* 1 ms */ - Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); } PhyDev->LinkUp =3D TRUE; DEBUG((DEBUG_INFO, "MvPhyDxe: link up\n")); } else { - Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); =20 if (Data & BMSR_LSTATUS) { PhyDev->LinkUp =3D TRUE; @@ -345,7 +358,7 @@ MvPhyInit1512 ( EFI_STATUS MvPhyInit ( IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN UINT32 PhyAddr, + IN UINT32 PhyIndex, IN PHY_CONNECTION PhyConnection, IN OUT PHY_DEVICE **OutPhyDev ) @@ -353,6 +366,7 @@ MvPhyInit ( EFI_STATUS Status; PHY_DEVICE *PhyDev; UINT8 *DeviceIds; + UINT8 MdioIndex; INTN i; =20 Status =3D gBS->LocateProtocol ( @@ -363,12 +377,20 @@ MvPhyInit ( if (EFI_ERROR(Status)) return Status; =20 + MdioIndex =3D Phy2MdioController[PhyIndex]; + + /* Verify correctness of PHY <-> MDIO assignment */ + if (!MVHW_DEV_ENABLED (Mdio, MdioIndex) || MdioIndex >=3D Mdio->Controll= erCount) { + DEBUG ((DEBUG_ERROR, "MvPhyDxe: Incorrect Mdio controller assignment f= or PHY#%d", PhyIndex)); + return EFI_INVALID_PARAMETER; + } + /* perform setup common for all PHYs */ PhyDev =3D AllocateZeroPool (sizeof (PHY_DEVICE)); - PhyDev->Addr =3D PhyAddr; + PhyDev->Addr =3D PhySmiAddresses[PhyIndex]; PhyDev->Connection =3D PhyConnection; DEBUG((DEBUG_INFO, "MvPhyDxe: PhyAddr is %d, connection %d\n", - PhyAddr, PhyConnection)); + PhyDev->Addr, PhyConnection)); *OutPhyDev =3D PhyDev; =20 DeviceIds =3D PcdGetPtr (PcdPhyDeviceIds); @@ -377,7 +399,7 @@ MvPhyInit ( if (MvPhyDevices[i].DevId =3D=3D DeviceIds[i]) { ASSERT (MvPhyDevices[i].DevInit !=3D NULL); /* proceed with PHY-specific initialization */ - return MvPhyDevices[i].DevInit(Snp, PhyAddr, PhyDev); + return MvPhyDevices[i].DevInit (Snp, PhyDev); } } =20 @@ -395,8 +417,8 @@ MvPhyStatus ( { UINT32 Data; =20 - Mdio->Read(Mdio, PhyDev->Addr, MII_BMSR, &Data); - Mdio->Read(Mdio, PhyDev->Addr, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); =20 if ((Data & BMSR_LSTATUS) =3D=3D 0) { PhyDev->LinkUp =3D FALSE; diff --git a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h b/Platfor= m/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h index 6bd06c5..0c3d935 100644 --- a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h +++ b/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h @@ -174,7 +174,6 @@ typedef EFI_STATUS (*MV_PHY_DEVICE_INIT) ( IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN UINT32 PhyAddr, IN OUT PHY_DEVICE *PhyDev ); =20 @@ -187,7 +186,6 @@ STATIC EFI_STATUS MvPhyInit1512 ( IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN UINT32 PhyAddr, IN OUT PHY_DEVICE *PhyDev ); =20 diff --git a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf b/Platf= orm/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf index c262ce4..2abd673 100644 --- a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf +++ b/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf @@ -63,8 +63,10 @@ gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled + gMarvellTokenSpaceGuid.PcdPhy2MdioController gMarvellTokenSpaceGuid.PcdPhyDeviceIds + gMarvellTokenSpaceGuid.PcdPhySmiAddresses gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg =20 [Depex] diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 620bd5c..2827976 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -519,14 +519,14 @@ Pp2DxePhyInitialize ( return Status; } =20 - if (Pp2Context->Port.PhyAddr =3D=3D 0xff) { + if (Pp2Context->Port.PhyIndex =3D=3D 0xff) { /* PHY iniitalization not required */ return EFI_SUCCESS; } =20 Status =3D Pp2Context->Phy->Init( Pp2Context->Phy, - Pp2Context->Port.PhyAddr, + Pp2Context->Port.PhyIndex, Pp2Context->Port.PhyInterface, &Pp2Context->PhyDev ); @@ -1147,25 +1147,25 @@ Pp2DxeParsePortPcd ( IN INTN Index ) { - UINT8 *PortIds, *GopIndexes, *PhyConnectionTypes, *AlwaysUp, *Speed, *Ph= yAddresses; + UINT8 *PortIds, *GopIndexes, *PhyConnectionTypes, *AlwaysUp, *Speed, *Ph= yIndexes; =20 PortIds =3D PcdGetPtr (PcdPp2PortIds); GopIndexes =3D PcdGetPtr (PcdPp2GopIndexes); - PhyConnectionTypes =3D PcdGetPtr (PcdPhyConnectionTypes); - PhyAddresses =3D PcdGetPtr (PcdPhySmiAddresses); + PhyConnectionTypes =3D PcdGetPtr (PcdPp2PhyConnectionTypes); + PhyIndexes =3D PcdGetPtr (PcdPp2PhyIndexes); AlwaysUp =3D PcdGetPtr (PcdPp2InterfaceAlwaysUp); Speed =3D PcdGetPtr (PcdPp2InterfaceSpeed); =20 ASSERT (PcdGetSize (PcdPp2GopIndexes) =3D=3D PcdGetSize (PcdPp2PortIds)); - ASSERT (PcdGetSize (PcdPhyConnectionTypes) =3D=3D PcdGetSize (PcdPp2Port= Ids)); + ASSERT (PcdGetSize (PcdPp2PhyConnectionTypes) =3D=3D PcdGetSize (PcdPp2P= ortIds)); ASSERT (PcdGetSize (PcdPp2InterfaceAlwaysUp) =3D=3D PcdGetSize (PcdPp2Po= rtIds)); ASSERT (PcdGetSize (PcdPp2InterfaceSpeed) =3D=3D PcdGetSize (PcdPp2PortI= ds)); - ASSERT (PcdGetSize (PcdPhySmiAddresses) =3D=3D PcdGetSize (PcdPp2PortIds= )); + ASSERT (PcdGetSize (PcdPp2PhyIndexes) =3D=3D PcdGetSize (PcdPp2PortIds)); =20 Pp2Context->Port.Id =3D PortIds[Index]; Pp2Context->Port.GopIndex =3D GopIndexes[Index]; Pp2Context->Port.PhyInterface =3D PhyConnectionTypes[Index]; - Pp2Context->Port.PhyAddr =3D PhyAddresses[Index]; + Pp2Context->Port.PhyIndex =3D PhyIndexes[Index]; Pp2Context->Port.AlwaysUp =3D AlwaysUp[Index]; Pp2Context->Port.Speed =3D Speed[Index]; } diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.h index cde2995..60f40be 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h @@ -327,7 +327,7 @@ struct Pp2DxePort { UINT16 RxRingSize; =20 INT32 PhyInterface; - UINTN PhyAddr; + UINT32 PhyIndex; BOOLEAN Link; BOOLEAN Duplex; BOOLEAN AlwaysUp; diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index 752fcc0..b4568d8 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -71,12 +71,12 @@ gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes - gMarvellTokenSpaceGuid.PcdPhySmiAddresses gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes gMarvellTokenSpaceGuid.PcdPp2Port2Controller gMarvellTokenSpaceGuid.PcdPp2PortIds =20 diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marv= ell/Include/Library/MvHwDescLib.h index 6ad1bc2..9ae03d0 100644 --- a/Platform/Marvell/Include/Library/MvHwDescLib.h +++ b/Platform/Marvell/Include/Library/MvHwDescLib.h @@ -70,6 +70,16 @@ typedef struct { } MVHW_I2C_DESC; =20 // +// MDIO devices description template definition +// +#define MVHW_MAX_MDIO_DEVS 2 + +typedef struct { + UINT8 MdioDevCount; + UINTN MdioBaseAddresses[MVHW_MAX_MDIO_DEVS]; +} MVHW_MDIO_DESC; + +// // NonDiscoverable devices description template definition // #define MVHW_MAX_XHCI_DEVS 4 @@ -168,6 +178,19 @@ MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ } =20 // +// Platform description of MDIO devices +// +#define MVHW_CP0_MDIO_BASE 0xF212A200 +#define MVHW_CP1_MDIO_BASE 0xF412A200 + +#define DECLARE_A7K8K_MDIO_TEMPLATE \ +STATIC \ +MVHW_MDIO_DESC mA7k8kMdioDescTemplate =3D {\ + 2,\ + { MVHW_CP0_MDIO_BASE, MVHW_CP1_MDIO_BASE }\ +} + +// // Platform description of NonDiscoverable devices // #define MVHW_CP0_XHCI0_BASE 0xF2500000 diff --git a/Platform/Marvell/Include/Protocol/Mdio.h b/Platform/Marvell/In= clude/Protocol/Mdio.h index 10acad4..d077a8f 100644 --- a/Platform/Marvell/Include/Protocol/Mdio.h +++ b/Platform/Marvell/Include/Protocol/Mdio.h @@ -35,6 +35,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MDIO_H__ #define __MDIO_H__ =20 +#include + #define MARVELL_MDIO_PROTOCOL_GUID { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0= x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} =20 typedef struct _MARVELL_MDIO_PROTOCOL MARVELL_MDIO_PROTOCOL; @@ -44,6 +46,7 @@ EFI_STATUS (EFIAPI *MARVELL_MDIO_READ) ( IN CONST MARVELL_MDIO_PROTOCOL *This, IN UINT32 PhyAddr, + IN UINT32 MdioIndex, IN UINT32 RegOff, IN UINT32 *Data ); @@ -53,6 +56,7 @@ EFI_STATUS (EFIAPI *MARVELL_MDIO_WRITE) ( IN CONST MARVELL_MDIO_PROTOCOL *This, IN UINT32 PhyAddr, + IN UINT32 MdioIndex, IN UINT32 RegOff, IN UINT32 Data ); @@ -60,6 +64,8 @@ EFI_STATUS struct _MARVELL_MDIO_PROTOCOL { MARVELL_MDIO_READ Read; MARVELL_MDIO_WRITE Write; + UINTN BaseAddresses[MVHW_MAX_MDIO_DEVS]; + UINTN ControllerCount; }; =20 extern EFI_GUID gMarvellMdioProtocolGuid; diff --git a/Platform/Marvell/Include/Protocol/MvPhy.h b/Platform/Marvell/I= nclude/Protocol/MvPhy.h index a91759a..99c75b3 100644 --- a/Platform/Marvell/Include/Protocol/MvPhy.h +++ b/Platform/Marvell/Include/Protocol/MvPhy.h @@ -62,6 +62,7 @@ typedef enum { =20 typedef struct { UINT32 Addr; + UINT8 MdioIndex; BOOLEAN LinkUp; BOOLEAN FullDuplex; BOOLEAN AutoNegotiation; diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index e23607f..0902086 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -160,19 +160,21 @@ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ 0x0 }|VOID*|0x30000207 =20 #MDIO - gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0|UINT64|0x3000043 + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x0 }|VOID*|0x3000043 =20 #PHY - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0 }|VOID*|0x3000044 + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }|VOID*|0x3000027 gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }|VOID*|0x3000095 + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024 gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE|BOOLEAN|0x3000070 =20 #NET - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024 gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x0 }|VOID*|0x3000028 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029 gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ 0x0 }|VOID*|0x3000044 + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0x0 }|VOID*|0x3000045 gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0 }|VOID*|0x300002D gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C =20 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index fa429d1..f0da515 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -126,25 +126,15 @@ PHY Driver configuration MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. Currently only 1518 series PHYs are supported. Following PCDs are required: =20 - - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes - (list of values corresponding to PHY_CONNECTION enum) - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg (boolean - if true, driver waits for autonegotiation on startup) - gMarvellTokenSpaceGuid.PcdPhyDeviceIds (list of values corresponding to MV_PHY_DEVICE_ID enum) + - gMarvellTokenSpaceGuid.PcdPhySmiAddresses + (addresses of PHY devices) + - gMarvellTokenSpaceGuid.PcdPhy2MdioController + (Array specifying, which Mdio controller the PHY is attached to) =20 -PHY_CONNECTION enum type is defined as follows: - - typedef enum { - 0 PHY_CONNECTION_RGMII, - 1 PHY_CONNECTION_RGMII_ID, - 2 PHY_CONNECTION_RGMII_TXID, - 3 PHY_CONNECTION_RGMII_RXID, - 4 PHY_CONNECTION_SGMII, - 5 PHY_CONNECTION_RTBI, - 6 PHY_CONNECTION_XAUI, - 7 PHY_CONNECTION_RXAUI - } PHY_CONNECTION; =20 MV_PHY_DEVICE_ID: =20 @@ -153,11 +143,8 @@ MV_PHY_DEVICE_ID: } MV_PHY_DEVICE_ID; =20 It should be extended when adding support for other PHY models. -Thus in order to set RGMII for 1st PHY and SGMII for 2nd, PCD should be: - - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x4 } =20 -with disabled autonegotiation: +Disable autonegotiation: =20 gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 @@ -171,8 +158,9 @@ MDIO configuration MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ a= nd EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required: =20 - - gMarvellTokenSpaceGuid.PcdMdioBaseAddress - (base address of SMI management register) + - gMarvellTokenSpaceGuid.PcdMdioControllers + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) =20 =20 I2C configuration @@ -249,8 +237,24 @@ are required to operate: - gMarvellTokenSpaceGuid.PcdPp2Port2Controller (Array specifying, to which controller the port belongs to) =20 - - gMarvellTokenSpaceGuid.PcdPhySmiAddresses - (Addresses of PHY devices) + - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes + (Indicates speed of the network interface: + + PHY_RGMII 0x0 + PHY_RGMII_ID 0x1 + PHY_RGMII_TXID 0x2 + PHY_RGMII_RXID 0x3 + PHY_SGMII 0x4 + PHY_RTBI 0x5 + PHY_XAUI 0x6 + PHY_RXAUI 0x7 + PHY_SFI 0x8 ) + + - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes + (Array specifying, to which PHY from + gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none, + e.g. in 10G SFI in-band link detection, 0xFF value must + be specified) =20 - gMarvellTokenSpaceGuid.PcdPp2PortIds (Identificators of PP2 ports) @@ -262,17 +266,13 @@ are required to operate: (Set to 0x1 for always-up interface, 0x0 otherwise) =20 - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed - (Values corresponding to PHY_SPEED enum. - PHY_SPEED is defined as follows: - - typedef enum { - 0 NO_SPEED, - 1 SPEED_10, - 2 SPEED_100, - 3 SPEED_1000, - 4 SPEED_2500, - 5 SPEED_10000 - } PHY_SPEED; + (Indicates speed of the network interface: + + PHY_SPEED_10 0x1 + PHY_SPEED_100 0x2 + PHY_SPEED_1000 0x3 + PHY_SPEED_2500 0x4 + PHY_SPEED_10000 0x5 ) =20 =20 UTMI PHY configuration --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:53:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507459807831289.41363586815316; Sun, 8 Oct 2017 03:50:07 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 89A5E21CF58D0; Sun, 8 Oct 2017 03:46:34 -0700 (PDT) Received: from mail-lf0-x22f.google.com (mail-lf0-x22f.google.com [IPv6:2a00:1450:4010:c07::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B3E4620945B76 for ; Sun, 8 Oct 2017 03:46:32 -0700 (PDT) Received: by mail-lf0-x22f.google.com with SMTP id d10so22155777lfg.11 for ; Sun, 08 Oct 2017 03:49:58 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id y17sm930370lfj.0.2017.10.08.03.49.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 08 Oct 2017 03:49:55 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22f; helo=mail-lf0-x22f.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=d3eIJ3/AExfz3/i1tf/JVwQmBSfLt+F3fFRJamPKkho=; b=BKcUUanjDNCAlmP1WbfGGfFC9MUAQoByVT1Lz/zV4EhS+8obZeZuqD6qJ3ad+NfrAo 84APk1wHGvVQEwsnO8lS5aZB1ITZmogIcdK/kAjP2HHpdOV3OgOGVleNKG9U73N/ASu4 D3fdUMKuJVn0iOa5vU7TN4/aKQTjGhXbDwu+pzg6+/3FzYzi6IAU3e/8HLt4ugB1cX1h 7JGbe+zik2Ni1hB4fY51d8n9kVbqxEWb8IfGNXiO+eiStzwuo1UJRInCzCp2AMJuDTl/ TTxjBis40ZFKA7wwv7trRRZ6X5C6UZ3uYi4xgC+Z4wiC7BjwezHN3NUVGf6/SiGXOoYM xQOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=d3eIJ3/AExfz3/i1tf/JVwQmBSfLt+F3fFRJamPKkho=; b=E/AhI59PUiPK5eYGLji20uVBXOUm5BDbK8pohLDzk8OdvK36AsZgNN6XgwriZ2D+la 9ijOz91uUDrzW4lYbRcLRom0EL67qnk7nbyckaabJ26fTUZ7AZtt+cFbuGK2CubjzMNK qpjaalPsujUga+D45Zch1cOMU0PuqlT9YgRizOQaMSu/Vvel05idR+agUiVII62fo4zR B0X8rvtV+fmH9HXqcJYHN2gkmrJcWWWml1SoP5qCB6tqChqyRAOwNGJ0Ow1qfI1cO9a7 UOJ5Fj+CS2ht5cRUk+GbQGGrdcYOCC+YoimgtSGXssJqWvf1xCzb2w4zmV+SpoO3QLGf 6l4A== X-Gm-Message-State: AMCzsaWGfoHTFtTf6sLCi3XXDe5vD6OHVhP9FRgEBWDIV4ZFLACFr6r+ wCG5Giw1WEncUqy/uKCVpILugG7zfxA= X-Google-Smtp-Source: AOwi7QBCGjVHuil5te6XkZWJsOggeGuctqLW8i9OWFx9ZmBsce9mDRh4ya8kKEM9I2mr1cCYX/UqUQ== X-Received: by 10.25.56.26 with SMTP id f26mr856563lfa.17.1507459796477; Sun, 08 Oct 2017 03:49:56 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 8 Oct 2017 12:56:52 +0200 Message-Id: <1507460212-10323-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507460212-10323-1-git-send-email-mw@semihalf.com> References: <1507460212-10323-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 5/5] Platform/Marvell/Armada: Remove ParsePcdLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Current PCD handling in libraries and drivers allow to get rid of this code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada.dsc.inc | 1 - Platform/Marvell/Include/Library/ParsePcdLib.h | 46 ---- Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.c | 228 ---------------= ----- Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.inf | 50 ----- 4 files changed, 325 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 7258017..89fb7e7 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -33,7 +33,6 @@ ArmPlatformLib|Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0L= ib.inf ComPhyLib|Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf MppLib|Platform/Marvell/Library/MppLib/MppLib.inf - ParsePcdLib|Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.inf UtmiPhyLib|Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf =20 DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf diff --git a/Platform/Marvell/Include/Library/ParsePcdLib.h b/Platform/Marv= ell/Include/Library/ParsePcdLib.h deleted file mode 100644 index a255685..0000000 --- a/Platform/Marvell/Include/Library/ParsePcdLib.h +++ /dev/null @@ -1,46 +0,0 @@ -/*************************************************************************= ******* -Copyright (C) 2016 Marvell International Ltd. - -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute a= nd/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modific= ation, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -* Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -**************************************************************************= *****/ - -#ifndef __PARSEPCDLIB_H__ -#define __PARSEPCDLIB_H__ - -EFI_STATUS -ParsePcdString ( - IN CHAR16 *PcdString, - IN UINT8 Count, - OUT UINTN *ValueTable, - OUT CHAR16 **StrTable - ); - -#endif diff --git a/Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.c b/Platform/= Marvell/Library/ParsePcdLib/ParsePcdLib.c deleted file mode 100644 index 9a4be8e..0000000 --- a/Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.c +++ /dev/null @@ -1,228 +0,0 @@ -/*************************************************************************= ******* -Copyright (C) 2016 Marvell International Ltd. - -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute a= nd/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modific= ation, -are permitted provided that the following conditions are met: - -* Redistributions of source code must Retain the above copyright notice, - this list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -* Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -**************************************************************************= *****/ -#define CHAR_NULL 0x0000 - -#include -#include -#include -#include - -STATIC -CHAR16 -CharToUpper ( - IN CHAR16 Char - ) -{ - - if (Char >=3D L'a' && Char <=3D L'z') { - return (CHAR16) (Char - (L'a' - L'A')); - } - - return Char; -} - -STATIC -BOOLEAN -IsDecimalDigitChar ( - IN CHAR16 Char - ) -{ - - return (BOOLEAN) (Char >=3D L'0' && Char <=3D L'9'); -} - - -STATIC -UINTN -HexCharToUintn ( - IN CHAR16 Char - ) -{ - if (IsDecimalDigitChar (Char)) { - return Char - L'0'; - } - - return (UINTN) (10 + CharToUpper (Char) - L'A'); -} - -STATIC -BOOLEAN -IsHexDigitCharacter ( - CHAR16 Char - ) -{ - - return (BOOLEAN) ((Char >=3D L'0' && Char <=3D L'9') || (Char >=3D L'A' = && - Char <=3D L'F') || (Char >=3D L'a' && Char <=3D L'f')); -} - -STATIC -UINTN -HexStrToUintn ( - CHAR16 *String - ) -{ - UINTN Result =3D 0; - - if (String =3D=3D NULL || StrSize(String) =3D=3D 0) { - return (UINTN)(-1); - } - - // Ignore spaces and tabs - while ((*String =3D=3D L' ') || (*String =3D=3D L'\t')) { - String++; - } - - // Ignore leading zeros after spaces - while (*String =3D=3D L'0') { - String++; - } - - if (CharToUpper (*String) !=3D L'X') { - return (UINTN)(-1); - } - - // Skip 'x' - String++; - - while (IsHexDigitCharacter (*String)) { - Result <<=3D 4; - Result +=3D HexCharToUintn (*String); - String++; - } - - return (UINTN) Result; -} - -STATIC -UINTN -DecimalStrToUintn ( - CHAR16 *String - ) -{ - UINTN Result =3D 0; - - while (IsDecimalDigitChar (*String)) { - Result =3D 10 * Result + (*String - L'0'); - String++; - } - - return Result; -} - -STATIC -UINTN -StrToUintn ( - CHAR16 *String - ) -{ - CHAR16 *Walker; - - // Chop off leading spaces - for (Walker =3D String; Walker !=3D NULL && *Walker !=3D CHAR_NULL && *W= alker =3D=3D L' '; Walker++); - - if (StrnCmp(Walker, L"0x", 2) =3D=3D 0 || StrnCmp(Walker, L"0X", 2) =3D= =3D 0) { - return HexStrToUintn (Walker); - } else { - return DecimalStrToUintn (Walker); - } -} - -EFI_STATUS -ParsePcdString ( - IN CHAR16 *PcdString, - IN UINT8 Count, - OUT UINTN *ValueTable, - OUT CHAR16 **StrTable - ) -{ - BOOLEAN ValueFlag =3D FALSE; - CHAR16 *Walker; - UINTN i, Tmp =3D 0; - - if (ValueTable !=3D NULL) { - ValueFlag =3D TRUE; - } - - // Set pointer at the end of PCD string - Walker =3D PcdString + StrLen (PcdString); - for (i =3D 0; i < Count; i++) { - while ((--Walker) >=3D PcdString) { - if (*Walker =3D=3D L';') { - // Cut off parsed chunk from PCD string by replacing ';' with - // null-terminator - *Walker =3D '\0'; - if (ValueFlag) { - Tmp =3D StrToUintn ((Walker + 1)); - if ((UINTN)(-1) =3D=3D Tmp) { - return EFI_INVALID_PARAMETER; - } - // Entry is parsed from the end to the beginning - // so fill table in the same manner - ValueTable[Count - (i + 1)] =3D Tmp; - } else { - StrTable[Count - (i + 1)] =3D Walker + 1; - } - Walker--; - break; - } - if (Walker =3D=3D PcdString) { - if (ValueFlag) { - Tmp =3D StrToUintn ((Walker)); - if (Tmp =3D=3D (UINTN)(-1)) { - return EFI_INVALID_PARAMETER; - } - } - // Last device's entry should be added to the table here. - // If not, return error - if (i !=3D (Count - 1)) { - DEBUG((DEBUG_ERROR, "ParsePcdLib: Please set PCD value for every= " - "device\n")); - return EFI_INVALID_PARAMETER; - } - // We parse from the end to the beginning - // so fill table in the same manner - if (ValueFlag) { - ValueTable[Count - (i + 1)] =3D Tmp; - } else { - StrTable[Count - (i + 1)] =3D Walker; - } - // End both loops - return EFI_SUCCESS; - } - } - } - - return EFI_SUCCESS; -} diff --git a/Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.inf b/Platfor= m/Marvell/Library/ParsePcdLib/ParsePcdLib.inf deleted file mode 100644 index b4db621..0000000 --- a/Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.inf +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright (C) 2016 Marvell International Ltd. -# -# Marvell BSD License Option -# -# If you received this File from Marvell, you may opt to use, redistribute= and/or -# modify this File under the following licensing terms. -# Redistribution and use in source and binary forms, with or without modif= ication, -# are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# * Neither the name of Marvell nor the names of its contributors may be -# used to endorse or promote products derived from this software without -# specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS = IS" AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IM= PLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIA= BLE FOR -# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL D= AMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVI= CES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON -# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF= THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D ParsePcdLib - FILE_GUID =3D 698d85a0-a952-453e-b8a4-1d6ea338a38e - MODULE_TYPE =3D BASE - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D ParsePcdLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - -[LibraryClasses] - ArmLib - DebugLib - -[Sources.common] - ParsePcdLib.c --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel