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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id y17sm930370lfj.0.2017.10.08.03.49.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 08 Oct 2017 03:49:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::229; helo=mail-lf0-x229.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qp3VpATz0S8pFa0uG6qFN3IDOYT82eism9o8oDMCXbg=; b=XHka3KRGXxxtcl7myhDnrnkP8Y5FETqBRZKmJ0aB8mPgFhjELXAHSJw5L7xaz1ikcQ p/ZPnCuHWGz47U7kCcv1ON/UJeXMKfPVuHJWgjSGEPPjYN5qClTkow0VqoeZlBiHATse hxI+6mbJmVVvZq7wpN5RkwzOxTwvD+LXn4bGy9yfQvYiNaAk+ubfd2KwCFz7yxCUaPQP 4MUh4WAUTHyZtwJ1eAXraonfKBGeKcmq/6imlll8zd2W6X3TyzZXAxDIwaeNaTBkcLae 6/iBMTHF+8d6fkA4YIUC86xLEmRMX+Vs4BI3TKzAavi5rtzk6E7qSxXUhC3e590HhBwd 7ajQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qp3VpATz0S8pFa0uG6qFN3IDOYT82eism9o8oDMCXbg=; b=mF9l0z5Aapa1FzY8lrgsz0qbSmHpzATTZTgvgv+CgtZEEOjX4moDojGzEQIE8aYKoq XjByvTw1oW50kjchOw2dYKEGvnedbq3N4pAemGkhVGqqI3MkyvcCL+ci8wSrq9hDW6f/ zd7u8ICdmdJm93sUypa78aMqg7oVStfQ1FyhPvqqjttFhaz4CiWayD3bTrWzxLIyhaMf BMREiTYLg4BIX7ecWTya6Y2FL3A3R4fEGBRHssghQS7Vz9UOxAEb5hyRGDwyXVru4Dcx CKpNKWsUyGGD/7W67jfiOiA2gb9PD3e3gtRwGFN6vyJk1ICritKdJb8M4quXF81xm4Rp q5kQ== X-Gm-Message-State: AMCzsaVZL16KwiWTGir4nkg/36hPeiokL/s/KSu+62Hn+vAmzLUaH7jH 8EsraCnpv+o2lJbr/tN9u+8bK6CvxzI= X-Google-Smtp-Source: AOwi7QDJTqpwsXWAQ4Ec5NHFAododPe1dRgMGXvuhf8hHkeP0FtH9DkBGEA/zB5aE/GxiXJpxhUoHg== X-Received: by 10.25.165.212 with SMTP id o203mr945193lfe.204.1507459792481; Sun, 08 Oct 2017 03:49:52 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 8 Oct 2017 12:56:49 +0200 Message-Id: <1507460212-10323-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507460212-10323-1-git-send-email-mw@semihalf.com> References: <1507460212-10323-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 2/5] Marvell/Drivers: MvI2cDxe: Move devices description to MvHwDescLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces I2c description, using the new structures and template in MvHwDescLib. This change enables more flexible addition of multiple I2c controllers and also allows for removal of string PCD parsing. Update Armada 70x0 DB description and PortingGuide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada70x0.dsc | 2 +- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 42 +++++++++++-------= -- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 3 +- Platform/Marvell/Include/Library/MvHwDescLib.h | 25 ++++++++++++ Platform/Marvell/Marvell.dec | 2 +- Silicon/Marvell/Documentation/PortingGuide.txt | 4 +- 6 files changed, 54 insertions(+), 24 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index dae9715..c11a973 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -78,7 +78,7 @@ # I2C gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60 } gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 } gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 } gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index fa79ebc..d85ee0b 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -42,12 +42,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include #include #include -#include #include +#include #include =20 #include "MvI2cDxe.h" =20 +DECLARE_A7K8K_I2C_TEMPLATE; + STATIC MV_I2C_BAUD_RATE baud_rate; =20 STATIC MV_I2C_DEVICE_PATH MvI2cDevicePathProtocol =3D { @@ -172,35 +174,39 @@ MvI2cInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { + MVHW_I2C_DESC *Desc =3D &mA7k8kI2cDescTemplate; + UINT8 *I2cDeviceTable, Index; EFI_STATUS Status; - UINT32 BusCount; - EFI_PHYSICAL_ADDRESS I2cBaseAddresses[PcdGet32 (PcdI2cBusCount)]; - INTN i; =20 - BusCount =3D PcdGet32 (PcdI2cBusCount); - if (BusCount =3D=3D 0) - return EFI_SUCCESS; + /* Obtain table with enabled I2c devices */ + I2cDeviceTable =3D (UINT8 *)PcdGetPtr (PcdI2cControllersEnabled); + if (I2cDeviceTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Missing PcdI2cControllersEnabled\n")); + return EFI_INVALID_PARAMETER; + } =20 - Status =3D ParsePcdString ( - (CHAR16 *) PcdGetPtr (PcdI2cBaseAddresses), - BusCount, - I2cBaseAddresses, - NULL - ); - if (EFI_ERROR(Status)) - return Status; + if (PcdGetSize (PcdI2cControllersEnabled) > MVHW_MAX_I2C_DEVS) { + DEBUG ((DEBUG_ERROR, "Wrong PcdI2cControllersEnabled format\n")); + return EFI_INVALID_PARAMETER; + } + + /* Initialize enabled chips */ + for (Index =3D 0; Index < PcdGetSize (PcdI2cControllersEnabled); Index++= ) { + if (!MVHW_DEV_ENABLED (I2c, Index)) { + DEBUG ((DEBUG_ERROR, "Skip I2c chip %d\n", Index)); + continue; + } =20 - for (i =3D 0; i < BusCount; i++) { Status =3D MvI2cInitialiseController( ImageHandle, SystemTable, - I2cBaseAddresses[i] + Desc->I2cBaseAddresses[Index] ); if (EFI_ERROR(Status)) return Status; } =20 - return Status; + return EFI_SUCCESS; } =20 STATIC diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf b/Platform/= Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf index 16374ef..80655f1 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf @@ -55,7 +55,6 @@ UefiLib UefiDriverEntryPoint UefiBootServicesTableLib - ParsePcdLib =20 [Protocols] gEfiI2cMasterProtocolGuid @@ -66,7 +65,7 @@ [Pcd] gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses gMarvellTokenSpaceGuid.PcdI2cSlaveBuses - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled gMarvellTokenSpaceGuid.PcdI2cClockFrequency gMarvellTokenSpaceGuid.PcdI2cBaudRate gMarvellTokenSpaceGuid.PcdI2cBusCount diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marv= ell/Include/Library/MvHwDescLib.h index 6a86865..e029b50 100644 --- a/Platform/Marvell/Include/Library/MvHwDescLib.h +++ b/Platform/Marvell/Include/Library/MvHwDescLib.h @@ -60,6 +60,16 @@ typedef struct { } MVHW_COMPHY_DESC; =20 // +// I2C devices description template definition +// +#define MVHW_MAX_I2C_DEVS 4 + +typedef struct { + UINT8 I2cDevCount; + UINTN I2cBaseAddresses[MVHW_MAX_I2C_DEVS]; +} MVHW_I2C_DESC; + +// // NonDiscoverable devices description template definition // #define MVHW_MAX_XHCI_DEVS 4 @@ -130,6 +140,21 @@ MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate =3D {\ } =20 // +// Platform description of I2C devices +// +#define MVHW_CP0_I2C0_BASE 0xF2701000 +#define MVHW_CP0_I2C1_BASE 0xF2701100 +#define MVHW_CP1_I2C0_BASE 0xF4701000 +#define MVHW_CP1_I2C1_BASE 0xF4701100 + +#define DECLARE_A7K8K_I2C_TEMPLATE \ +STATIC \ +MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ + 4,\ + { MVHW_CP0_I2C0_BASE, MVHW_CP0_I2C1_BASE, MVHW_CP1_I2C0_BASE, MVHW_CP1_I= 2C1_BASE }\ +} + +// // Platform description of NonDiscoverable devices // #define MVHW_CP0_XHCI0_BASE 0xF2500000 diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index fc00f1a..d2ab0a9 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -113,7 +113,7 @@ gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }|VOID*|0x3000184 gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x0 }|VOID*|0x3000050 gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0 }|VOID*|0x3000185 - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|{ 0x0 }|VOID*|0x3000047 + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }|VOID*|0x3000047 gMarvellTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x3000048 gMarvellTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x3000049 gMarvellTokenSpaceGuid.PcdI2cBusCount|0|UINT32|0x3000183 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 25cb66b..b2bb595 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -189,8 +189,8 @@ In order to enable driver on a new platform, following = steps need to be taken: (buses to which accoring slaves are attached) - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 (number of SoC's I2C buses) - - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" - (base addresses of I2C controller buses) + - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 } + (array with used controllers) - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 (I2C host controller clock frequency) - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel