From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507568049901396.7695593519484; Mon, 9 Oct 2017 09:54:09 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 64A5B21EA15C7; Mon, 9 Oct 2017 09:50:41 -0700 (PDT) Received: from mail-lf0-x22f.google.com (mail-lf0-x22f.google.com [IPv6:2a00:1450:4010:c07::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 65A5821EA15B9 for ; Mon, 9 Oct 2017 09:50:39 -0700 (PDT) Received: by mail-lf0-x22f.google.com with SMTP id c82so24208897lfc.6 for ; Mon, 09 Oct 2017 09:54:06 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:04 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22f; helo=mail-lf0-x22f.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KfmfySvtY88h3B/oIZwQiy50PTS1MYnW3iqTnqzuYtY=; b=uxpbePfHn1MbnSABq1MA7tMifZZFEQOVzKxvhX8isvyu5HmYsk2e07g6EVr68k1sNl Do38lCkyN0gPqQdWePzlumEhIQqg6Pilg1zc8kQG6Y2N3vQ1E7nrw46SYJlfP5cMbH3g +z+M/mlW5YPuUVKwbNoSE67FhKZ3ze+f5y8ztxiZWvF08vC/IAE4rQDIOTauYB5iVirX cMsq+FZdOEV1lseMxDZ9Kd7knujwFKLe+c8yCoozXqARBmr7/pZiPSKm8wzv62RQOxLY UdHG8eL59q000Ae4XBYfPZdH51QNwmZuPUvHb3EG0CLqe/tna+hZFKbPn1MEDwvd/X4C JzPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KfmfySvtY88h3B/oIZwQiy50PTS1MYnW3iqTnqzuYtY=; b=Zr2SQrSQO/txDJHxnq4KpcJDheYs2af5sa3vScG2QSzYB9+RKBCcxY9qWyIeobxu+d YG5ppj5h35TtDNC8ON6PG9pL1CkgCNv76J8b86f+f40Q18n/iTGE060EBJBZpQmtuENR 8fQ0UeZuQ6sYGavPjHXCcRWMkJztK6gpUe9hwZ4cZlNnN9IUz1KV7Zx1oEPfOxg2jD/t yMNzG9+WJknkL4dNcc1AGSfugwsBoD6sjeYvQfIiUd9WBBtNQ+t6BB+pVBanx30h6EMm 6Ao1glk3hN1kBTAp26YFi/JcCeqGIjQj5LVeJ2fCB+jGethtx9fh027dTYtoB6039jp5 9Zjg== X-Gm-Message-State: AMCzsaUT2s4G3VVZRFnZKAcj6kxUHYCoA+eNNlETdeQ2zPUaEzmzcV8N 0phnoqZRQRtmRE9HJD29ee/SZPq2gBU= X-Google-Smtp-Source: AOwi7QCi9ytZKxiXWCTtcl0Z92FoXP6dQGcpW175qUJZUMtdG8XRKBudXpa54nL0m9NyBkrGCvVMSQ== X-Received: by 10.46.85.145 with SMTP id g17mr4667817lje.84.1507568044711; Mon, 09 Oct 2017 09:54:04 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:50 +0200 Message-Id: <1507568462-28775-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In order to enable modification of dynamic PCD's for the libraries and DXE drivers, this patch introduces new driver. It is executed prior to other drivers. Mpp, ComPhy and Utmi libraries initialization were moved from PrePi stage to DXE. To force the correct driver dispatch sequence, introduce a protocol GUID and install the protocol as a NULL protocol when PlatInitDxe executes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Signed-off-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada.dsc.inc | 3 ++ Platform/Marvell/Armada/Armada70x0.fdf | 5 +++ Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c | 44 +++++++= +++++++++++++ Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf | 44 +++++++= +++++++++++++ Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 11 ----- Platform/Marvell/Marvell.dec | 5 +++ 6 files changed, 101 insertions(+), 11 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 89fb7e7..417bb0c 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -378,6 +378,9 @@ ArmPkg/Drivers/TimerDxe/TimerDxe.inf ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf =20 + # Platform Initialization + Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf + # Platform drivers Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index c861e78..763d76a 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -89,6 +89,11 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1b= 30c =20 INF MdeModulePkg/Core/Dxe/DxeMain.inf =20 + # + # Platform Initialization + # + INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf + # PI DXE Drivers producing Architectural Protocols (EFI Services) INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c b/Pl= atform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c new file mode 100644 index 0000000..919454b --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c @@ -0,0 +1,44 @@ +/** @file + Copyright (C) Marvell International Ltd. and its affiliates + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +ArmadaPlatInitDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_ERROR, "\nArmada Platform Init\n\n")); + + Status =3D gBS->InstallProtocolInterface (&ImageHandle, + &gMarvellPlatformInitCompleteProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR (Status); + + MvComPhyInit (); + UtmiPhyInit (); + MppInitialize (); + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf b/= Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf new file mode 100644 index 0000000..29abcaf --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -0,0 +1,44 @@ +#/* @file +# Copyright (C) Marvell International Ltd. and its affiliates +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D PlatInitDxe + FILE_GUID =3D 8c66f65b-08a6-4c91-b993-ff81e0adf818 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D ArmadaPlatInitDxeEntryPoint + +[Sources] + PlatInitDxe.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/Marvell/Marvell.dec + +[LibraryClasses] + ComPhyLib + DebugLib + MppLib + PcdLib + TimerLib + UefiDriverEntryPoint + UtmiPhyLib + +[Protocols] + gMarvellPlatformInitCompleteProtocolGuid ## PRODUCES + +[Depex] + TRUE diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c = b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c index 0ed310f..968d28f 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c @@ -15,12 +15,8 @@ =20 #include #include -#include -#include -#include #include =20 - ARM_CORE_INFO mArmada7040MpCoreInfoTable[] =3D { { // Cluster 0, Core 0 @@ -90,13 +86,6 @@ ArmPlatformInitialize ( IN UINTN MpId ) { - if (!ArmPlatformIsPrimaryCore (MpId)) { - return RETURN_SUCCESS; - } - - MvComPhyInit (); - UtmiPhyInit (); - MppInitialize (); return RETURN_SUCCESS; } =20 diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 0902086..e7d7c2c 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -56,6 +56,11 @@ gShellFUpdateHiiGuid =3D { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4= a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } } gShellSfHiiGuid =3D { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x= 0f, 0x6d, 0x58, 0x81, 0x39 } } =20 +[Protocols] + # installed as a protocol by PlatInitDxe to force ordering between DXE d= rivers + # that depend on the lowlevel platform initialization having been comple= ted + gMarvellPlatformInitCompleteProtocolGuid =3D { 0x465b8cf7, 0x016f, 0x4ba= 6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } } + [PcdsFixedAtBuild.common] #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507568052591917.4945068615796; Mon, 9 Oct 2017 09:54:12 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A305421EA15CD; Mon, 9 Oct 2017 09:50:42 -0700 (PDT) Received: from mail-lf0-x234.google.com (mail-lf0-x234.google.com [IPv6:2a00:1450:4010:c07::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AA64F21EA15BA for ; Mon, 9 Oct 2017 09:50:40 -0700 (PDT) Received: by mail-lf0-x234.google.com with SMTP id d10so25714495lfg.11 for ; Mon, 09 Oct 2017 09:54:07 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:05 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::234; helo=mail-lf0-x234.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZdAtkaiyGucONKiY51w06jVCLe0xXbqUDwOasWQ8S2s=; b=csHJ4ela6GVDqlwhoF4IUkHY7Fj85O+snYiPvCN2eHEiC9fAsK2pFWPmJExHkG7Brc rXhJJ5hw3qwFsXfWqYdfYRxkWo613fRN/15eeV0CJAKBHyXu7F+PE9rw9OD8JjEvBh67 m0MeVxetcqaabJ+mu6w7SgawCdgbc1u3NaJzdZs/LCAD48/C6Xo85vnmmwQrYmTl5yGS eO1zT7d8ddc9TcRzRyVA2uVbik1Bal8l5xi+OqtKfkGTKVPd1Lti5rAjThe/wKOpCYqF XpZ2pYwqFu1QrNvl5aoBxFM3NOrRkjfWLPdKIaPSdaPBnX2l+2aPuRKM2uu1oZBvPp+g /HPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZdAtkaiyGucONKiY51w06jVCLe0xXbqUDwOasWQ8S2s=; b=EngAmZIKBrUy9DYJTwryKCEvDWN09SRC6R8UeiAWFllOY7YEgRQ6Pd6WoxNNdFb481 BNdJpw0VjpZf93sjdCakzvJydmF+MTDQl+5hra9tgiEiovZbY5J8LphW1g+Pg6G7E5+S aMgnGQ2ilbRVsiRxMUutvA+YqXbPsiT8vrCfxX1e59qsMquOxpvm8cFk95hp34N2ymh+ Hs5m2trlLZYPNwjyJulbFfU2MMDDzxcs/+HeyxqnsN406/nyz3wmolESyiLn3oWjwMcQ H/Tt6Jo5pCWR/bc98XyCg0HsXw+jX2RCEz4GjDYgzRuJDFojGRDtgIwjoxIYljhdaFs1 hEBg== X-Gm-Message-State: AMCzsaXe5hK8FNndqkq/TbMhLfo20zJCxQuQCnMxcSrlHHX3UHMUk1AQ O7m9GT4jlYNUvh2qPd41ViIfWpFRgdA= X-Google-Smtp-Source: AOwi7QAotEZ9iEAOsWEtnp86xjOW2cSnKXL15BlW/InAfhjfAmGI7+pe5ounEmY4weLOlKLd9uNBLw== X-Received: by 10.46.21.84 with SMTP id 20mr4604578ljv.168.1507568046034; Mon, 09 Oct 2017 09:54:06 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:51 +0200 Message-Id: <1507568462-28775-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 02/13] Marvell/Armada: Switch to dynamic PCDs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel For full functionality, including HII forms wired to non-volatile UEFI variables, we need dynamic PCDs as well. So let's enable those. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 10 +++++++--- Platform/Marvell/Armada/Armada70x0.fdf | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 417bb0c..433892e 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -67,8 +67,7 @@ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf =20 - # Assume everything is fixed at build. do not use runtime PCD feature - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf =20 BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf =20 @@ -150,6 +149,7 @@ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre= PiHobListPointerLib.inf PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf =20 [LibraryClasses.common.SEC, LibraryClasses.common.PEIM] MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf @@ -368,10 +368,14 @@ # DXE MdeModulePkg/Core/Dxe/DxeMain.inf { - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf } =20 + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + # Architectural Protocols DXE ArmPkg/Drivers/CpuDxe/CpuDxe.inf ArmPkg/Drivers/ArmGic/ArmGicDxe.inf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index 763d76a..b3d1c60 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -95,6 +95,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1b3= 0c INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf =20 # PI DXE Drivers producing Architectural Protocols (EFI Services) + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507568054923477.8250521825371; Mon, 9 Oct 2017 09:54:14 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E071F21EA15CC; Mon, 9 Oct 2017 09:50:43 -0700 (PDT) Received: from mail-lf0-x22f.google.com (mail-lf0-x22f.google.com [IPv6:2a00:1450:4010:c07::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C5BBA21EA15C5 for ; Mon, 9 Oct 2017 09:50:41 -0700 (PDT) Received: by mail-lf0-x22f.google.com with SMTP id g70so12474826lfl.3 for ; Mon, 09 Oct 2017 09:54:09 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:06 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22f; helo=mail-lf0-x22f.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3wQ354SZgnRk23NoVJnpxfDn/hM5ledE6OyClaFyI3Q=; b=yiYWiM4UV/YQuATgSCwWurb+axsZUNMEWOyNVzgYZ8+QqL+O084i92YMu2+Woj0Z+8 6M58u998tehrWFoN/PtLV83SE/dFvK8dXd37uDIDaZIPCRVyEH5Cad2ERD/YSPa5TEND 9nZw/l9Q1pTiF0tzIEWsFHS0L9jtnKRHreGiPEZcjIHhuRhTvOrRGjyi8f2fYY3qLl4q LUr0AgW/RqJKsvB0RY63+qll8zN7Q348si3JAdlaxDRM3e9fuWR4f11srRj0emmFXeWf ZAmUy/5V5hEN7bLLhBvwbObUl+PYI9o1N3S3jJ+Xq1JhDfP4belRv4x4Qdzv0cTFdj+a XhTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3wQ354SZgnRk23NoVJnpxfDn/hM5ledE6OyClaFyI3Q=; b=iFjKk2R//rBy7t3PmMVgpekVjzZIv/tGfe3O0bvgvQE84cZ4Bo6j1fsyio4v3SCPZU W8nO9NYBAfhf2PrNSRSHNFoDQ8DSRPU3CrcfiifNhxolu6kEsF8GONrMUx4Uqk9Q1/fb Y4ivVHjMIEqAHXcY0A1s4oiXg+7Z0FK7CteH9pt57GlawbeydhhOXd7c1l/cx1DpY5xG Oz3EhGAZAiU+ZdgF20BrvV/4T8Znsn89gghYbUTjF9VZvjFFkhU+hqovv5D1v/J85VxF Km7F+Zsi59xTWUqVQ4ytI9icDNSsrgwIEUFhVhBbXXhdn55G8BRLIk2jqjQE2GJOEWiB PQog== X-Gm-Message-State: AMCzsaVDK6250LiKvChJMaWCptxblU8w0PI8SXuDa8cPJXX/62Xt3Vxr pN/sLasFZuQjkA0Pn53zIFHfWWMVhCo= X-Google-Smtp-Source: AOwi7QA0ttJEHWm/ZXhNy+UveQOa7CWP6U9AtW7HYuseABtVcrVZyDKPXcNjtONPNQH9zXfp8mNn/A== X-Received: by 10.46.41.7 with SMTP id u7mr4481956lje.107.1507568047247; Mon, 09 Oct 2017 09:54:07 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:52 +0200 Message-Id: <1507568462-28775-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 03/13] Marvell/Armada: Armada70x0Lib: Terminate call stack list at entry X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel To avoid dereferencing junk when walking the call stack in exception handlers (which may prevent us from getting a full backtrace), set the frame pointer to 0x0 when first entering UEFI. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S = | 1 + 1 file changed, 1 insertion(+) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatf= ormHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlat= formHelper.S index 9265636..72f8cfc 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelp= er.S +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelp= er.S @@ -16,6 +16,7 @@ #include =20 ASM_FUNC(ArmPlatformPeiBootAction) + mov x29, xzr ret =20 //UINTN --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507568057795236.431681739615; Mon, 9 Oct 2017 09:54:17 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2967921EA15DB; Mon, 9 Oct 2017 09:50:45 -0700 (PDT) Received: from mail-lf0-x22c.google.com (mail-lf0-x22c.google.com [IPv6:2a00:1450:4010:c07::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 087FB21EA15CC for ; Mon, 9 Oct 2017 09:50:43 -0700 (PDT) Received: by mail-lf0-x22c.google.com with SMTP id 90so19857290lfs.13 for ; Mon, 09 Oct 2017 09:54:10 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:07 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22c; helo=mail-lf0-x22c.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=O/et75SsDvULATOnbKgNnRKp0FPqFVB1FaxdMoiwZh4=; b=PBT1rN40ljSTgxnq4iwO2ae6VKbqsZUhI+wNffcSsnQkDEukLPZ61d4RJsuWNAB2d8 wcrOqA3HiE3zWKL5MJd8TF/HYb5a+eW1vgpItvV74sLpQYnskuNPROGfrdyCI8VXc4fK pvEeHvqWqbmb88qamXHZGX0zwjyj9VTRO80CdLAkaKDEl/Skhmxz+Pgwnccs0fD3RK10 KoZgZQ3QM+uAWN7/AVhXQxVscdWj+O6R7wBNdSqkQklX6Udd1DOe5wYEPV7sZbYisruw mnmHuIhowygWed+w9xmuu4SbAJJ0Y6+Gei7Jua6zuVWEjuD7yOZBiMVNqLOeorE4gZvv kUMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=O/et75SsDvULATOnbKgNnRKp0FPqFVB1FaxdMoiwZh4=; b=iHkuc0QjjRmOE8O4PSNtTbp+xk+Sx0Fn+4wb6KJ39nbC3ZsuK8iUUaI7YXNcA/KBx7 W3N01x4gbY0me3RqbL2G4zsxxvJstMCLgR4IcoWvA7xhykXMezkPblyoevKjWL0USLua zi893GLrcIBJLZDYNGKWINhXomIM8RtxXVe0RP3JqB2+G4B/QS2+md9hZ/m6RVC6dRwi eVwoasGjoPCRjpb+sXAAVcSAMxH7UVmJLl1NzfWaopPeVevgf0GOwDDj8sgqDi07sp6/ 5sLgsQFNc+sm2t3sI3TP+OTEovFPV5omeHi7MJmCmlPd/ImEW79qq5OEqclkc2dClr52 sxrg== X-Gm-Message-State: AMCzsaVY1oYg6bgO7E8dEnapWL/xCdde0v31xDxEa5lnxegN7TlCqjD3 u2OhKu6kfDFcB3XbmBmeMVlGkRcl7bE= X-Google-Smtp-Source: AOwi7QDN8hVR4EpDJRQ7tnB8hq68iEcB82NXgTom0alMHuIWP1m/OwX7Z/8QvwnR9K1BmOmZy8KLgQ== X-Received: by 10.46.67.156 with SMTP id z28mr5783804lje.124.1507568048447; Mon, 09 Oct 2017 09:54:08 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:53 +0200 Message-Id: <1507568462-28775-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 04/13] Marvell/Armada: Armada70x0Lib: Clean FV in the D-cache before boot X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel To prevent cache coherency issues when chainloading via U-Boot, clean and invalidate the FV image in the caches before re-enabling the MMU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S = | 15 +++++++++++++++ Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf = | 3 +++ 2 files changed, 18 insertions(+) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatf= ormHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlat= formHelper.S index 72f8cfc..7544361 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelp= er.S +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelp= er.S @@ -17,6 +17,21 @@ =20 ASM_FUNC(ArmPlatformPeiBootAction) mov x29, xzr + + MOV32 (x0, FixedPcdGet64 (PcdFvBaseAddress)) + MOV32 (x3, FixedPcdGet32 (PcdFvSize)) + add x3, x3, x0 + + mrs x1, ctr_el0 + and x1, x1, #0xf // Dminline + mov x2, #4 + lsl x1, x2, x1 // by-VA stride for D-cache maintenance + +0:dc civac, x0 + add x0, x0, x1 + cmp x0, x3 + b.lt 0b + ret =20 //UINTN diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.in= f b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 2e198c3..6966683 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -67,5 +67,8 @@ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore =20 + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdFvSize + [Ppis] gArmMpCoreInfoPpiGuid --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507568061013114.19459771526033; Mon, 9 Oct 2017 09:54:21 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6367B21EA15DF; Mon, 9 Oct 2017 09:50:45 -0700 (PDT) Received: from mail-lf0-x22b.google.com (mail-lf0-x22b.google.com [IPv6:2a00:1450:4010:c07::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6A93821EA15BA for ; Mon, 9 Oct 2017 09:50:44 -0700 (PDT) Received: by mail-lf0-x22b.google.com with SMTP id 75so664690lfx.1 for ; Mon, 09 Oct 2017 09:54:11 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:08 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22b; helo=mail-lf0-x22b.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n8QDShp+Oaxhbw9WR9alMZeqHewJz0depNLgztERpUQ=; b=T8hHAWIaI6EP/z8uB1lJN6tKWI+t4W3Ts19SaQtX8sQj358MYBPoFI/He6pGP9hbaj S8v2ixXIVwOa1Jykf0jbxl5m6/xKNWgJPJHCDX/RdaVrVZPYUHpp5iV1fTGxrOvCzIkx wgR9sSc9bXYqb6Q+16/B6XqqRcFnz+cgxyvOFWepXX5DBs4j/DrTZOqNZ6dEATJMAdHu cnmiyy6ziaVw3NYGSG0fncqv79yKxwDWcOODcOcFcO9rGvzHOYctlewAmbsB3UHzDlH5 Wr5l6QVA+UM5kOPaTVLSv4Bb91c4XngUilDvEj5PkjnofF9IKNzLF2NBeN+If3AGG38A SapA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n8QDShp+Oaxhbw9WR9alMZeqHewJz0depNLgztERpUQ=; b=QhycrkP7I/Z/DW7VFV7dqWFntJRwqju7sqp/oiD2DMtDJUYj1xM6zn3RMWXxwNsEKJ wPcOZktaHxIqWptl27NO3dE4nEciZfpozJFloz3as1dxgW9jMl+R43WrV8JxGehyLT79 YMGGElJTGgxza+7GTtx7iKCLG3NU1RVYM8kGIz/2AbYtQ97a6Bd7Kw+KsrpzoRfFq+S0 zv//YrQqlUdsMZTdMxUWrfvhIJLmYjh+flaBNWh0cdyE/80Zv1etzJN57mRfi1j6aNuo VssmeNBQrTSfUGURtG9nQHIPLn8hv4P9RNLe6sS1RFszZbUHXwkRjhJYnYDd4+d6Q5Z7 l+Tg== X-Gm-Message-State: AMCzsaWTNQhPer9fVp6W3E+47gu5Vf+aNC86WZdFnFO6sBKFOwzMUG94 MnQC2pQks7Avut/hjAM3vD9d1gBCdOY= X-Google-Smtp-Source: AOwi7QBRWSlprayWZPLrH2qbpYaKxIClGoUFqEx6or5AZueHdS9UHwXVf1MDgc4cQay6aquNAXDpRg== X-Received: by 10.46.97.17 with SMTP id v17mr5641385ljb.155.1507568049690; Mon, 09 Oct 2017 09:54:09 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:54 +0200 Message-Id: <1507568462-28775-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 05/13] Marvell/Armada: Use 4k/64k aligned sections for DXE/DXE-rt modules X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Enable strict memory protection at boot time and under the OS, by using 4 KB section alignment for DXE_DRIVER, UEFI_DRIVER and UEFI_APPLICATION modules, and 64 KB alignment for DXE_RUNTIME_DRIVER modules. Note that the latter is mandated by the UEFI spec. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 433892e..1b4e713 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -486,6 +486,12 @@ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 } =20 +[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,B= uildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICA= TION] + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x10000 + ##########################################################################= ###### # # Defines - platform description macros --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507568063859217.30055239324884; Mon, 9 Oct 2017 09:54:23 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9FA7221EA15BA; Mon, 9 Oct 2017 09:50:47 -0700 (PDT) Received: from mail-lf0-x236.google.com (mail-lf0-x236.google.com [IPv6:2a00:1450:4010:c07::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A5FA421EA15D5 for ; Mon, 9 Oct 2017 09:50:45 -0700 (PDT) Received: by mail-lf0-x236.google.com with SMTP id k40so8545675lfi.4 for ; Mon, 09 Oct 2017 09:54:12 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:10 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::236; helo=mail-lf0-x236.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zM+e0p6s5F+GtjW/oKA9f7K7ABrI05t/6RpCxpHll9M=; b=0B+HoiwYSXYYv7eGFnMXFyaD488Zl6Nf2n/gR+Uc4LNKG6tSPGG/YnwyiRENUcRwxj CHDu/YEnSbHAjufiOqgoDmC2jo81dGbdBWJCDZlP6Rlykq+dv2dbBceLOHW2bQmefYD1 ePnHxGDJKOWlUnqK21xQb6k52aTmtmU0mZ1w2QMk6Bk1YsXpO+xy4eVTAT4LxhViheXY o2nUhuSK1nB13xZydoI8O+jgNrFMdOeiPSuCHm7Cc9OPPjydq6qHxjsBj6mEBr97cejX ygNkEbDZ0FuDOqiRCB8iyFy7YGhZoP0rLG/JkLUV18W+q0wBa7wLtlfgizePrWqPP5CN /rDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zM+e0p6s5F+GtjW/oKA9f7K7ABrI05t/6RpCxpHll9M=; b=kW4gNVTWP5j6naSh3iRHMQxzBr/a6lSs9xDHRTOLRIc/vSGLJ6SLhyHBwbPXroGPIB apAxzh7xIp+ed3qHpaa2u+hEaIl3vAzDPI5ViOz5UC4TuJomXkIPQxX1sVK7/v618iT/ +yKrIjunIZ6LhZIVi3qSVPieIXm4Z9QhdPPHG5DEi9nOlR2t1E646t9Vf4/k+tCBlDkl nn1tYkIIggdvg/SxvqczRZQP997nfeWi44qF0k8bU0CkdWwzL+1bO0b8Eqx2JRsaNndC xWG2eMOyf+9v2oghYuFBKTtDAZjVMSBQItQXUFz+mSa11pcvw3Jbp7FL4qFDRqXS3Edc huFg== X-Gm-Message-State: AMCzsaXqEWkyjIgS4xHScyOGixeVwIiqgleq2LCpMddFJqLxmkaEqdD5 kdsxJHLFatQQtYFlwnNoGYEteQGPTVk= X-Google-Smtp-Source: AOwi7QCxh2wdLs79T2LIEVMgPb8xEG2ed0j5um5wQwoZqoYTnpZDWwVSoJm6lH3pqDmBSugvhbUbMg== X-Received: by 10.25.24.105 with SMTP id o102mr3597692lfi.131.1507568051027; Mon, 09 Oct 2017 09:54:11 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:55 +0200 Message-Id: <1507568462-28775-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 06/13] Marvell/Armada: Switch to generic BDS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Switch from the Intel BDS to the generic BDS, which is preferred for ARM platforms given that it is completely legacy free. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 19 ++++++++++++++++--- Platform/Marvell/Armada/Armada70x0.fdf | 3 ++- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 1b4e713..e920461 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -126,8 +126,9 @@ =20 # BDS Libraries CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf - GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLi= b.inf - PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelB= dsLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo= tManagerLib.inf CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf =20 @@ -350,6 +351,12 @@ # Shell. gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE =20 + # GUID of the generic BDS UiApp + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + # use the 'TTYTERM' terminal type for optimal compatibility with Linux t= erminal emulators + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + # ARM Pcds gArmTokenSpaceGuid.PcdSystemMemoryBase|0 gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 @@ -459,7 +466,13 @@ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } =20 # UEFI application (Shell Embedded Boot Loader) ShellPkg/Application/Shell/Shell.inf { diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index b3d1c60..999b968 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -175,7 +175,8 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf =20 =20 # PEI phase firmware volume --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150756806898923.067483365111116; Mon, 9 Oct 2017 09:54:28 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DCEC021F3C184; Mon, 9 Oct 2017 09:50:49 -0700 (PDT) Received: from mail-lf0-x22a.google.com (mail-lf0-x22a.google.com [IPv6:2a00:1450:4010:c07::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 051F621EA15B9 for ; Mon, 9 Oct 2017 09:50:46 -0700 (PDT) Received: by mail-lf0-x22a.google.com with SMTP id l23so21160594lfk.10 for ; Mon, 09 Oct 2017 09:54:14 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:11 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22a; helo=mail-lf0-x22a.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T7pBxJ7iBCnpsaLdb4uSfMDXS+28ewIFiK/Jxhy55jg=; b=hNY5YCuiVH1Ydbz9hsl6Cj78DD3TppHH+nma0siuzRz6U/TbzIkO/BpyGlEJROfn76 xK+pIxuKKDxzIWgmWfISzgoNDtVJdeR1350GajvTa3fELNmFfxZ5F5UT2KAFGTindywH 3+MhZ7d0vdrLj0kblbu+J7FNPevvMsXS0ZuswYh8vL1OgRiHzI4Z7UwA5G8Zt6SV7jIm loUoDjeTpTj2qgr37QPVYgDK6dkGI+kgnKxcgc9xuCmU3bkLBqrbjpgkY1cS8L0ASn6i ekMMq/nzG7acdo7U386GRWXyz2+G0RzqF0Ae70iCuugkoidOT3Arvg4V8Na5sskbnet1 u5Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T7pBxJ7iBCnpsaLdb4uSfMDXS+28ewIFiK/Jxhy55jg=; b=b8LdZUts0KrqhSfr8o1s/dq6ae8qdY+JkcgptSGaLQh7DIDfTRWqthnb9PCP1aqoKt 5n0O/jKGC9OSXLpmhQlQJwwO5VyuhpEPn+ToXe3/kQCHedZLfmcHLrc1MJcWssyEyaFE vI+495PhxU5QvpjgwDiZn2ALWPp18vmmPAOKrgqAwjwVhHqX77NIi4Ck8VbC3jS29b8Q zlel0jHpTwovh6JcJISZ4r7oSoiNwybiI6zZgKv8RLtAOvQUGtukVZ7X1ls5j+LTUBEW StJLFVrEU6gS17UQX43qyZxBZEFZ3KZRWkvNW5URdIUQMlGMHtZqdnyn2FhHyaJtLU2C 8lpg== X-Gm-Message-State: AMCzsaX/d5XtO3OMD9MbU1fcGhW8Tns1SEBo64xVcgfcmQ+sIlASl/Fu bPArl0qgraiXF32cDi7nvIx6yah7F2c= X-Google-Smtp-Source: AOwi7QAtxpzg3mG7LCFrIvjls7rY6QJGoZ3q495naWquztOa8RZ3P8v30xTZ3Hu4NyGJ5n7Psj5r8Q== X-Received: by 10.25.159.146 with SMTP id i140mr3239490lfe.253.1507568052326; Mon, 09 Oct 2017 09:54:12 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:56 +0200 Message-Id: <1507568462-28775-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 07/13] Marvell/Armada: Re-enable driver model diagnostics PCDs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel For some reason, one of the early ARM platforms disabled all the diagnostics related to the UEFI driver model, resulting in the output of UEFI shell utilities such as 'devices' or 'drivers' to become completely useless. Armada's shared .DSC include file inherited this for no good reason, so let's revert it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index e920461..5071bd5 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -207,10 +207,6 @@ ##########################################################################= ###### =20 [PcdsFeatureFlag.common] - gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE =20 # # Control what commands are supported from the UI --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507568069764464.16688450670165; Mon, 9 Oct 2017 09:54:29 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 22A8A21F3C187; Mon, 9 Oct 2017 09:50:50 -0700 (PDT) Received: from mail-lf0-x230.google.com (mail-lf0-x230.google.com [IPv6:2a00:1450:4010:c07::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4540621EA15C5 for ; Mon, 9 Oct 2017 09:50:48 -0700 (PDT) Received: by mail-lf0-x230.google.com with SMTP id p184so27778576lfe.12 for ; Mon, 09 Oct 2017 09:54:15 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::230; helo=mail-lf0-x230.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bchyVimM0NgjRhQGLEsFq/B2GfjXglDO8oazF5/2S5w=; b=HqG8Nixz7Zgm2Nqsg77ZWrvztqoTFiyKWrb2vk6jKqbZWJEBnozFTgmxig3JDiEcyG BuuaEqEm63Z8tMwBXEWBqhbHXyI+bsrAlfl4TmoVnNk3Hf0Ef/GQ8dG7q2XShyO1jqFb p8jCN56jM89TlROcG9mm4SBeU54SMQ3FCTLtQk16zz1NzAzOXUExzFR6TVE/cgPiSdMn Vxw44yuFEnL53zzVnx5kwLPkCY85KxWRjWK6PoTaC3PAOMA3FVDzqVl+8jbOX0SGr88h RLCmgpawz/U9TmcjSeVjjX5H2bQKwBQD0dJlQviaIaf+FqLsxaWdim7ySj4oHSe3Yz8c auzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bchyVimM0NgjRhQGLEsFq/B2GfjXglDO8oazF5/2S5w=; b=mIsUxszHNpJf6kSBbQ3uc8LsRjS3w7RiM1JyMQFbxmz/5HEMY/NAg+yrQVozmizv9J LB/v3kYdEyWJlz0WX7GXA9Uf9XRGu/F76D5osegQ1Jw8xbX+oKzvNPmB04H1D831PMD8 ZHShyDiXOPkGPhZOVesFvL1mWHuwuRCCeKE837F19aJYcrAZbQItbW9CkvHzVb0hl8JX ahHfWT2F3ObVf1v2jB7MDhCqJTK1+4NAEu9OnpBPq0OUrfxldz2/QZveNR2ah9HNUddv /o6FC2+KLliN7zmNIEMFhpEcZraLdTt1UAXVNmRJAnIkEeXzgsT6cFg87H/DgVOOSK0c Wf7A== X-Gm-Message-State: AMCzsaUf6EIN+6skUO48v/EUhsueeDYbIQ0xk31r9YyxxT1tvY9Ds2D+ 5PzVUsbotwy61QVDQx/kKBFecirlpno= X-Google-Smtp-Source: AOwi7QAGFdWuONFLU2RQVJpnNyeU1+ZNftGcTqYw7czRbv+NF3GmNrpEbh3WP9DyEd3eSxsL+J99Qw== X-Received: by 10.25.229.221 with SMTP id i90mr2253580lfk.71.1507568053521; Mon, 09 Oct 2017 09:54:13 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:57 +0200 Message-Id: <1507568462-28775-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 08/13] Marvell/Armada: Modify GICC alias X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The GIC architecture mandates that the CPU interface, which consists of 2 consecutive 4 KB frames, can be mapped using separate mappings. Since this is problematic on 64 KB pages, the MMU-400 aliases each frame 16 times, and the two consecutive frames can be found at offset 0xf000. This patch is intended to expose correct GICC alias via MADT, once ACPI support is added. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 5071bd5..bd2336f 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -263,7 +263,14 @@ =20 # ARM Generic Interrupt Controller gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF0220000 + + # + # NOTE: the GIC architecture mandates that the CPU interface, which cons= ists + # of 2 consecutive 4 KB frames, can be mapped using separate mappings. + # Since this is problematic on 64 KB pages, the MMU-400 aliases each fra= me + # 16 times, and the two consecutive frames can be found at offset 0xf000 + # + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF022F000 =20 # ARM Architectural Timer Support gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|25000000 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507568072749927.3696132121765; Mon, 9 Oct 2017 09:54:32 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5FEEF21F3C183; Mon, 9 Oct 2017 09:50:50 -0700 (PDT) Received: from mail-lf0-x22e.google.com (mail-lf0-x22e.google.com [IPv6:2a00:1450:4010:c07::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 73CB121F3C181 for ; Mon, 9 Oct 2017 09:50:49 -0700 (PDT) Received: by mail-lf0-x22e.google.com with SMTP id a16so10595548lfk.0 for ; Mon, 09 Oct 2017 09:54:16 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:14 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22e; helo=mail-lf0-x22e.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PWr3CVDCyD9UBxCf8+vpM+gdkShh9pZbPcif/Q/AYAA=; b=JuGsDRUCzt3/VJooHjOT/MiL4/3+fxhKD37d7fUyRzGSdPqbVoIkj4CvPdYfNTdDYv cQXL9iY0mQncDTZXt+OlOkBBJTxHUA9VaxhCTQETbNQKDGwdTL65CrDO0lpbBkqdf/Cp y+wrXj8D2h/epQ4kYkjfK49mpTjwtSWfGJCfF4+6Sy162SDu39LNksx9cy5tjBbfpbcF hngVgbOulojrSiJTXmrktpFfD9Wv3PKt0aBItU26KEPtz1TJkCT8hTqi6rWsipJJPHff CHNLEAs/NBwM6J3Mw4E3Bp3f6G+YPEIMAtsnrUO5YNUJWBDBWwdjr7pix/i5yj6sG7D7 JOxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PWr3CVDCyD9UBxCf8+vpM+gdkShh9pZbPcif/Q/AYAA=; b=IG3dviW3ohLzU+bg9YEc9+gA6ZgUUjFu0tY2TWg+h5p9s647+mIm4DeWZedoR6wH9b QbOYErt7zfInDf6gPgQu1gyLv5sUZzKXc3Uka5VTYpUJpGLt4pHG0HVlUf+h64qJpk2g c6D9SAJJ9GPne9M1YeqByPPEntRLX/OuTiKxBRQoy9XiTgdrsP9ntSLnKkQEabwdF61e TNv6gqYs94HNo8dft7mze1KQrDBqBfa7qKpo7guZA2768obQijH2OWj9GjP8U9WTU6Mo IQJaBtHQStTD35PfmS3hVwghlRhhwSi1LsguxLBx2NUOQ7/EWXOJzzCiF1KoXMtk0gY9 uyww== X-Gm-Message-State: AMCzsaVJHG3LdiXtwWpetEG22KLg6SOvSNLH3urMLRBhzA+Ic6aNMZOP DBPkEDvntIFCdm8z73LfUlnZ0C9nfGI= X-Google-Smtp-Source: AOwi7QDhyDvhC/HMvOKzGFrehRqWDSHw6BTMYwwa6EukPYPl+6PcLpSZstm6kJDbDpoXM88HIxJfYg== X-Received: by 10.25.41.8 with SMTP id p8mr3921532lfp.31.1507568054772; Mon, 09 Oct 2017 09:54:14 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:58 +0200 Message-Id: <1507568462-28775-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 09/13] Marvell/Armada: Disable PerformanceLibrary X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Remove the gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask setting so it reverts to its default of 0, and disables performance profiling. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index bd2336f..b718c60 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -251,7 +251,6 @@ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150756807579552.7130302761168; Mon, 9 Oct 2017 09:54:35 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9A34821F3C18F; Mon, 9 Oct 2017 09:50:51 -0700 (PDT) Received: from mail-lf0-x22b.google.com (mail-lf0-x22b.google.com [IPv6:2a00:1450:4010:c07::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id ADAA621F3C189 for ; Mon, 9 Oct 2017 09:50:50 -0700 (PDT) Received: by mail-lf0-x22b.google.com with SMTP id a69so5037881lfe.5 for ; Mon, 09 Oct 2017 09:54:18 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:15 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22b; helo=mail-lf0-x22b.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SKcAARrXYOCpFMI6ew2YK5sv1XmKs3DDSjPIQv/ENs8=; b=E+0mfUfLaAKzSUmMY1txViy5s0Sj2SgmSrMytVBdKrLq5GxzG9hYQJanpQF0v/Q+C9 oyaburhrlsDJPnpDtINSlFgZpbhysdAGy5PKYNlPKdKuG/OUhfFJh7KVznB1Qw1PrVNH 9e+eY2FDlXM92qPrqrPlfqSxBG3X9h2y77af/emxJSfc3U6iO9/VV0qIwkgqKp9ejyLi +aFIVkf+GxoZvc96hDANpENI5raPXNGVaZNbh4DkuiGGno9/vHiY+RO8KoSnbSmr+Z28 qa5fh8A44Rwn1Q1FbDNen0+uQMje7CxShWXnY7HEIMhVs2UEpi84zjSvoEN6sHuvEU7F 9ngg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SKcAARrXYOCpFMI6ew2YK5sv1XmKs3DDSjPIQv/ENs8=; b=b/aj7V/P2X8rUsh8PEHLbDn99BEW5Pd7obefFP4k9daRwihbhaGPRzHx7XNxLjKkw3 XXLZRWd0xO1eYpNlZu+AvHfMgiTvtHg/GlZ3jimQfyinZOA+C/vHGLKaQGEVO3RfJ5oY TtzFuAcudmXnxfcmegMmI5WAdVvJCQsOYfQ7AGERYADXwRzl8AVohjSM/jzuDoC0JyFS M2c2MQ3tCEfZkBnNKSvk6O8gGHLIUseqkc4H/259MWS8uWA0wROTBmIjygh0kSyFUodz pALXfyMkINB2GxXyNimxeHQGCdmTumOIRiqNe6K45qouuYXJxFpx9y6if1AuwSuTDDae XhbQ== X-Gm-Message-State: AMCzsaW8glFGoFS3sGPQMja0dgLGufPatNT8VU311aUqhv8pmNolA2yD KvqFOQfeyImgepcKS9hyIXPPkcHXPhQ= X-Google-Smtp-Source: AOwi7QDZBzXKgMUYqKsBO4tmlrGDCi1KX3j+HiH8lHI+7RUprHFPS0QmbW5+4yLczqG8VVV20MiGUg== X-Received: by 10.46.21.25 with SMTP id s25mr4716098ljd.71.1507568056031; Mon, 09 Oct 2017 09:54:16 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:59 +0200 Message-Id: <1507568462-28775-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 10/13] Marvell/Armada: Switch to unicore PrePi X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel There is no point in using the MPCore PrePi, given that only the primary core will enter UEFI at EL2, and the secondaries will be held in EL3 until summoned by the OS. So use the unicore flavour instead. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 2 +- Platform/Marvell/Armada/Armada70x0.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index b718c60..5a5fde9 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -372,7 +372,7 @@ [Components.common] =20 # PEI Phase modules - ArmPlatformPkg/PrePi/PeiMPCore.inf + ArmPlatformPkg/PrePi/PeiUniCore.inf =20 # DXE MdeModulePkg/Core/Dxe/DxeMain.inf { diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index 999b968..2c3efe0 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -199,7 +199,7 @@ READ_STATUS =3D TRUE READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE =20 - INF ArmPlatformPkg/PrePi/PeiMPCore.inf + INF ArmPlatformPkg/PrePi/PeiUniCore.inf =20 FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507568079311453.00735033534863; Mon, 9 Oct 2017 09:54:39 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D7D3521F3C186; Mon, 9 Oct 2017 09:50:53 -0700 (PDT) Received: from mail-lf0-x22e.google.com (mail-lf0-x22e.google.com [IPv6:2a00:1450:4010:c07::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DDB6821F3C189 for ; Mon, 9 Oct 2017 09:50:51 -0700 (PDT) Received: by mail-lf0-x22e.google.com with SMTP id n69so198353lfn.2 for ; Mon, 09 Oct 2017 09:54:19 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:16 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22e; helo=mail-lf0-x22e.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iGLRvlevdljkjDDJY1CPFfrsXsWqLPDbEjJMzwxx5yo=; b=eqBOLVKmZInEYIqeXrPTv8fs4uIROvcwLH8m39ftqLKpbDsZjh0+Vfrl0wTTrBYY10 lICrC13W1804Ttj/876nyt7ArMPAMUpMejs/qITi7wjBNmxMw0Kc6W8S2aUfIYtYWRW1 Q7bKqaW6ctAnNdRw073FhOvxXt9dfZQt/lL8y6duq2IAV7Wthxi8udVAXXaXThPHhjbt mSVVe38t3lubXpYw8sQD62SFzemGLBKbTPatG+hhrJDTuTDhd3ifA6kgo/F+odrbT/mE Uty5psJsfuVGtn97dqpCZbEoeChT5WHbBrFhtA/Lnw5E+KbQsWYN/OLLv4ebmbe6D+XJ lU+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iGLRvlevdljkjDDJY1CPFfrsXsWqLPDbEjJMzwxx5yo=; b=mLvZvL4Z9DBH4/jKGaE3YYBRLs0Frr6VflGrpkQlpKPwrjSUG+jFb3ndaSFMmhAP58 bMYBP+LIyOMaNBbtcAA5UujqXqxX2mCZGHKR65JXBrVbYGa0xgoIAtrswKsvjIylzZEs t/j7VntwdGg0qnO5zYxHOOIISzExKxJdK1Y+wep3Fo3lQwdeeyHKx+QNBUmTSTEntbeQ VlNNly9VflyxOusdA7Gv39joWSdq5S6nCgARrLTt+JMKME4bq1Ys15zM3Ii8uAHqHu/J jJF4Fgz6n6jCr1Yp8j0tC/IDdGvhWhFHYL3hp1lNagR2z3auyLn9UoksbU2BS6E1cpkA A/QQ== X-Gm-Message-State: AMCzsaVszLoJjgl8flLr2QjfJe2vc5NqWw1/WROoTtv9qdgN6gP36Ylt 8ALPy4+JSnYH+xfWGz976uL0KAvf3x0= X-Google-Smtp-Source: AOwi7QAW3Ow25/eCGV5uKPxA2W42NtdEGdMmzi6moxFReFkm3xVt5fbCOUg33o6vCNqYjHMUGsGDHA== X-Received: by 10.46.58.2 with SMTP id h2mr2975785lja.132.1507568057323; Mon, 09 Oct 2017 09:54:17 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:01:00 +0200 Message-Id: <1507568462-28775-12-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 11/13] Marvell/Armada: Remove outdated SEC alignment override X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The FDFs no longer require explicit alignment for sections containing aligned objects, so change it to 'Auto' and FIXED (which allows some padding to be removed), and remove some other cruft while at it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada70x0.fdf | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index 2c3efe0..15ae52b 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -235,16 +235,9 @@ READ_LOCK_STATUS =3D TRUE # ##########################################################################= ## =20 -[Rule.ARM.SEC] - FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { - TE TE Align =3D 32 $(INF_OUTPUT)/$(MODULE_NAME).efi - } - -# The AArch64 Vector Table requires a 2K alignment that is not supported b= y the FDF specification. -# It is the reason 4K is used instead of 2K for the module alignment. [Rule.AARCH64.SEC] - FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { - TE TE Align =3D 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).e= fi } =20 [Rule.Common.PEI_CORE] --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507568082318464.6407054710347; Mon, 9 Oct 2017 09:54:42 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 21A3F21F3C193; Mon, 9 Oct 2017 09:50:55 -0700 (PDT) Received: from mail-lf0-x22d.google.com (mail-lf0-x22d.google.com [IPv6:2a00:1450:4010:c07::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3680921F3C180 for ; Mon, 9 Oct 2017 09:50:53 -0700 (PDT) Received: by mail-lf0-x22d.google.com with SMTP id a132so19942127lfa.7 for ; Mon, 09 Oct 2017 09:54:20 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:17 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22d; helo=mail-lf0-x22d.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UUg1f8BzErIQFbZTqvwCkvy6XxZXeq4SN0WM8lqfl9Y=; b=wZ3nIxWBG2aIOb6yCe9CPs4KCKKny+/xYVgd0lc2XCDb2xFOEIWUe7PH8AQHlIdy9t w4wJfe8N11dWKs3lWsxFqWmkVgeEdBmwVS2eXTC3fr1af3SAN58LVRozRDxUHC8DDbIf fNs6opS6QiYNLGSIIdFyNZakNt96tPVCweT3BOfc3QwQEcvz/9sqZ4zxRuv+a8JVvcIg VCEypGsiP0KaOPCLEJGswN/7OGvGYAoZvb4XnfDqxCdG6VnUA7y0sC+tT4yvNdtTXSS8 /4KWdg/AIAbi0NNT8sLKgTwJJ5tdtr5PCioHQOorY8xkhnrA+d8pMVKVaBpaUOiqxMsu A5RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UUg1f8BzErIQFbZTqvwCkvy6XxZXeq4SN0WM8lqfl9Y=; b=rhobRIOl1yR8hDoZn4q5xN/cho4prMNonHRPC6wYPGXueHzSjTbLSrMBVqZQ+DzX2K TdTVurvIcxVs3WafSYPQSL57HsJqULCGJ8xE1O996fB9wBw3dGpGfwJBA6hcDff96kE0 qz/2PKoTc6JdipkcUiVCVAJXW4F5REqt/oQj/6u9d0X6Srny/RkBlHYvllrYIxWqObUf ZeLqRtGZ1LJ3jTwXuDcADQha6SkwpmmoY5slcfzLwEBrXR2CiG/9h5WJBVMtgfjJwyo5 wDiHcGemVi7mW9Xf2cGVe1RvgldQnaD6g/5ivAAAE+QRGEw9PL9FAln1Y3VV6j6VzyaE EdTA== X-Gm-Message-State: AMCzsaX8gWcdSAzCYcVRSiZ9mDaouYwpmEjKqAiaqy7mjWqx41tIm0VP f9CrZYQTiDSx/29nW82NSerC2HAWICo= X-Google-Smtp-Source: AOwi7QAx3Yw2fvF6PXnEdEOwrsBIVYE2t+hrY3Vp234xgB58z8BjJp2qILe5pHi7Jqk8svm5ZpPR1Q== X-Received: by 10.46.48.20 with SMTP id w20mr4045079ljw.51.1507568058613; Mon, 09 Oct 2017 09:54:18 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:01:01 +0200 Message-Id: <1507568462-28775-13-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 12/13] Marvell/Armada: Add the UefiPxeBcDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel This driver allows automatic booting via the network. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 1 + Platform/Marvell/Armada/Armada70x0.fdf | 1 + 2 files changed, 2 insertions(+) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 5a5fde9..1aa485c 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -412,6 +412,7 @@ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index 15ae52b..bf54c6e 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -125,6 +125,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf INF Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf INF Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf INF Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:57:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150756808584538.59047010944869; Mon, 9 Oct 2017 09:54:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5A19221F3C18E; Mon, 9 Oct 2017 09:50:57 -0700 (PDT) Received: from mail-lf0-x22c.google.com (mail-lf0-x22c.google.com [IPv6:2a00:1450:4010:c07::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F2C8C21F3C18E for ; Mon, 9 Oct 2017 09:50:54 -0700 (PDT) Received: by mail-lf0-x22c.google.com with SMTP id p184so27778942lfe.12 for ; Mon, 09 Oct 2017 09:54:22 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:19 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22c; helo=mail-lf0-x22c.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fSZtqw8+DeVP4ffcWgYr1xoYk8IxBQH6F/F1BwgNDKk=; b=xJXnNtmjxcK9yjcnoc4Ppo4A0ux9v6aCUjdTeI+txShAq5BoXnkQWWNNxOhLExTvRT oC48Cv7zIlXD/l6OkXhamQZYbHWdiS4ssi9GgUvR+KMkU61Cr4+3VdZDcSKvLvZfKT70 i1YFp2dQTEpoDJ71rEo3vhb28Awz3geR9UqZU6z3k0ipgNbKZWoJM850cM/tGPu9sTbL 52cMiMUT0GjXYVZYmFltN5JOHvLnXTF2jwnlIYFlU+agJbXWB/bft0dPKqPvuYV0wVq6 eRzCH14LkNJ1NqdB10HeVNxkytwaqBwnGzaTupYvWP7UWlnHHnFYobHIJZ2X0V0Uz0S5 S9FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fSZtqw8+DeVP4ffcWgYr1xoYk8IxBQH6F/F1BwgNDKk=; b=S88caqgYaEgVfLbOlXfjOJsKyf1V3EfYBWsgmn+ItKDbtfkS1qhNZr22q7U8XiwRkm gnQJyAEeID2VZX9EuPe04ldtZr7tSlVqVHIk5JEMJ2THze+rvv1uRgXX6EmSiPMODu0r AinGQyinb2zjvpIjyufMZs0tbecKSd2RiYV6ZiYsWzReUKVBw/Rwhzemy6gPyiewupyd vfDht6Q3nZPrGhci4wCdyo4aryO6+aBy/4TsiNA+xYKYk7prMmGWhJltKblSQMSL/W7g miSvyzDyw6vgWotgOMIO919q+EdiKo5zVlDbNs8qX8ujlnbvUwubY5C0Er9Z0PwBzhmY IJjA== X-Gm-Message-State: AMCzsaWll+U2U0ezGuZJBS0FuyifsNkczL26QOouFWZMDpaQXEGASf+R PcZXzAjJTUTa1CVTJr2Ecw8+qk/fC6M= X-Google-Smtp-Source: AOwi7QBtOh/0GCHhoWLSKFr0WSYFhZP1azmjNCiU3wyWnPIWnxSXMA3ta+4BKNTMDO+JkV/tbmZpcA== X-Received: by 10.46.22.4 with SMTP id w4mr5044187ljd.21.1507568059939; Mon, 09 Oct 2017 09:54:19 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:01:02 +0200 Message-Id: <1507568462-28775-14-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 13/13] Marvell/Documentation: Follow EDK2 coding style in the PortingGuide X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch removes tabs and wrong line endings in the file, maiking it acceptable to the PatchCheck.py script. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Documentation/PortingGuide.txt | 800 ++++++++++---------- 1 file changed, 400 insertions(+), 400 deletions(-) diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index f0da515..66ec918 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -1,400 +1,400 @@ -UEFI Porting Guide -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -This document provides instructions for adding support for new Marvell Arm= ada -board. For the sake of simplicity new Marvell board will be called "new_bo= ard". - -1. Create configuration files for new target - 1.1 Create FDF file for new board - - - Copy and rename edk2-platforms/Platform/Marvell/Armada/Armada70x0.fdf = to - edk2-platforms/Platform/Marvell/Armada/new_board.fdf - - Change the first no-comment line: - [FD.Armada70x0_EFI] to [FD.{new_board}_EFI] - - 1.2 Create DSC file for new board - - - Add new_board.dsc file to edk2-platforms/Platform/Marvell/Armada direc= tory - - Insert following [Defines] section to new_board.dsc: - - [Defines] - PLATFORM_NAME =3D {new_board} - PLATFORM_GUID =3D {newly_generated_GUID} - PLATFORM_VERSION =3D 0.1 - DSC_SPECIFICATION =3D 0x00010019 - OUTPUT_DIRECTORY =3D {output_directory} - SUPPORTED_ARCHITECTURES =3D AARCH64 - BUILD_TARGETS =3D DEBUG|RELEASE - SKUID_IDENTIFIER =3D DEFAULT - FLASH_DEFINITION =3D {path_to_fdf_file} - - - Add "!include Armada.dsc.inc" entry to new_board.dsc - -2. Driver support - - According to content of files from - edk2-platforms/Silicon/Marvell/Documentation/PortingGuide.txt - insert PCD entries into new_board.dsc for every needed interface (as li= sted below). - -3. Compilation - - Refer to edk2-platforms/Platform/Marvell/Readme.md. Remember to change - {platform} to new_board in order to point build system to newly created= DSC file. - -4. Output file - - Output files (and among others FD file, which may be used by ATF) are - generated under directory pointed by "OUTPUT_DIRECTORY" entry (see poin= t 1.2). - - -COMPHY configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -In order to configure ComPhy library, following PCDs are available: - - - gMarvellTokenSpaceGuid.PcdComPhyDevices - -This array indicates, which ones of the ComPhy chips defined in -MVHW_COMPHY_DESC template will be configured. - -Every ComPhy PCD has part where stands for chip ID (order is n= ot -important, but configuration will be set for first PcdComPhyChipCount chip= s). - -Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes -settings for this chip. Their format is array of up to 10 values reflecting -defined numbers for SPEED/TYPE/INVERT, whose description can be found in: - - OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h - - - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes - (Array of types - currently supported are: - - CP_UNCONNECTED 0x0 - CP_PCIE0 0x1 - CP_PCIE1 0x2 - CP_PCIE2 0x3 - CP_PCIE3 0x4 - CP_SATA0 0x5 - CP_SATA1 0x6 - CP_SATA2 0x7 - CP_SATA3 0x8 - CP_SGMII0 0x9 - CP_SGMII1 0xA - CP_SGMII2 0xB - CP_SGMII3 0xC - CP_QSGMII 0xD - CP_USB3_HOST0 0xE - CP_USB3_HOST1 0xF - CP_USB3_DEVICE 0x10 - CP_XAUI0 0x11 - CP_XAUI1 0x12 - CP_XAUI2 0x13 - CP_XAUI3 0x14 - CP_RXAUI0 0x15 - CP_RXAUI1 0x16 - CP_SFI 0x17 ) - - - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds - (Array of speeds - currently supported are: - - CP_1_25G 0x1 - CP_1_5G 0x2 - CP_2_5G 0x3 - CP_3G 0x4 - CP_3_125G 0x5 - CP_5G 0x6 - CP_5_15625G 0x7 - CP_6G 0x8 - CP_6_25G 0x9 - CP_10_3125G 0xA ) - - - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags - (Array of lane inversion types - currently supported are: - - CP_NO_INVERT 0x0 - CP_TXD_INVERT 0x1 - CP_RXD_INVERT 0x2 - CP_ALL_INVERT 0x3 ) - -Example -------- - - #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_H= OST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $= (CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } - - -PHY Driver configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. -Currently only 1518 series PHYs are supported. Following PCDs are required: - - - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg - (boolean - if true, driver waits for autonegotiation on startup) - - gMarvellTokenSpaceGuid.PcdPhyDeviceIds - (list of values corresponding to MV_PHY_DEVICE_ID enum) - - gMarvellTokenSpaceGuid.PcdPhySmiAddresses - (addresses of PHY devices) - - gMarvellTokenSpaceGuid.PcdPhy2MdioController - (Array specifying, which Mdio controller the PHY is attached to) - - -MV_PHY_DEVICE_ID: - - typedef enum { - 0 MV_PHY_DEVICE_1512, - } MV_PHY_DEVICE_ID; - -It should be extended when adding support for other PHY models. - -Disable autonegotiation: - - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE - -assuming, that PHY models are 1512: - - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - - -MDIO configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ a= nd -EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required: - - - gMarvellTokenSpaceGuid.PcdMdioControllers - (Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled) - - -I2C configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -In order to enable driver on a new platform, following steps need to be ta= ken: - - add following line to .dsc file: - edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf - - add following line to .fdf file: - INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf - - add PCDs with relevant values to .dsc file: - - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } - (addresses of I2C slave devices on bus) - - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } - (buses to which accoring slaves are attached) - - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 - (number of SoC's I2C buses) - - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 } - (array with used controllers) - - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 - (I2C host controller clock frequency) - - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 - (baud rate used in I2C transmission) - - -PciEmulation configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D -Installation of various NonDiscoverable devices via PciEmulation driver is= performed -via set of PCDs. Following are available: - - - gMarvellTokenSpaceGuid.PcdPciEXhci - (Indicates, which Xhci devices are used) - - - gMarvellTokenSpaceGuid.PcdPciEAhci - (Indicates, which Ahci devices are used) - - - gMarvellTokenSpaceGuid.PcdPciESdhci - (Indicates, which Sdhci devices are used) - -All above PCD's correspond to hardware description in a dedicated structur= e: - -STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate - -in Platform/Marvell/PciEmulation/PciEmulation.c file. It comprises device -count, base addresses, register region size and DMA-coherency type. - -Example -------- - -Assuming we want to enable second XHCI port and one SDHCI port on Armada -70x0 board, following needs to be declared: - - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } - - -SATA configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -There is one additional PCD for AHCI: - - - gMarvellTokenSpaceGuid.PcdSataBaseAddress - (Base address of SATA controller register space - used in SATA ComPhy init - sequence) - - -Pp2Dxe configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs -are required to operate: - - - gMarvellTokenSpaceGuid.PcdPp2Controllers - (Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled) - - - gMarvellTokenSpaceGuid.PcdPp2Port2Controller - (Array specifying, to which controller the port belongs to) - - - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes - (Indicates speed of the network interface: - - PHY_RGMII 0x0 - PHY_RGMII_ID 0x1 - PHY_RGMII_TXID 0x2 - PHY_RGMII_RXID 0x3 - PHY_SGMII 0x4 - PHY_RTBI 0x5 - PHY_XAUI 0x6 - PHY_RXAUI 0x7 - PHY_SFI 0x8 ) - - - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes - (Array specifying, to which PHY from - gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none, - e.g. in 10G SFI in-band link detection, 0xFF value must - be specified) - - - gMarvellTokenSpaceGuid.PcdPp2PortIds - (Identificators of PP2 ports) - - - gMarvellTokenSpaceGuid.PcdPp2GopIndexes - (Indexes used in GOP operation) - - - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp - (Set to 0x1 for always-up interface, 0x0 otherwise) - - - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed - (Indicates speed of the network interface: - - PHY_SPEED_10 0x1 - PHY_SPEED_100 0x2 - PHY_SPEED_1000 0x3 - PHY_SPEED_2500 0x4 - PHY_SPEED_10000 0x5 ) - - -UTMI PHY configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -In order to configure UTMI, following PCDs are available: - - - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled - (Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled) - - - gMarvellTokenSpaceGuid.PcdUtmiPortType - (Indicates type of the connected USB port: - - UTMI_USB_HOST0 0x0 - UTMI_USB_HOST1 0x1 - UTMI_USB_DEVICE0 0x2 ) - -Example -------- - - # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB= _HOST1) } - - -SPI driver configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Following PCDs are available for configuration of spi driver: - - - gMarvellTokenSpaceGuid.PcdSpiClockFrequency - (Frequency (in Hz) of SPI clock) - - - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency - (Max SCLK line frequency (in Hz) (max transfer frequency) ) - -SpiFlash configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Folowing PCDs for spi flash driver configuration must be set properly: - - - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles - (Size of SPI flash address in bytes (3 or 4) ) - - - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize - (Size of minimal erase block in bytes) - - - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize - (Size of SPI flash page) - - - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize - (Size of SPI flash sector, 65536 bytes by default) - - - gMarvellTokenSpaceGuid.PcdSpiFlashId - (Id of SPI flash) - - - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd - (Spi flash polling flag) - - - gMarvellTokenSpaceGuid.PcdSpiFlashMode - (Default SCLK mode (see SPI_MODE enum in file - edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h)) - - - gMarvellTokenSpaceGuid.PcdSpiFlashCs - (Chip select used for communication with the Flash) - -MPP configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Multi-Purpose Ports (MPP) are configurable through platform PCDs. -In order to set desired pin multiplexing, .dsc file needs to be modified. -(edk2-platforms/Platform/Marvell/Armada/{platform_name}.dsc - please refer= to -Documentation/Build.txt for currently supported {platftorm_name} ) -Following PCDs are available: - - - gMarvellTokenSpaceGuid.PcdMppChipCount - (Indicates how many different chips are placed on board. So far up to 4 c= hips - are supported) - -Every MPP PCD has part where - stands for chip ID (order is not important, but configuration will = be - set for first PcdMppChipCount chips). - -Below is example for the first chip (Chip0). - - - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag - (Indicates that register order is reversed. (Needs to be used only for AP= 806-Z1) ) - - - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress - (This is base address for MPP configuration register) - - - gMarvellTokenSpaceGuid.PcdChip0MppPinCount - (Defines how many MPP pins are available) - - - gMarvellTokenSpaceGuid.PcdChip0MppSel0 - - gMarvellTokenSpaceGuid.PcdChip0MppSel1 - - gMarvellTokenSpaceGuid.PcdChip0MppSel2 - (This registers defines functions of 10 pins in ascending order) - -Examples --------- - - # APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, = 0x1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, = 0x0, 0x0, 0x0, 0x0 } - -Set pin 6 and 7 to 0xa function: - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, = 0xa, 0xa, 0x0, 0x0 } - - -MarvellResetSystemLib configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -This simple library allows to mask given bits in given reg at UEFI 'reset' -command call. These variables are configurable through PCDs: - - - gMarvellTokenSpaceGuid.PcdResetRegAddress - - gMarvellTokenSpaceGuid.PcdResetRegMask - - -Ramdisk configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -There is one PCD available for Ramdisk configuration - - - gMarvellTokenSpaceGuid.PcdRamDiskSize - (Defines size of Ramdisk) +UEFI Porting Guide +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This document provides instructions for adding support for new Marvell Arm= ada +board. For the sake of simplicity new Marvell board will be called "new_bo= ard". + +1. Create configuration files for new target + 1.1 Create FDF file for new board + + - Copy and rename edk2-platforms/Platform/Marvell/Armada/Armada70= x0.fdf to + edk2-platforms/Platform/Marvell/Armada/new_board.fdf + - Change the first no-comment line: + [FD.Armada70x0_EFI] to [FD.{new_board}_EFI] + + 1.2 Create DSC file for new board + + - Add new_board.dsc file to edk2-platforms/Platform/Marvell/Armad= a directory + - Insert following [Defines] section to new_board.dsc: + + [Defines] + PLATFORM_NAME =3D {new_board} + PLATFORM_GUID =3D {newly_genera= ted_GUID} + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010019 + OUTPUT_DIRECTORY =3D {output_direc= tory} + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D {path_to_fdf_= file} + + - Add "!include Armada.dsc.inc" entry to new_board.dsc + +2. Driver support + - According to content of files from + edk2-platforms/Silicon/Marvell/Documentation/PortingGuide.txt + insert PCD entries into new_board.dsc for every needed interface (as li= sted below). + +3. Compilation + - Refer to edk2-platforms/Platform/Marvell/Readme.md. Remember to change + {platform} to new_board in order to point build system to newly created= DSC file. + +4. Output file + - Output files (and among others FD file, which may be used by ATF) are + generated under directory pointed by "OUTPUT_DIRECTORY" entry (see poin= t 1.2). + + +COMPHY configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to configure ComPhy library, following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdComPhyDevices + +This array indicates, which ones of the ComPhy chips defined in +MVHW_COMPHY_DESC template will be configured. + +Every ComPhy PCD has part where stands for chip ID (order is n= ot +important, but configuration will be set for first PcdComPhyChipCount chip= s). + +Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes +settings for this chip. Their format is array of up to 10 values reflecting +defined numbers for SPEED/TYPE/INVERT, whose description can be found in: + + OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h + + - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + (Array of types - currently supported are: + + CP_UNCONNECTED 0x0 + CP_PCIE0 0x1 + CP_PCIE1 0x2 + CP_PCIE2 0x3 + CP_PCIE3 0x4 + CP_SATA0 0x5 + CP_SATA1 0x6 + CP_SATA2 0x7 + CP_SATA3 0x8 + CP_SGMII0 0x9 + CP_SGMII1 0xA + CP_SGMII2 0xB + CP_SGMII3 0xC + CP_QSGMII 0xD + CP_USB3_HOST0 0xE + CP_USB3_HOST1 0xF + CP_USB3_DEVICE 0x10 + CP_XAUI0 0x11 + CP_XAUI1 0x12 + CP_XAUI2 0x13 + CP_XAUI3 0x14 + CP_RXAUI0 0x15 + CP_RXAUI1 0x16 + CP_SFI 0x17 ) + + - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds + (Array of speeds - currently supported are: + + CP_1_25G 0x1 + CP_1_5G 0x2 + CP_2_5G 0x3 + CP_3G 0x4 + CP_3_125G 0x5 + CP_5G 0x6 + CP_5_15625G 0x7 + CP_6G 0x8 + CP_6_25G 0x9 + CP_10_3125G 0xA ) + + - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags + (Array of lane inversion types - currently supported are: + + CP_NO_INVERT 0x0 + CP_TXD_INVERT 0x1 + CP_RXD_INVERT 0x2 + CP_ALL_INVERT 0x3 ) + +Example +------- + + #ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1= ), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G= ), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + + +PHY Driver configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. +Currently only 1518 series PHYs are supported. Following PCDs are required: + + - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + (boolean - if true, driver waits for autonegotiation on startup) + - gMarvellTokenSpaceGuid.PcdPhyDeviceIds + (list of values corresponding to MV_PHY_DEVICE_ID enum) + - gMarvellTokenSpaceGuid.PcdPhySmiAddresses + (addresses of PHY devices) + - gMarvellTokenSpaceGuid.PcdPhy2MdioController + (Array specifying, which Mdio controller the PHY is attached to) + + +MV_PHY_DEVICE_ID: + + typedef enum { + 0 MV_PHY_DEVICE_1512, + } MV_PHY_DEVICE_ID; + +It should be extended when adding support for other PHY models. + +Disable autonegotiation: + + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + +assuming, that PHY models are 1512: + + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + + +MDIO configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ a= nd +EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required: + + - gMarvellTokenSpaceGuid.PcdMdioControllers + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) + + +I2C configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to enable driver on a new platform, following steps need to be ta= ken: + - add following line to .dsc file: + edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf + - add following line to .fdf file: + INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf + - add PCDs with relevant values to .dsc file: + - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } + (addresses of I2C slave devices on bus) + - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } + (buses to which accoring slaves are attached) + - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + (number of SoC's I2C buses) + - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 } + (array with used controllers) + - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 + (I2C host controller clock frequency) + - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + (baud rate used in I2C transmission) + + +PciEmulation configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +Installation of various NonDiscoverable devices via PciEmulation driver is= performed +via set of PCDs. Following are available: + + - gMarvellTokenSpaceGuid.PcdPciEXhci + (Indicates, which Xhci devices are used) + + - gMarvellTokenSpaceGuid.PcdPciEAhci + (Indicates, which Ahci devices are used) + + - gMarvellTokenSpaceGuid.PcdPciESdhci + (Indicates, which Sdhci devices are used) + +All above PCD's correspond to hardware description in a dedicated structur= e: + +STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate + +in Platform/Marvell/PciEmulation/PciEmulation.c file. It comprises device +count, base addresses, register region size and DMA-coherency type. + +Example +------- + +Assuming we want to enable second XHCI port and one SDHCI port on Armada +70x0 board, following needs to be declared: + + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } + + +SATA configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +There is one additional PCD for AHCI: + + - gMarvellTokenSpaceGuid.PcdSataBaseAddress + (Base address of SATA controller register space - used in SATA Com= Phy init + sequence) + + +Pp2Dxe configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs +are required to operate: + + - gMarvellTokenSpaceGuid.PcdPp2Controllers + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) + + - gMarvellTokenSpaceGuid.PcdPp2Port2Controller + (Array specifying, to which controller the port belongs to) + + - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes + (Indicates speed of the network interface: + + PHY_RGMII 0x0 + PHY_RGMII_ID 0x1 + PHY_RGMII_TXID 0x2 + PHY_RGMII_RXID 0x3 + PHY_SGMII 0x4 + PHY_RTBI 0x5 + PHY_XAUI 0x6 + PHY_RXAUI 0x7 + PHY_SFI 0x8 ) + + - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes + (Array specifying, to which PHY from + gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none, + e.g. in 10G SFI in-band link detection, 0xFF value must + be specified) + + - gMarvellTokenSpaceGuid.PcdPp2PortIds + (Identificators of PP2 ports) + + - gMarvellTokenSpaceGuid.PcdPp2GopIndexes + (Indexes used in GOP operation) + + - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp + (Set to 0x1 for always-up interface, 0x0 otherwise) + + - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed + (Indicates speed of the network interface: + + PHY_SPEED_10 0x1 + PHY_SPEED_100 0x2 + PHY_SPEED_1000 0x3 + PHY_SPEED_2500 0x4 + PHY_SPEED_10000 0x5 ) + + +UTMI PHY configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to configure UTMI, following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) + + - gMarvellTokenSpaceGuid.PcdUtmiPortType + (Indicates type of the connected USB port: + + UTMI_USB_HOST0 0x0 + UTMI_USB_HOST1 0x1 + UTMI_USB_DEVICE0 0x2 ) + +Example +------- + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, = 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST= 0), $(UTMI_USB_HOST1) } + + +SPI driver configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Following PCDs are available for configuration of spi driver: + + - gMarvellTokenSpaceGuid.PcdSpiClockFrequency + (Frequency (in Hz) of SPI clock) + + - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency + (Max SCLK line frequency (in Hz) (max transfer frequency) ) + +SpiFlash configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Folowing PCDs for spi flash driver configuration must be set properly: + + - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles + (Size of SPI flash address in bytes (3 or 4) ) + + - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize + (Size of minimal erase block in bytes) + + - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize + (Size of SPI flash page) + + - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize + (Size of SPI flash sector, 65536 bytes by default) + + - gMarvellTokenSpaceGuid.PcdSpiFlashId + (Id of SPI flash) + + - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd + (Spi flash polling flag) + + - gMarvellTokenSpaceGuid.PcdSpiFlashMode + (Default SCLK mode (see SPI_MODE enum in file + edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h)) + + - gMarvellTokenSpaceGuid.PcdSpiFlashCs + (Chip select used for communication with the Flash) + +MPP configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Multi-Purpose Ports (MPP) are configurable through platform PCDs. +In order to set desired pin multiplexing, .dsc file needs to be modified. +(edk2-platforms/Platform/Marvell/Armada/{platform_name}.dsc - please refer= to +Documentation/Build.txt for currently supported {platftorm_name} ) +Following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdMppChipCount + (Indicates how many different chips are placed on board. So far up= to 4 chips + are supported) + +Every MPP PCD has part where + stands for chip ID (order is not important, but configuration will = be + set for first PcdMppChipCount chips). + +Below is example for the first chip (Chip0). + + - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag + (Indicates that register order is reversed. (Needs to be used only= for AP806-Z1) ) + + - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress + (This is base address for MPP configuration register) + + - gMarvellTokenSpaceGuid.PcdChip0MppPinCount + (Defines how many MPP pins are available) + + - gMarvellTokenSpaceGuid.PcdChip0MppSel0 + - gMarvellTokenSpaceGuid.PcdChip0MppSel1 + - gMarvellTokenSpaceGuid.PcdChip0MppSel2 + (This registers defines functions of 10 pins in ascending order) + +Examples +-------- + + # APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0= x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + +Set pin 6 and 7 to 0xa function: + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } + + +MarvellResetSystemLib configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +This simple library allows to mask given bits in given reg at UEFI 'reset' +command call. These variables are configurable through PCDs: + + - gMarvellTokenSpaceGuid.PcdResetRegAddress + - gMarvellTokenSpaceGuid.PcdResetRegMask + + +Ramdisk configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +There is one PCD available for Ramdisk configuration + + - gMarvellTokenSpaceGuid.PcdRamDiskSize + (Defines size of Ramdisk) --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel