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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::230; helo=mail-lf0-x230.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bchyVimM0NgjRhQGLEsFq/B2GfjXglDO8oazF5/2S5w=; b=HqG8Nixz7Zgm2Nqsg77ZWrvztqoTFiyKWrb2vk6jKqbZWJEBnozFTgmxig3JDiEcyG BuuaEqEm63Z8tMwBXEWBqhbHXyI+bsrAlfl4TmoVnNk3Hf0Ef/GQ8dG7q2XShyO1jqFb p8jCN56jM89TlROcG9mm4SBeU54SMQ3FCTLtQk16zz1NzAzOXUExzFR6TVE/cgPiSdMn Vxw44yuFEnL53zzVnx5kwLPkCY85KxWRjWK6PoTaC3PAOMA3FVDzqVl+8jbOX0SGr88h RLCmgpawz/U9TmcjSeVjjX5H2bQKwBQD0dJlQviaIaf+FqLsxaWdim7ySj4oHSe3Yz8c auzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bchyVimM0NgjRhQGLEsFq/B2GfjXglDO8oazF5/2S5w=; b=mIsUxszHNpJf6kSBbQ3uc8LsRjS3w7RiM1JyMQFbxmz/5HEMY/NAg+yrQVozmizv9J LB/v3kYdEyWJlz0WX7GXA9Uf9XRGu/F76D5osegQ1Jw8xbX+oKzvNPmB04H1D831PMD8 ZHShyDiXOPkGPhZOVesFvL1mWHuwuRCCeKE837F19aJYcrAZbQItbW9CkvHzVb0hl8JX ahHfWT2F3ObVf1v2jB7MDhCqJTK1+4NAEu9OnpBPq0OUrfxldz2/QZveNR2ah9HNUddv /o6FC2+KLliN7zmNIEMFhpEcZraLdTt1UAXVNmRJAnIkEeXzgsT6cFg87H/DgVOOSK0c Wf7A== X-Gm-Message-State: AMCzsaUf6EIN+6skUO48v/EUhsueeDYbIQ0xk31r9YyxxT1tvY9Ds2D+ 5PzVUsbotwy61QVDQx/kKBFecirlpno= X-Google-Smtp-Source: AOwi7QAGFdWuONFLU2RQVJpnNyeU1+ZNftGcTqYw7czRbv+NF3GmNrpEbh3WP9DyEd3eSxsL+J99Qw== X-Received: by 10.25.229.221 with SMTP id i90mr2253580lfk.71.1507568053521; Mon, 09 Oct 2017 09:54:13 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 9 Oct 2017 19:00:57 +0200 Message-Id: <1507568462-28775-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 08/13] Marvell/Armada: Modify GICC alias X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The GIC architecture mandates that the CPU interface, which consists of 2 consecutive 4 KB frames, can be mapped using separate mappings. Since this is problematic on 64 KB pages, the MMU-400 aliases each frame 16 times, and the two consecutive frames can be found at offset 0xf000. This patch is intended to expose correct GICC alias via MADT, once ACPI support is added. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 5071bd5..bd2336f 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -263,7 +263,14 @@ =20 # ARM Generic Interrupt Controller gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF0220000 + + # + # NOTE: the GIC architecture mandates that the CPU interface, which cons= ists + # of 2 consecutive 4 KB frames, can be mapped using separate mappings. + # Since this is problematic on 64 KB pages, the MMU-400 aliases each fra= me + # 16 times, and the two consecutive frames can be found at offset 0xf000 + # + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF022F000 =20 # ARM Architectural Timer Support gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|25000000 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel