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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:15 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22c; helo=mail-lf0-x22c.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dwv/Fr4N35nZLSf70S50ynqOxcSGgkWPv2OAlKpRD2Y=; b=ntVSscafm3410DgLHugvy96GiNc8Hvk5XK03bkEwFH/EzhlCBygQbCiOnNF6qh2/jC ervaDpVK1e4HI/hR91PW4o+2TFhRiEX24vLhu/0J/GZKZll2+6sk8UGVN1G1tZmamzd/ uz6Ve8jcR9COSvl95l0U5bg18Lp7SmT0LTQHkcnZXM+oCplqaRlwns2f0ZuT6njkuDes EfFzxHbTPfJw8E/p2qEniV3XLCz0XD9MGfSTyiQ3I0z5Yr7fybYkvzieHifPx7q+tvc0 R2aI10R4rdLoEb/0VJtSm/ZqO+O8jldHWrPw6gAxHtRGEqO/kO3db0fydIaOCRgQwEX7 MeGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dwv/Fr4N35nZLSf70S50ynqOxcSGgkWPv2OAlKpRD2Y=; b=QmikUH/lRSlt9aOwNLg3rtqeZwFZH4bi3KJIf5M1HiqGD1OWf1vwzfUKxGZRChiqPn h3/a0CMiZ+ee3YK+RZuEMUIJwYNnWnuULx8eSreEd7rSoFODh4PMJLJb4KALRmw90e9z Spt/1ihJH7h+xUWOyJHv1c3TJNgWonwbFdRxBF9cwNZQx/2znPT4+qodcyEX0QjtFWjr BljzBLENHeQTDc/TL6Wadx+A6b8s1Iqz/jm1GOkHk77XDN21G18GGW5cPecw0G0xhdFX UQaNMZXH2ow7eYNDpfdn8LcjzaxFXVIW3XN9I30NA3ntxTLadx/CYt6skBrf9oQdOsDX z5fg== X-Gm-Message-State: AMCzsaXYhWpvSbKb41Og4xlwcaxAetQ01EMiqrA+0j0NFug2CGrzmXOx 1afH3GyKyJpAVlSLGmOCXzU9EsnCaYw= X-Google-Smtp-Source: ABhQp+SrgtrPGzE9x2VNjlZstgkxKEsXFJiZl8bp26U04oYfhI3dx1FnuAG9YcFXWnAptzKeLVLqfg== X-Received: by 10.25.222.202 with SMTP id i71mr9874lfl.177.1507736476044; Wed, 11 Oct 2017 08:41:16 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:44 +0200 Message-Id: <1507736449-6073-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 3/8] Marvell/Armada: Remove custom reset library residues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When switching to generic PSCI reset library, obsolete parts of previous custom reset library (PCDs, documentation) remained. Remove them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada70x0.dsc | 4 ---- Platform/Marvell/Marvell.dec | 4 ---- Silicon/Marvell/Documentation/PortingGuide.txt | 9 --------- 3 files changed, 17 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 430803c..946c93e 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -138,9 +138,5 @@ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 } gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 - #ResetLib - gMarvellTokenSpaceGuid.PcdResetRegAddress|0xf06f0084 - gMarvellTokenSpaceGuid.PcdResetRegMask|0x1 - #RTC gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x1 } diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 78f5e53..434d6cb 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -188,10 +188,6 @@ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034 gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 =20 -#ResetLib - gMarvellTokenSpaceGuid.PcdResetRegAddress|0|UINT64|0x40000050 - gMarvellTokenSpaceGuid.PcdResetRegMask|0|UINT32|0x4000051 - #RTC gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 =20 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 66ec918..cbe3bed 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -383,15 +383,6 @@ Set pin 6 and 7 to 0xa function: gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } =20 =20 -MarvellResetSystemLib configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -This simple library allows to mask given bits in given reg at UEFI 'reset' -command call. These variables are configurable through PCDs: - - - gMarvellTokenSpaceGuid.PcdResetRegAddress - - gMarvellTokenSpaceGuid.PcdResetRegMask - - Ramdisk configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D There is one PCD available for Ramdisk configuration --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel