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charset="utf-8" Set global variables on Entry function based on CPUID checks. The variables replace Intel macros to allow support on AMD x86 systems. Specifically, the replaced macros are: 1) SRAM_SAVE_STATE_MAP_OFFSET 2) SMM_PSD_OFFSET Cc: Jiewen Yao Cc: Ruiyu Ni Cc: Michael D Kinney Cc: Jordan Justen Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++--- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++--- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43 +++++++++---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72 ++++++++++++++++++= ++-- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++---- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45 ++++++++++---- 12 files changed, 265 insertions(+), 99 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c b/UefiCpuPkg/PiSmmC= puDxeSmm/Ia32/Semaphore.c index 02a866b..7b2e5fb 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c @@ -1,15 +1,17 @@ /** @file -Semaphore mechanism to indicate to the BSP that an AP has exited SMM -after SMBASE relocation. + Semaphore mechanism to indicate to the BSP that an AP has exited SMM + after SMBASE relocation. =20 -Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
-This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD = License -which accompanies this distribution. The full text of the license may be = found at -http://opensource.org/licenses/bsd-license.php + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 @@ -38,7 +40,7 @@ SemaphoreHook ( =20 mRebasedFlag =3D RebasedFlag; =20 - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_= SAVE_STATE_MAP_OFFSET); + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + gSmmSm= ramStateMapOffset); mSmmRelocationOriginalAddress =3D (UINTN)HookReturnFromSmm ( CpuIndex, CpuState, diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCp= uDxeSmm/Ia32/SmiEntry.S index 3243a91..d25c099 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +29,9 @@ ASM_GLOBAL ASM_PFX(gSmbase) ASM_GLOBAL ASM_PFX(mXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) +ASM_GLOBAL ASM_PFX(gSmmPsdOffset) +ASM_GLOBAL ASM_PFX(gPsdGdtSize) +ASM_GLOBAL ASM_PFX(gPsdGdtPtr) =20 .equ MSR_IA32_MISC_ENABLE, 0x1A0 .equ MSR_EFER, 0xc0000080 @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 -.equ DSC_GDTPTR, 0x30 -.equ DSC_GDTSIZ, 0x38 -.equ DSC_CS, 14 -.equ DSC_DS, 16 -.equ DSC_SS, 18 +# .equ DSC_OFFSET, 0xfb00 +# .equ DSC_GDTPTR, 0x30 +# .equ DSC_GDTSIZ, 0x38 +# +.equ DSC_CS, 14 +.equ DSC_DS, 16 +.equ DSC_SS, 18 .equ DSC_OTHERSEG, 20 =20 .equ PROTECT_MODE_CS, 0x08 @@ -55,11 +61,11 @@ _SmiEntryPoint: .byte 0xbb # mov bx, imm16 .word _GdtDesc - _SmiEntryPoint + 0x8000 .byte 0x2e,0xa1 # mov ax, cs:[offset16] - .word DSC_OFFSET + DSC_GDTSIZ +ASM_PFX(gPsdGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ decl %eax movl %eax, %cs:(%edi) # mov cs:[bx], ax .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16] - .word DSC_OFFSET + DSC_GDTPTR +ASM_PFX(gPsdGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR movw %ax, %cs:2(%edi) movw %ax, %bp # ebp =3D GDT base .byte 0x66 @@ -167,7 +173,11 @@ NxeDone: movl %cr0, %ebx orl $0x080010023, %ebx # enable paging + WP + NE + MP = + PE movl %ebx, %cr0 - leal DSC_OFFSET(%edi),%ebx + + movl $ASM_PFX(gSmmPsdOffset), %ebx # leal DSC_OFFSET(%edi), %ebx + movzxw (%ebx), %esi + leal (%edi, %esi), %ebx + movw DSC_DS(%ebx),%ax movl %eax, %ds movw DSC_OTHERSEG(%ebx),%ax diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmm= CpuDxeSmm/Ia32/SmiEntry.asm index 8296f36..c9c471f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,9 +31,10 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h -DSC_GDTPTR EQU 30h -DSC_GDTSIZ EQU 38h +; DSC_OFFSET EQU 0fb00h +; DSC_GDTPTR EQU 30h +; DSC_GDTSIZ EQU 38h +; DSC_CS EQU 14 DSC_DS EQU 16 DSC_SS EQU 18 @@ -53,6 +56,9 @@ EXTERNDEF gSmbase:DWORD EXTERNDEF mXdSupported:BYTE EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE EXTERNDEF gSmiHandlerIdtr:FWORD +EXTERNDEF gSmmPsdOffset:WORD +EXTERNDEF gPsdGdtSize:WORD +EXTERNDEF gPsdGdtPtr:WORD =20 .code =20 @@ -62,11 +68,11 @@ _SmiEntryPoint: DB 0bbh ; mov bx, imm16 DW offset _GdtDesc - _SmiEntryPoint + 8000h DB 2eh, 0a1h ; mov ax, cs:[offset16] - DW DSC_OFFSET + DSC_GDTSIZ +gPsdGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ dec eax mov cs:[edi], eax ; mov cs:[bx], ax DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16] - DW DSC_OFFSET + DSC_GDTPTR +gPsdGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax mov bp, ax ; ebp =3D GDT base DB 66h @@ -173,7 +179,10 @@ mXdSupported DB 1 mov ebx, cr0 or ebx, 080010023h ; enable paging + WP + NE + MP + PE mov cr0, ebx - lea ebx, [edi + DSC_OFFSET] + + movzx esi, word ptr [gSmmPsdOffset] ; lea ebx, [edi + DSC_OFFS= ET] + lea ebx, [edi + esi] + mov ax, [ebx + DSC_DS] mov ds, eax mov ax, [ebx + DSC_OTHERSEG] diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index 4d2383f..666233b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -25,17 +27,18 @@ ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -%define DSC_GDTPTR 0x30 -%define DSC_GDTSIZ 0x38 -%define DSC_CS 14 -%define DSC_DS 16 -%define DSC_SS 18 -%define DSC_OTHERSEG 20 +; %define DSC_OFFSET 0xfb00 +; %define DSC_GDTPTR 0x30 +; %define DSC_GDTSIZ 0x38 +; +%define DSC_CS 14 +%define DSC_DS 16 +%define DSC_SS 18 +%define DSC_OTHERSEG 20 =20 %define PROTECT_MODE_CS 0x8 %define PROTECT_MODE_DS 0x20 -%define TSS_SEGMENT 0x40 +%define TSS_SEGMENT 0x40 =20 extern ASM_PFX(SmiRendezvous) extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -50,16 +53,28 @@ global ASM_PFX(gSmbase) global ASM_PFX(mXdSupported) extern ASM_PFX(gSmiHandlerIdtr) =20 +extern ASM_PFX(gSmmPsdOffset) +global ASM_PFX(gPsdGdtSize) +global ASM_PFX(gPsdGdtPtr) + SECTION .text =20 BITS 16 ASM_PFX(gcSmiHandlerTemplate): _SmiEntryPoint: mov bx, _GdtDesc - _SmiEntryPoint + 0x8000 - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ] + + mov eax, ASM_PFX(gPsdGdtSize) ; mov ax, [cs:DSC_OFFSET + D= SC_GDTSIZ] + mov si, [cs:eax] ; + mov ax, [cs:si] ; + dec ax mov [cs:bx], ax - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR] + + mov eax, ASM_PFX(gPsdGdtPtr) ; mov eax, [cs:DSC_OFFSET + = DSC_GDTPTR] + mov si, [cs:eax] ; + mov eax, [cs:si] ; + mov [cs:bx + 2], eax mov ebp, eax ; ebp =3D GDT base o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx] @@ -160,7 +175,10 @@ ASM_PFX(mXdSupported): DB 1 mov ebx, cr0 or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE mov cr0, ebx - lea ebx, [edi + DSC_OFFSET] + + movzx esi, word [ASM_PFX(gSmmPsdOffset)] ; lea ebx, [edi + DSC_= OFFSET] + lea ebx, [edi + esi] ; + mov ax, [ebx + DSC_DS] mov ds, eax mov ax, [ebx + DSC_OTHERSEG] @@ -205,5 +223,8 @@ ASM_PFX(SmiHandler): .7: rsm =20 +ASM_PFX(gPsdGdtSize): RESW 1 +ASM_PFX(gPsdGdtPtr) : RESW 1 + ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 282d2e6..ad7c811 100755 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -116,6 +116,31 @@ UINTN mSmmCpuSmramRangeCount; =20 UINT8 mPhysicalAddressBits; =20 +// +// Set default value for SMRAM offset +// from +// +UINT16 gSmmSmramStateMapOffset =3D SMRAM_SAVE_STATE_MAP_OFFSET; + +// +// Set default value for PSD offset in SMRAM +// +UINT16 gSmmPsdOffset =3D INTEL_SMM_PSD_OFFSET; + +// +// Constants relating to PROCESSOR_SMM_DESCRIPTOR +// +#define SMM_PSD_GDTPTR 0x30 +#define SMM_PSD_GDTSIZE 0x38 + + +// +// External global variables associated with SMI Handler Template +// +extern UINT16 gPsdGdtSize; +extern UINT16 gPsdGdtPtr; + + /** Initialize IDT to setup exception handlers for SMM. =20 @@ -407,7 +432,7 @@ SmmRelocateBases ( gcSmiInitGdtr.Limit =3D gcSmiGdtr.Limit; =20 U8Ptr =3D (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET); - CpuStatePtr =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMR= AM_SAVE_STATE_MAP_OFFSET); + CpuStatePtr =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + gSm= mSmramStateMapOffset); =20 // // Backup original contents at address 0x38000 @@ -500,6 +525,29 @@ SmmReadyToLockEventNotify ( } =20 /** + Determine if the standard CPU signature is "AuthenticAMD". + + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. + +**/ +STATIC +BOOLEAN +StandardSignatureIsAuthenticAMD ( + VOID + ) +{ + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && + RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && + RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); +} + +/** The module Entry Point of the CPU SMM driver. =20 @param ImageHandle The firmware allocated handle for the EFI image. @@ -547,6 +595,20 @@ PiCpuSmmEntry ( ); =20 // + // Override SMRAM offsets for AMD + // + if (StandardSignatureIsAuthenticAMD ()) { + gSmmSmramStateMapOffset =3D AMD_SMRAM_SAVE_STATE_MAP_OFFSET; + gSmmPsdOffset =3D AMD_SMM_PSD_OFFSET; + } + + // + // Initialize PSD global variables associated with SMI Handler + // + gPsdGdtSize =3D gSmmPsdOffset + SMM_PSD_GDTSIZE; + gPsdGdtPtr =3D gSmmPsdOffset + SMM_PSD_GDTPTR; + + // // Fix segment address of the long-mode-switch jump // if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { @@ -707,12 +769,12 @@ PiCpuSmmEntry ( =20 // // Compute tile size of buffer required to hold the CPU SMRAM Save State= Map, extra CPU - // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI= entry point. + // specific context start starts at SMBASE + gSmmPsdOffset, and the SMI = entry point. // This size is rounded up to nearest power of 2. // TileCodeSize =3D GetSmiHandlerSize (); TileCodeSize =3D ALIGN_VALUE(TileCodeSize, SIZE_4KB); - TileDataSize =3D (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof= (SMRAM_SAVE_STATE_MAP); + TileDataSize =3D (gSmmSmramStateMapOffset - gSmmPsdOffset) + sizeof (SMR= AM_SAVE_STATE_MAP); TileDataSize =3D ALIGN_VALUE(TileDataSize, SIZE_4KB); TileSize =3D TileDataSize + TileCodeSize - 1; TileSize =3D 2 * GetPowerOfTwo32 ((UINT32)TileSize); @@ -725,7 +787,7 @@ PiCpuSmmEntry ( // the SMI Handler size must be reduced or the size of the extra CPU spe= cific // context must be reduced. // - ASSERT (TileSize <=3D (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_= STATE_MAP) - SMM_HANDLER_OFFSET)); + ASSERT (TileSize <=3D (gSmmSmramStateMapOffset + sizeof (SMRAM_SAVE_STAT= E_MAP) - SMM_HANDLER_OFFSET)); =20 // // Allocate buffer for all of the tiles. @@ -783,7 +845,7 @@ PiCpuSmmEntry ( for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { mCpuHotPlugData.SmBase[Index] =3D (UINTN)Buffer + Index * Til= eSize - SMM_HANDLER_OFFSET; gSmmCpuPrivate->CpuSaveStateSize[Index] =3D sizeof(SMRAM_SAVE_STATE_MA= P); - gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); + gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + gSmmSmramStateMapOffset); gSmmCpuPrivate->Operation[Index] =3D SmmCpuNone; =20 if (Index < mNumberOfCpus) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 1cf85c1..8ad9d56 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -56,6 +56,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include =20 #include +#include #include =20 #include "CpuService.h" @@ -360,7 +361,21 @@ typedef struct { UINT32 MsrIndex; } MP_MSR_LOCK; =20 -#define SMM_PSD_OFFSET 0xfb00 +#define INTEL_SMM_PSD_OFFSET 0xfb00 + +// +// Definitions for AMD systems are based on contents of the +// AMD64 Architecture Programmer's Manual +// Volume 2: System Programming, Section 10 System-Management Mode +// +#define AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00 +#define AMD_SMM_PSD_OFFSET 0xfc00 + +// +// External global variables for SMRAM offsets +// +extern UINT16 gSmmSmramStateMapOffset; +extern UINT16 gSmmPsdOffset; =20 /// /// All global semaphores' pointer diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 3ad5256..8707424 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -1,13 +1,15 @@ /** @file =20 -Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD = License -which accompanies this distribution. The full text of the license may be = found at -http://opensource.org/licenses/bsd-license.php + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 @@ -703,7 +705,7 @@ PatchSmmSaveStateMap ( =20 TileCodeSize =3D GetSmiHandlerSize (); TileCodeSize =3D ALIGN_VALUE(TileCodeSize, SIZE_4KB); - TileDataSize =3D (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof= (SMRAM_SAVE_STATE_MAP); + TileDataSize =3D (gSmmSmramStateMapOffset - gSmmPsdOffset) + sizeof (SMR= AM_SAVE_STATE_MAP); TileDataSize =3D ALIGN_VALUE(TileDataSize, SIZE_4KB); TileSize =3D TileDataSize + TileCodeSize - 1; TileSize =3D 2 * GetPowerOfTwo32 ((UINT32)TileSize); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmC= puDxeSmm/SmramSaveState.c index 3188d43..1f460b7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -1,14 +1,16 @@ /** @file -Provides services to access SMRAM Save State Map + Provides services to access SMRAM Save State Map =20 -Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD = License -which accompanies this distribution. The full text of the license may be = found at -http://opensource.org/licenses/bsd-license.php + Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 @@ -690,7 +692,7 @@ InstallSmiHandler ( // // Initialize PROCESSOR_SMM_DESCRIPTOR // - Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFF= SET); + Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + gSmmPsdOffs= et); CopyMem (Psd, &gcPsd, sizeof (gcPsd)); Psd->SmmGdtPtr =3D (UINT64)GdtBase; Psd->SmmGdtSize =3D (UINT32)GdtSize; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c b/UefiCpuPkg/PiSmmCp= uDxeSmm/X64/Semaphore.c index 6dbcb08..3f52c7a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c @@ -1,15 +1,17 @@ /** @file -Semaphore mechanism to indicate to the BSP that an AP has exited SMM -after SMBASE relocation. + Semaphore mechanism to indicate to the BSP that an AP has exited SMM + after SMBASE relocation. =20 -Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
-This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD = License -which accompanies this distribution. The full text of the license may be = found at -http://opensource.org/licenses/bsd-license.php + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 @@ -51,7 +53,7 @@ SemaphoreHook ( mRebasedFlag =3D RebasedFlag; mRebasedFlagAddr32 =3D (UINT32)(UINTN)mRebasedFlag; =20 - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_= SAVE_STATE_MAP_OFFSET); + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + gSmmSm= ramStateMapOffset); mSmmRelocationOriginalAddress =3D HookReturnFromSmm ( CpuIndex, CpuState, diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpu= DxeSmm/X64/SmiEntry.S index 600d862..c3405ec 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S @@ -1,6 +1,8 @@ #-------------------------------------------------------------------------= ----- # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -26,6 +28,9 @@ ASM_GLOBAL ASM_PFX(gSmiStack) ASM_GLOBAL ASM_PFX(gSmbase) ASM_GLOBAL ASM_PFX(mXdSupported) ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) +ASM_GLOBAL ASM_PFX(gSmmPsdOffset) +ASM_GLOBAL ASM_PFX(gPsdGdtSize) +ASM_GLOBAL ASM_PFX(gPsdGdtPtr) =20 .equ MSR_IA32_MISC_ENABLE, 0x1A0 .equ MSR_EFER, 0xc0000080 @@ -34,12 +39,13 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) # # Constants relating to PROCESSOR_SMM_DESCRIPTOR # -.equ DSC_OFFSET, 0xfb00 -.equ DSC_GDTPTR, 0x30 -.equ DSC_GDTSIZ, 0x38 -.equ DSC_CS, 14 -.equ DSC_DS, 16 -.equ DSC_SS, 18 +# .equ DSC_OFFSET, 0xfb00 +# .equ DSC_GDTPTR, 0x30 +# .equ DSC_GDTSIZ, 0x38 +# +.equ DSC_CS, 14 +.equ DSC_DS, 16 +.equ DSC_SS, 18 .equ DSC_OTHERSEG, 20 # # Constants relating to CPU State Save Area @@ -49,9 +55,9 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) =20 .equ PROTECT_MODE_CS, 0x08 .equ PROTECT_MODE_DS, 0x20 -.equ LONG_MODE_CS, 0x38 -.equ TSS_SEGMENT, 0x40 -.equ GDT_SIZE, 0x50 +.equ LONG_MODE_CS, 0x38 +.equ TSS_SEGMENT, 0x40 +.equ GDT_SIZE, 0x50 =20 .text =20 @@ -70,12 +76,12 @@ _SmiEntryPoint: # fix GDT descriptor # .byte 0x2e,0xa1 # mov ax, cs:[offset16] - .word DSC_OFFSET + DSC_GDTSIZ +ASM_PFX(gPsdGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ .byte 0x48 # dec ax .byte 0x2e movl %eax, (%rdi) # mov cs:[bx], ax .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16] - .word DSC_OFFSET + DSC_GDTPTR +ASM_PFX(gPsdGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR .byte 0x2e movw %ax, 2(%rdi) .byte 0x66,0x2e @@ -182,7 +188,11 @@ Base: LongMode: # long mode (64-bit code) starts h= ere movabsq $ASM_PFX(gSmiHandlerIdtr), %rax lidt (%rax) - lea (DSC_OFFSET)(%rdi), %ebx + + movl $ASM_PFX(gSmmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi), %= ebx + movzxw (%ebx), %rsi + leal (%rdi, %rsi), %ebx + movw DSC_DS(%rbx), %ax movl %eax,%ds movw DSC_OTHERSEG(%rbx), %ax diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/SmiEntry.asm index c74f82a..72eeb1a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -31,6 +33,10 @@ EXTERNDEF gSmiStack:DWORD EXTERNDEF gSmbase:DWORD EXTERNDEF mXdSupported:BYTE EXTERNDEF gSmiHandlerIdtr:FWORD +EXTERNDEF gSmmPsdOffset:WORD +EXTERNDEF gPsdGdtSize:WORD +EXTERNDEF gPsdGdtPtr:WORD + =20 MSR_IA32_MISC_ENABLE EQU 1A0h MSR_EFER EQU 0c0000080h @@ -39,9 +45,10 @@ MSR_EFER_XD EQU 0800h ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -DSC_OFFSET EQU 0fb00h -DSC_GDTPTR EQU 30h -DSC_GDTSIZ EQU 38h +: DSC_OFFSET EQU 0fb00h +; DSC_GDTPTR EQU 30h +; DSC_GDTSIZ EQU 38h +; DSC_CS EQU 14 DSC_DS EQU 16 DSC_SS EQU 18 @@ -73,12 +80,12 @@ _SmiEntryPoint: DW offset _GdtDesc - _SmiEntryPoint + 8000h ; bx =3D GdtDesc off= set ; fix GDT descriptor DB 2eh, 0a1h ; mov ax, cs:[offset16] - DW DSC_OFFSET + DSC_GDTSIZ +gPsdGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ DB 48h ; dec ax DB 2eh mov [rdi], eax ; mov cs:[bx], ax DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16] - DW DSC_OFFSET + DSC_GDTPTR +gPsdGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR DB 2eh mov [rdi + 2], ax ; mov cs:[bx + 2], eax DB 66h, 2eh @@ -177,7 +184,10 @@ Base: @LongMode: ; long mode (64-bit code) starts h= ere mov rax, offset gSmiHandlerIdtr lidt fword ptr [rax] - lea ebx, [rdi + DSC_OFFSET] + + movzx rsi, word ptr [gSmmPsdOffset] ; lea ebx, [rdi + DSC_OFFS= ET] + lea ebx, [rdi + rsi] ; + mov ax, [rbx + DSC_DS] mov ds, eax mov ax, [rbx + DSC_OTHERSEG] diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index c3c094f..3a841c9 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,7 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -29,12 +31,13 @@ ; ; Constants relating to PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -%define DSC_GDTPTR 0x30 -%define DSC_GDTSIZ 0x38 -%define DSC_CS 14 -%define DSC_DS 16 -%define DSC_SS 18 +; %define DSC_OFFSET 0xfb00 +; %define DSC_GDTPTR 0x30 +; %define DSC_GDTSIZ 0x38 +; +%define DSC_CS 14 +%define DSC_DS 16 +%define DSC_SS 18 %define DSC_OTHERSEG 20 ; ; Constants relating to CPU State Save Area @@ -44,9 +47,9 @@ =20 %define PROTECT_MODE_CS 0x8 %define PROTECT_MODE_DS 0x20 -%define LONG_MODE_CS 0x38 -%define TSS_SEGMENT 0x40 -%define GDT_SIZE 0x50 +%define LONG_MODE_CS 0x38 +%define TSS_SEGMENT 0x40 +%define GDT_SIZE 0x50 =20 extern ASM_PFX(SmiRendezvous) extern ASM_PFX(gSmiHandlerIdtr) @@ -60,6 +63,10 @@ global ASM_PFX(gSmiCr3) global ASM_PFX(gcSmiHandlerTemplate) global ASM_PFX(gcSmiHandlerSize) =20 +extern ASM_PFX(gSmmPsdOffset) +global ASM_PFX(gPsdGdtSize) +global ASM_PFX(gPsdGdtPtr) + DEFAULT REL SECTION .text =20 @@ -67,10 +74,18 @@ BITS 16 ASM_PFX(gcSmiHandlerTemplate): _SmiEntryPoint: mov bx, _GdtDesc - _SmiEntryPoint + 0x8000 - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ] + + mov eax, ASM_PFX(gPsdGdtSize) ; mov ax, [cs:DSC_OFFSET + D= SC_GDTSIZ] + mov si, [cs:eax] ; + mov ax, [cs:si] ; + dec ax mov [cs:bx], ax - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR] + + mov eax, ASM_PFX(gPsdGdtPtr) ; mov eax, [cs:DSC_OFFSET + = DSC_GDTPTR] + mov si, [cs:eax] ; + mov eax, [cs:si] ; + mov [cs:bx + 2], eax o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx] mov ax, PROTECT_MODE_CS @@ -160,7 +175,10 @@ Base: @LongMode: ; long mode (64-bit code) starts h= ere mov rax, ASM_PFX(gSmiHandlerIdtr) lidt [rax] - lea ebx, [rdi + DSC_OFFSET] + + movzx rsi, word [ASM_PFX(gSmmPsdOffset)] ; lea ebx, [rdi + DSC_= OFFSET] + lea ebx, [rdi + rsi] + mov ax, [rbx + DSC_DS] mov ds, eax mov ax, [rbx + DSC_OTHERSEG] @@ -220,5 +238,8 @@ _SmiHandler: .1: rsm =20 +ASM_PFX(gPsdGdtSize): RESW 1 +ASM_PFX(gPsdGdtPtr) : RESW 1 + gcSmiHandlerSize DW $ - _SmiEntryPoint =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel