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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id i62sm746461lji.42.2017.10.25.08.18.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Oct 2017 08:18:57 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=errthaIWrru5Bnp1B7cVZDvmBf6lHkerMn625pOvuaM=; b=UVrNM7DIiMGh9ZguXzWZxhMeOWY1Alj08tBNeZs3yjbSpWcFjIBEq6HAZ7P7gl5J8z pX93WRAZugGsZUMP2p8bCXbaH50wDqe/sDf2dEYR09ZDHt6eoPMsCSIjdBscsk2v+A8d +alN/sRdu4LOhcSMv+SPdVJmDeel/E1RJxjX6wOroEp16MCkpwagmFBBFLOj9XGCDXBC I8RZZuEBG4v5xLedFFXgmIZw/BujfS6W/xuRVM4ip5SNpHB71aAmS1PHpRoDBnM/Ygg3 8XfXimn8eoBbXnx08ViXYgofhaKKGpyDzGSh/fNl95SFkZnxblSEw+bApTiPDS2ulEXv Aowg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=errthaIWrru5Bnp1B7cVZDvmBf6lHkerMn625pOvuaM=; b=aqgf98ffIKVjHzos38B34udC1lQbL/gUc3gI2/K0bID2i/mr2tFWONjIzya60KApen WHHR6znBCCXW9OjIlKGWesecr5v1DqxZ60C2/g+29AbH2aQz6pT8keaUBwRTHm3hKRPH drw4uY9fnRYpf9VfEGHjJOwDYPv5HTzRw4tVAL+Oj1y3ogS8b+hWgI/kgWETYmQYy8bu uZ4feJrwcFh+UBQ1NK+uyWjEcXBBbAGs+m+COfsVVst6h7g4gwFPdQ8pv9ixk2/XLbjw GrVkb2WiKwSNlwhpqqhcF9VnjkWEmsw9vvPB2jFo47f0PzY75W2R90Gg9ke3Iv5WpVFr O94w== X-Gm-Message-State: AMCzsaWugSVgS4BtSYMxyOQUhnUz72iuhpIFeU9G8y5eWbW80Mgj0ld3 2JoX7YxiBP0G67b6srjenXvzfT6FGyg= X-Google-Smtp-Source: ABhQp+SLZiYTLzk3tvI3zjr5w9MxjbjIBTPkZgRlOivSHyh8ySzQl+ojco8lu1ORXsBVC2UmzxBE3w== X-Received: by 10.46.20.3 with SMTP id u3mr8098952ljd.164.1508944738356; Wed, 25 Oct 2017 08:18:58 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 17:18:13 +0200 Message-Id: <1508944693-16315-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508944693-16315-1-git-send-email-mw@semihalf.com> References: <1508944693-16315-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 6/8] Marvell/Armada: Enable dynamic DRAM size detection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Instead of using hardcoded value in PcdSystemMemorySize PCD, obtain DRAM size directly from SoC registers, which are filled by firmware during early initialization stage. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 61 ++++= +++++++++++++++- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 25 ++++= ++++ 2 files changed, 85 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem= .c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c index 978e4d3..f384415 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c @@ -50,6 +50,59 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. =20 STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY= _MAP_DESCRIPTORS]; =20 +// Obtain DRAM size basing on register values filled by early firmware. +STATIC +UINT64 +GetDramSize ( + IN OUT UINT64 *MemSize + ) +{ + UINT64 BaseAddr; + UINT8 RegionCode; + UINT8 Cs; + + *MemSize =3D 0; + + for (Cs =3D 0; Cs < DRAM_MAX_CS_NUM; Cs++) { + + /* Exit loop on first disabled DRAM CS */ + if (!DRAM_CS_ENABLED (Cs)) { + break; + } + + /* + * Sanity check for base address of next DRAM block. + * Only continuous space will be used. + */ + BaseAddr =3D GET_DRAM_REGION_BASE (Cs); + if (BaseAddr !=3D *MemSize) { + DEBUG ((DEBUG_ERROR, + "%a: DRAM blocks are not contiguous, limit size to 0x%llx\n", + __FUNCTION__, + *MemSize)); + return EFI_SUCCESS; + } + + /* Decode area length for current CS from register value */ + RegionCode =3D GET_DRAM_REGION_SIZE_CODE (Cs); + + if (DRAM_REGION_SIZE_EVEN (RegionCode)) { + *MemSize +=3D GET_DRAM_REGION_SIZE_EVEN (RegionCode); + } else if (DRAM_REGION_SIZE_ODD (RegionCode)) { + *MemSize +=3D GET_DRAM_REGION_SIZE_ODD (RegionCode); + } else { + DEBUG ((DEBUG_ERROR, + "%a: Invalid memory region code (0x%x) for CS#%d\n", + __FUNCTION__, + RegionCode, + Cs)); + return EFI_INVALID_PARAMETER; + } + } + + return EFI_SUCCESS; +} + /** Return the Virtual Memory Map of your platform =20 @@ -72,12 +125,18 @@ ArmPlatformGetVirtualMemoryMap ( UINT64 MemHighSize; UINT64 ConfigSpaceBaseAddr; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + EFI_STATUS Status; =20 ASSERT (VirtualMemoryMap !=3D NULL); =20 ConfigSpaceBaseAddr =3D FixedPcdGet64 (PcdConfigSpaceBaseAddress); =20 - MemSize =3D FixedPcdGet64 (PcdSystemMemorySize); + // Obtain total memory size from the hardware. + Status =3D GetDramSize (&MemSize); + if (EFI_ERROR (Status)) { + MemSize =3D FixedPcdGet64 (PcdSystemMemorySize); + DEBUG ((DEBUG_ERROR, "Limit total memory size to %d MB\n", MemSize / 1= 024 / 1024)); + } =20 if (DRAM_REMAP_ENABLED) { MemLowSize =3D MIN (DRAM_REMAP_TARGET, MemSize); diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem= .h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h index 8101cf3..cc30e4a 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h @@ -46,3 +46,28 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB #define DRAM_REMAP_TARGET \ (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS) + +#define DRAM_CH0_MMAP_LOW_REG(cs) (0xf0020200 + (cs) * 0x8) +#define DRAM_CS_VALID_ENABLED_MASK 0x1 +#define DRAM_AREA_LENGTH_OFFS 16 +#define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS) +#define DRAM_START_ADDRESS_L_OFFS 23 +#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFF= S) +#define DRAM_CH0_MMAP_HIGH_REG(cs) (0xf0020204 + (cs) * 0x8) +#define DRAM_START_ADDR_HTOL_OFFS 32 + +#define DRAM_MAX_CS_NUM 8 + +#define DRAM_CS_ENABLED(Cs) \ + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_CS_VALID_ENABLED= _MASK) +#define GET_DRAM_REGION_BASE(Cs) \ + ((UINT64)MmioRead32 (DRAM_CH0_MMAP_HIGH_REG ((Cs))) << \ + DRAM_START_ADDR_HTOL_OFFS) | \ + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_START_ADDRESS_L_= MASK); +#define GET_DRAM_REGION_SIZE_CODE(Cs) \ + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG ((Cs))) & \ + DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS +#define DRAM_REGION_SIZE_EVEN(C) (((C) >=3D 7) && ((C) <=3D 26)) +#define GET_DRAM_REGION_SIZE_EVEN(C) ((UINT64)1 << ((C) + 16)) +#define DRAM_REGION_SIZE_ODD(C) ((C) <=3D 4) +#define GET_DRAM_REGION_SIZE_ODD(C) ((UINT64)0x18000000 << (C)) --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel