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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:34 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NciNr3Ya+JDiOR5JmP43mlANvMK7QVnBlNN5Io6Jve0=; b=XiCse4P5RLt0KZqbh/q6QEegBTi+8VOmADy3DG3nesr+5LTQl6EkE3z8D08GoykceC /7TymwZkkdfUp/APNuILVxo7587tBo0Q6mReN0bWnv5V751+hDUpEUe/m0vutMrFoYjj WC+6IVlVbOazqPLCJJVOejTme9bU7gDly9LIIGRafJldMIVV8Hv0VoK9NTLQ/XNrfnkE yT4fmlrVj7/BUCX47M+wbpuHoCUDJG7YwC9yOjmyx7VuNf3BqKFNqQYEuCwcxGLc1GV6 GC/NOLGg/RpdyeBTluJ/ddQzbdgr1+IDQNtkF9hCfygvw47MqisHvoBo+OI95dn+Smop h7cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NciNr3Ya+JDiOR5JmP43mlANvMK7QVnBlNN5Io6Jve0=; b=CFCx5HZR45F973BYpwb/GAaLTMcy3ls32A+K/ECDbn9IZ06LTQxP6XrdBNC/2zV0Wr 4EePypjFL+BNuddjYnIdYuCktU559LQGN4+LhHcii1f+GykRXKPNSqbdb7y2BPXoBjv9 KO0w8qLHVD4mWonN4HIaQvHTkK7QVpLPHjSUI/y75kYmmdLW7m4wAC9xWKMCgQUw+9Ip rmVCxTDXxlqc4/WQXJ94px8jr6jk9WOJ3Q2Z9ZypT4pHbrqvUz31BdNLFII9QByJwqzX +0UToTX0VAA5hViEWByiV30auZdy17C6WyNzxA0jllzZQDAsVCnsNGzcm2LfN1l+fLIC H+cg== X-Gm-Message-State: AMCzsaX12cW/bApd/+POWobi2ub8SNaf47fbCEppo7Xat4vhh4O6KhOg 1AtiTQGAY//0E40HrGCe5UKpE9xIc4I= X-Google-Smtp-Source: ABhQp+RsNdI4N8iCq8MBUKLmwHeZvwYFZmZTvnPgfT/c6fWvg2SPEtffEqZWJcefLLzLSbFiXm+1WA== X-Received: by 10.25.153.136 with SMTP id b130mr347040lfe.233.1509121955207; Fri, 27 Oct 2017 09:32:35 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:44 +0200 Message-Id: <1509121913-12937-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 01/10] Marvell/Drivers: MvI2cDxe: Abort transaction immediately upon fail X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, David Greeson , neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: David Greeson Although the I2C transaction routines were prepared to return their status, they were never used. This could cause bus lock-up e.g. in case of failing to send a slave address, the data transfer was attempted to be continued anyway. This patch fixes faulty behavior by checking transaction status and stopping it immediately, once the fail is detected. On the occasion fix style around modified functions calls. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: David Greeson [Style adjustment and cleanup] Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 62 +++++++++++++------- 1 file changed, 41 insertions(+), 21 deletions(-) diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index d85ee0b..b4599d2 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -565,6 +565,7 @@ MvI2cStartRequest ( UINTN Transmitted; I2C_MASTER_CONTEXT *I2cMasterContext =3D I2C_SC_FROM_MASTER(This); EFI_I2C_OPERATION *Operation; + EFI_STATUS Status =3D EFI_SUCCESS; =20 ASSERT (RequestPacket !=3D NULL); ASSERT (I2cMasterContext !=3D NULL); @@ -574,33 +575,52 @@ MvI2cStartRequest ( ReadMode =3D Operation->Flags & I2C_FLAG_READ; =20 if (Count =3D=3D 0) { - MvI2cStart ( I2cMasterContext, - (SlaveAddress << 1) | ReadMode, - I2C_TRANSFER_TIMEOUT - ); + Status =3D MvI2cStart (I2cMasterContext, + (SlaveAddress << 1) | ReadMode, + I2C_TRANSFER_TIMEOUT); } else if (!(Operation->Flags & I2C_FLAG_NORESTART)) { - MvI2cRepeatedStart ( I2cMasterContext, - (SlaveAddress << 1) | ReadMode, - I2C_TRANSFER_TIMEOUT - ); + Status =3D MvI2cRepeatedStart (I2cMasterContext, + (SlaveAddress << 1) | ReadMode, + I2C_TRANSFER_TIMEOUT); } =20 + /* I2C transaction was aborted, so stop further transactions */ + if (EFI_ERROR (Status)) { + MvI2cStop (I2cMasterContext); + break; + } + + /* + * If sending the slave address was successful, + * proceed to read or write section. + */ if (ReadMode) { - MvI2cRead ( I2cMasterContext, - Operation->Buffer, - Operation->LengthInBytes, - &Transmitted, - Count =3D=3D 1, - I2C_TRANSFER_TIMEOUT - ); + Status =3D MvI2cRead (I2cMasterContext, + Operation->Buffer, + Operation->LengthInBytes, + &Transmitted, + Count =3D=3D 1, + I2C_TRANSFER_TIMEOUT); + Operation->LengthInBytes =3D Transmitted; } else { - MvI2cWrite ( I2cMasterContext, - Operation->Buffer, - Operation->LengthInBytes, - &Transmitted, - I2C_TRANSFER_TIMEOUT - ); + Status =3D MvI2cWrite (I2cMasterContext, + Operation->Buffer, + Operation->LengthInBytes, + &Transmitted, + I2C_TRANSFER_TIMEOUT); + Operation->LengthInBytes =3D Transmitted; } + + /* + * The I2C read or write transaction failed. + * Stop the I2C transaction. + */ + if (EFI_ERROR (Status)) { + MvI2cStop (I2cMasterContext); + break; + } + + /* Check if there is any more data to be sent */ if (Count =3D=3D RequestPacket->OperationCount - 1) { MvI2cStop ( I2cMasterContext ); } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 02:21:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509121963697373.28796727365796; Fri, 27 Oct 2017 09:32:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AD41421CEB140; Fri, 27 Oct 2017 09:28:52 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BB4702034A873 for ; Fri, 27 Oct 2017 09:28:51 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id n69so8032194lfn.2 for ; Fri, 27 Oct 2017 09:32:39 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:36 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=62MZxKGrLwDNAL7VVdwiAB+eOx/7pEIj1NCX96CROZs=; b=ocQk3KjTJGTBp1Eo9mPp/MDsk7hq5B2FjC8JInTPiLFnRSC6W2LwUzbC73SOqmGa4+ MKGF53Q85XTAtSHmpvLWheeD525X2OmitnswGVUgcijyms9+DIWSS/6KL8K6C/2alOTZ Di4kU9GOrEbjZEeWguPZazWUXxCsTg4fVWtNpzeyhkdOED2Ctk+/0R4tlaJMNMf6G/+k U+fd/nP+hwUDD634IqXP26ss8VvZT/X+NUH7Q/XmR1QLQbx6Ev6lgDhygTq79FBKRPbo 13YbT7BdyCttOsi82GAE0fgRTjLFUmPConMZ5obl570ds6yPMN0QB4WMdWp+QiT7eKTC 0mrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=62MZxKGrLwDNAL7VVdwiAB+eOx/7pEIj1NCX96CROZs=; b=cunan0vNwWBtZKOE7YzMI6GZHDbNYvV9iBAPlyUk007NR61B/paZhO0fcvwFT5Rq49 2Ez+gLm6UKn0fzMIq7dtRTWmK7IpAf/57d3JysVD0PCTnzvbDVyDbRmkx0JVPL0FtJHO 04Jt5iOTXuJlCPnkv2SYWn8ZFer7R5BT/FH973/ngo0Jjm2MXViWTe16q3tZtPQoK3Zo yWvTPLo53oEBMpElgFI1a88wH22JaHbpRFqiQQtXVz9GN+k7pJHJFnFx8/uz8v2Lhdx9 lxq8Can1VsMcbSfZ0JAO+2oNum8i+sC2iptxCi60nfhp09UTvmQD/lZC3TO9DeoRiESG ZQVA== X-Gm-Message-State: AMCzsaUI9ZAfTBCMZwLSnYFYuqtqVdAwj3m/IEJolesfz+mbgGIBhawj 2UzrdPwcDzGvMf9O4FTla/lrOic7yPE= X-Google-Smtp-Source: ABhQp+QByB7KFyvCP0zulcwuPMHCy5kXs8jFla7qB2GPfxLy648P9fxptZ5K0ZoCiv6zPjNeluXLXQ== X-Received: by 10.25.165.212 with SMTP id o203mr355924lfe.204.1509121957110; Fri, 27 Oct 2017 09:32:37 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:45 +0200 Message-Id: <1509121913-12937-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 02/10] Marvell/Drivers: MvI2cDxe: Fix returning status in MvI2cStartRequest X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In MvI2cStartRequest the status was assigned to the variable without dereferencing a pointer. Fix it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index b4599d2..a62383f 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -627,7 +627,7 @@ MvI2cStartRequest ( } =20 if (I2cStatus !=3D NULL) - I2cStatus =3D EFI_SUCCESS; + *I2cStatus =3D EFI_SUCCESS; if (Event !=3D NULL) gBS->SignalEvent(Event); return EFI_SUCCESS; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 02:21:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509121966911123.82761609688464; Fri, 27 Oct 2017 09:32:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E9E9321CEB13A; Fri, 27 Oct 2017 09:28:56 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1984821CEB139 for ; Fri, 27 Oct 2017 09:28:53 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id a132so8025073lfa.7 for ; Fri, 27 Oct 2017 09:32:40 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:37 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XOFO9TtAZ3RTSamL64u3tOj918MQw0Favl3owH37cuk=; b=O1+9zvhjkdUvwVF3jphPpPsJHcyQ6rPYswsrTRmYs+3q0z4Kh/dscOstMR0RhKAQ23 8CdcxwQO7PPRc5yPW1XU9tG4tvcp4q8zZHJ7P6+PaIlrBckVjqnVs4LLJlSKPINUqs5I ODn1TQ3NKqzj66nwgXsEXe9D8g7kYD3ny/o5F8baSbBftX9Kilivqeo0uRCBGV/ochp2 wpc1Cb8LPrW4hT3rUaZKE23pGscqLKDo8mjPY6La22tj5KLpSZaOCp62rxXvCVEVks97 PoIOmaWu6ut5lkl7xIOY9gMksgPVLrHZMqCN7M3DNP0XVuwKwdoHI54yQ6vqfD7tYs1Y bSiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XOFO9TtAZ3RTSamL64u3tOj918MQw0Favl3owH37cuk=; b=BzrKcob3tzqIKNc2MO/+voXTikFa8KHAidpIs4nbGbktpSOF1eZ/fcxUc02DZ5oB5Y 6u8LGllGQ2Fo8WRwBOoIGOrBQw6pk3MkSL73h65kdECiEjaC8J4uEmeB0O0TryQEwecF j2tJXal8mDGv0BBS+1/snueHDHjce/uV2Y+xOqpEyOmX93XjpnsjC0JYoa7jWGgyQI+j Q8Jl1kA/FGlS8j/n/cIgGTbUyagbYcGCI4iPdO5dRQiWAnKU4Ta1ighs6wSMu7eBVaOR HZDBxaahaBvmutJnXNZKG37GSW6o7ndNh2bEcUSz+lszCUhYkEnSO1KccG68/bRYixyF h25w== X-Gm-Message-State: AMCzsaXW1uhpS6NI2yQZB0EvluOhfBpNYO4nZ0nLBtRKVOxWLpcUOPZN WsnKz/rME3xJtfdnJiABFSo5MAslgHU= X-Google-Smtp-Source: ABhQp+T3oSV/GdGxn/I4KXHuSETZPcuujALvHDq2Ec4tHUkQbu6URgEmKM/0koOpGvU7+/4vvA0lDg== X-Received: by 10.25.76.212 with SMTP id z203mr306346lfa.39.1509121958514; Fri, 27 Oct 2017 09:32:38 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:46 +0200 Message-Id: <1509121913-12937-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 03/10] Marvell/Drivers: MvI2cDxe: Reduce bus occupation time X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, David Greeson , neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: David Greeson During each transaction start, clearing the I2C_CONTROL_FLAG was surrounded by 3 uncoditional stalls. This was not necessary, so replace them with one busy-wait loop, whose polling count could be also safely reduced. Above improvements result in faster transfer initialization and allow to reduce the I2C bus occupation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: David Greeson Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 6 +----- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.h | 2 +- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index a62383f..d6f590d 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -243,9 +243,8 @@ MvI2cClearIflg ( IN I2C_MASTER_CONTEXT *I2cMasterContext ) { - gBS->Stall(I2C_OPERATION_TIMEOUT); + MvI2cPollCtrl (I2cMasterContext, I2C_OPERATION_TIMEOUT, I2C_CONTROL_IFLG= ); MvI2cControlClear(I2cMasterContext, I2C_CONTROL_IFLG); - gBS->Stall(I2C_OPERATION_TIMEOUT); } =20 /* Timeout is given in us */ @@ -295,9 +294,6 @@ MvI2cLockedStart ( MvI2cClearIflg(I2cMasterContext); } =20 - /* Without this delay we Timeout checking IFLG if the Timeout is 0 */ - gBS->Stall(I2C_OPERATION_TIMEOUT); - if (MvI2cPollCtrl(I2cMasterContext, Timeout, I2C_CONTROL_IFLG)) { DEBUG((DEBUG_ERROR, "MvI2cDxe: Timeout sending %sSTART condition\n", Mask =3D=3D I2C_STATUS_START ? "" : "repeated ")); diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.h b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.h index 028fd54..3c9beaf 100644 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.h +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.h @@ -68,7 +68,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #define I2C_SOFT_RESET 0x1c #define I2C_TRANSFER_TIMEOUT 10000 -#define I2C_OPERATION_TIMEOUT 1000 +#define I2C_OPERATION_TIMEOUT 100 =20 #define I2C_UNKNOWN 0x0 #define I2C_SLOW 0x1 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 02:21:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509121970506789.1712565099496; Fri, 27 Oct 2017 09:32:50 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 31EDD21EA15A2; Fri, 27 Oct 2017 09:28:57 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5F02721CEB12D for ; Fri, 27 Oct 2017 09:28:54 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id r129so8014766lff.8 for ; Fri, 27 Oct 2017 09:32:41 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:39 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TUMONFAKMpiQWShizYJCsesNltdW4p7QVVldO0pf3Wo=; b=VS0KtZ2v8P8npaVl75k5DUb4sc/roXH9RPWtEFn4itkqq4VkA6hraP/CATz0T1urYT 6f9Uud+jmd37ICF4AVP7IvxTW1wG/p2LWJrmrSj32+SRVbl3kKDvdzoKSy0IaJel7tgl EvX4V78rjkq7uEFc+ALzRzHtyQOE43r0i9uxgvI/UX0iAqqrchbhv13pYiVLeeDMr4ZG S15baoeZFWvlXXVHGpxYITaSkwmV8Ty9Q1O6txeKObCWlCTLqp6S7WyJdiljQUAiKaO3 LsN9WqvHpOU/Ow3PuqkYJ+wIUpZQF1KYI2WtMnWUn4DgkJdZZmc6ae5tv5wUpChkeyLu v2jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TUMONFAKMpiQWShizYJCsesNltdW4p7QVVldO0pf3Wo=; b=F7zFxbCEqs06Y7S1orwbOWnaLgwX7x/wAy647WWc75bNmxXugTFulEERfZDjWyb2pQ nH/jaDKc0N4WaXas2Rtpm9/JeayXcPiQgcT+KfAU0OOCqA03z1gO+Xxmx31MyjlNcLvB 6ITlCfdDzsy9zixMTD6eRXCUTtFVZ+XKUOjQfwwYk8Ujao2LyzPFsXhpYoRXEO3jsIXe zek0wakE44M+BwR77qqMxJEKQ6wS9VRWHH/duHDloRpI0bq0pTSaHZPFtMllHY4VOLsY vTR+ALYQzd4K33LDuZ2g+Q1fv9fPiYT3vyfblz1fXcjg/fI8PLFD3bl6WlpkhiTdeaW+ lTag== X-Gm-Message-State: AMCzsaUyk4hksfVKSFLdjavOGP43XlboU47TAOAo2x8OONu/ZoYWPMGc ef6y1AlAaYA7IVVDy1gxlnU5TDi1xQ0= X-Google-Smtp-Source: ABhQp+QRhnY7v144awrHoWmX4Y7gQkcVq6fmQXWI5/uuvSPM/D6bjnTKmFgaguTHTOpHvSjWBRilVg== X-Received: by 10.25.22.28 with SMTP id m28mr357085lfi.185.1509121959927; Fri, 27 Oct 2017 09:32:39 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:47 +0200 Message-Id: <1509121913-12937-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 04/10] Marvell/Library: MppLib: Prevent overwriting PCD values X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, Joe Zhou , ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Joe Zhou After enabling dynamic PCDs, it is possible to reconfigure MPP during platform initialization. It occurred that due to a faulty way of passing temporary values, information obtained from PCDs was overwritten. This patch fixes the issue, which on the occasion simplifies PcdToMppRegs function. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Joe Zhou Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Library/MppLib/MppLib.c | 21 ++++++++------------ 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/Platform/Marvell/Library/MppLib/MppLib.c b/Platform/Marvell/Li= brary/MppLib/MppLib.c index c09acf9..383c820 100644 --- a/Platform/Marvell/Library/MppLib/MppLib.c +++ b/Platform/Marvell/Library/MppLib/MppLib.c @@ -74,7 +74,7 @@ STATIC VOID SetRegisterValue ( UINT8 RegCount, - UINT8 **MppRegPcd, + UINT8 MppRegPcd[][MPP_PINS_PER_REG], UINTN BaseAddr, BOOLEAN ReverseFlag ) @@ -99,10 +99,10 @@ STATIC UINT8 PcdToMppRegs ( UINTN PinCount, - UINT8 **MppRegPcd + UINT8 **MppRegPcd, + UINT8 MppRegPcdTmp[][MPP_PINS_PER_REG] ) { - UINT8 MppRegPcdTmp[MPP_MAX_REGS][MPP_PINS_PER_REG]; UINT8 PcdGroupCount, MppRegCount; UINTN i, j, k, l; =20 @@ -125,14 +125,7 @@ PcdToMppRegs ( for (j =3D 0; j < PCD_PINS_PER_GROUP; j++) { k =3D (PCD_PINS_PER_GROUP * i + j) / MPP_PINS_PER_REG; l =3D (PCD_PINS_PER_GROUP * i + j) % MPP_PINS_PER_REG; - MppRegPcdTmp[k][l] =3D MppRegPcd[i][j]; - } - } - - /* Update input table */ - for (i =3D 0; i < MppRegCount; i++) { - for (j =3D 0; j < MPP_PINS_PER_REG; j++) { - MppRegPcd[i][j] =3D MppRegPcdTmp[i][j]; + MppRegPcdTmp[k][l] =3D (UINT8)MppRegPcd[i][j]; } } =20 @@ -191,6 +184,7 @@ MppInitialize ( BOOLEAN ReverseFlag[MAX_CHIPS]; UINT8 *MppRegPcd[MAX_CHIPS][MPP_MAX_REGS]; UINT32 i, ChipCount; + UINT8 TmpMppValue[MPP_MAX_REGS][MPP_PINS_PER_REG]; =20 ChipCount =3D PcdGet32 (PcdMppChipCount); =20 @@ -203,8 +197,9 @@ MppInitialize ( for (i =3D 0; i < MAX_CHIPS; i++) { if (i =3D=3D ChipCount) break; - RegCount =3D PcdToMppRegs (PinCount[i], MppRegPcd[i]); - SetRegisterValue (RegCount, MppRegPcd[i], BaseAddr[i], ReverseFlag[i]); + + RegCount =3D PcdToMppRegs (PinCount[i], MppRegPcd[i], TmpMppValue); + SetRegisterValue (RegCount, TmpMppValue, BaseAddr[i], ReverseFlag[i]); =20 /* * eMMC PHY IP has its own MPP configuration. --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 02:21:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509121974256663.6924175168309; Fri, 27 Oct 2017 09:32:54 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7272921EA15D7; Fri, 27 Oct 2017 09:29:00 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C110221CEB12D for ; Fri, 27 Oct 2017 09:28:55 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id 75so8047600lfx.1 for ; Fri, 27 Oct 2017 09:32:43 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:40 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=c2fyQgv2Z5WT0KL9Kq9Fe8K5V0Zyqvytvrut+0OQ5J0=; b=J5ck1PkO6llWm9lX7NiNGSd7Azsb1IEk3qTTgcpzmUoi+/dWqriPOGmQNaSxYDBTMa RThwOHH/nzY4efsoJBGyPtcW/DuTVkRceVPxzMuy4p51PcT7aQnvJBTVCTkqhs2Wj+0G k2eqLw0X/QlV5+E1WEy0dc50Jthd4UkDe2+OZNkWFhKG7K0HLGOr6d7T56mjT3bcQUYq MWaodQ/w3zETpB3WAJsY/YeIFNW5hMNWU8YrJJyZXjwJ8aHid2HXmroppC9omEOCH5Us Ulge2WsNSxpHn4wahm89vfdX3GmWzSS9jDie6TAv7jToIdhCkx0OOrneXXhtgnVk4Cbo 5e6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c2fyQgv2Z5WT0KL9Kq9Fe8K5V0Zyqvytvrut+0OQ5J0=; b=VVIls2Vv8ZNADy4kvGbyK2DbCz2DPoqdt3rxXjLcbymAPofTjJh53bljNdV2BLjLOx xYax5Ez2ahSqw3v/fSpu88JTJOVGQXE1ovRSUnEUy4AFO9DpjXmeztUrVgOn3RRVSF6L ga960vYWUh7eEaK0XR0dzNQlJcKiv46EHMPr1Jc1ukqQmp0gQDvVL/Lk6UVe/1becydc V2bKgZCBZ1LV+fHiJrNPnyblO+po7GAPqY/f8et4Ovz9NsQIDfz0WObK4B0sKzCYoO2r YWytnOQbQ4muf6iKdVxIbviTHEtyp46cQQjgMRCZE+X3XQRjor6T/9VNw77o3ZT5s4JJ RSGg== X-Gm-Message-State: AMCzsaV3x8CxFVYdgsNh+rjJPDKCpDIT4ho6Ewp57rQ7G8TvN4c98FUf 20WzeDK6Xtr0LGrFxiu3NLOwrdLDCvI= X-Google-Smtp-Source: ABhQp+T8F53rd3wPkChA1COhVYOteuwHFYE9yJK4UJRQ14t+cApRiHrRBU2f/Oq/h0Ti9w3+MpGK8A== X-Received: by 10.25.178.206 with SMTP id t75mr379236lfk.228.1509121961225; Fri, 27 Oct 2017 09:32:41 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:48 +0200 Message-Id: <1509121913-12937-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 05/10] Marvell/Library: MppLib: Disable the stack protector X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel MppLib may be used very early (in SEC), at which point stack protection measures are more likely to cause harm than help, given that not even the UART has been configured to the point where we can complain usefully. So just disable it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Library/MppLib/MppLib.inf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Platform/Marvell/Library/MppLib/MppLib.inf b/Platform/Marvell/= Library/MppLib/MppLib.inf index 2de9cd0..1268542 100644 --- a/Platform/Marvell/Library/MppLib/MppLib.inf +++ b/Platform/Marvell/Library/MppLib/MppLib.inf @@ -106,3 +106,6 @@ gMarvellTokenSpaceGuid.PcdChip3MppSel7 =20 gMarvellTokenSpaceGuid.PcdPciESdhci + +[BuildOptions] + *_*_*_CC_FLAGS =3D -fno-stack-protector --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 02:21:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509121977837918.6272769498833; Fri, 27 Oct 2017 09:32:57 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B798221F3B3E3; Fri, 27 Oct 2017 09:29:00 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 01C6921E1B76A for ; Fri, 27 Oct 2017 09:28:56 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id l23so8011497lfk.10 for ; Fri, 27 Oct 2017 09:32:44 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:41 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lB+l/pkxnBfH0TSzI0QyKiJPPs+O8DuOjdIlbvgep/o=; b=VDlaVkNAAV7vIYVoaqaQvcL8KzG2E0gbBBp+eA3LTL+gr6VdMbTx/g5skewCie2sPR GGGsgyzJs/20M7pk2AvzPdqPFOl9q2S43QbyAi59aOoTjUUQbqaYmi71n1LywMSx8uEw bEU7FmH5GGmgWASV/unvQdlzE6X1+gv2EpNxYA6XTrNhdkUvCnSPMAgPpMv895H/5hnD WivPvf8rp0xxlIeYFj14Q5rpmNUExe3sjgk81a+61VAAr0qLOsTk8113xMKh2ie9AIKW vTPGADVH7htsh1+8oEsyNuamZ+zg5xkhY4ipnWNJisDdm1tJIQxeq0olsvYBoNSfgZMm pgsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lB+l/pkxnBfH0TSzI0QyKiJPPs+O8DuOjdIlbvgep/o=; b=TZKwQZgG8vXS1SepwoVeYHD2a884QrCkgbx5lNguzVH+8YqA+1WzUVDFKKu/JSni61 ce2T7KadsevdqyKkHBsKLOMk5lCkTFmi4YaRJowM0qOYDMopIX6oU9Z3zcA3fY3Xarm8 kXcV0OXlnbxtTKEul738I4S0A3HPObeObJuDZuJYYJsTu8kezU/Evxa/sYix7s/vbxtb nLrJAKmC6/5DBfvaiK+48+Wg/8luHWfbhboRv8z6u4NEw65PxyB/A+aFcupvV1GBJVjY hIw1n8TS5IiCS68zcKiebcG6yDCWfnN9EjPfrThaFDaNn+9leG2GQYOnbn+AJv3kjywa vvkA== X-Gm-Message-State: AMCzsaUp9VTwN7Fu1akodZQWzFJ1QlVNIrQnrVWHjuaFspL9lvvZCu2C LgdC3H/H5U6JiFhNXq/1ivmRzlCN4fA= X-Google-Smtp-Source: ABhQp+T8rjWFfW2zcWV5Cpra9O4cNspUVdzH/3tf4mCTNVcAye22CUSDqMNWIFAlAPhhPjpkl2Gk0g== X-Received: by 10.25.83.76 with SMTP id h73mr359238lfb.196.1509121962519; Fri, 27 Oct 2017 09:32:42 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:49 +0200 Message-Id: <1509121913-12937-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 06/10] Marvell/Library: MppLib: Take 0xFF placeholders into account X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The MppSel definition PCDs contain 0xFF placeholders for values that should be left untouched. MppLib needs to be taught how to take those into account. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Library/MppLib/MppLib.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Platform/Marvell/Library/MppLib/MppLib.c b/Platform/Marvell/Li= brary/MppLib/MppLib.c index 383c820..297725f 100644 --- a/Platform/Marvell/Library/MppLib/MppLib.c +++ b/Platform/Marvell/Library/MppLib/MppLib.c @@ -79,18 +79,24 @@ SetRegisterValue ( BOOLEAN ReverseFlag ) { - UINT32 i, j, CtrlVal; + UINT32 i, j, CtrlVal, CtrlMask, PinIndex; INTN Sign; =20 Sign =3D ReverseFlag ? -1 : 1; =20 for (i =3D 0; i < RegCount; i++) { CtrlVal =3D 0; + CtrlMask =3D 0; for (j =3D 0; j < MPP_PINS_PER_REG; j++) { - CtrlVal |=3D MPP_PIN_VAL(7 * (UINTN) ReverseFlag + j * Sign, - MppRegPcd[i][7 * (UINTN) ReverseFlag + j * Sign]); + + PinIndex =3D 7 * (UINTN)ReverseFlag + j * Sign; + + if (MppRegPcd[i][PinIndex] !=3D 0xff) { + CtrlVal |=3D MPP_PIN_VAL(PinIndex, MppRegPcd[i][PinIndex]); + CtrlMask |=3D MPP_PIN_VAL(PinIndex, 0xf); + } } - MmioWrite32 (BaseAddr + 4 * i * Sign, CtrlVal); + MmioAndThenOr32 (BaseAddr + 4 * i * Sign, ~CtrlMask, CtrlVal); } } =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 02:21:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509121981314778.0735304566756; Fri, 27 Oct 2017 09:33:01 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0905B21F3B3E6; Fri, 27 Oct 2017 09:29:01 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4A04121E1B76A for ; Fri, 27 Oct 2017 09:28:58 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id n69so8032561lfn.2 for ; Fri, 27 Oct 2017 09:32:45 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:43 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rwet9tcB6m+d7EppTvzCZbj3uAtRZWmz7vvXBHa72U0=; b=nizQLqn7x2244YclH0c/N4GLs6Ap0UlxUR8CXIvMYtu7GHIh+nAvWBa+jANrAaGvJi VOrZ4FVBwY4n3BmcXU8i9TedxWQg/7MmQBWKw2YuY4PN10EJ0hHpV5XtOcIc6KFTAtov geXhvU9DbeiNqJXMma8oJiOop3qzJ7i8ok7xC5M7UMnkaqJFjoFYoV6LTJJRIgqV8n1P qlf7E7I3fAdqMg4vY0ZDTXoX8ouY+WBQbw254LDuhXnp5uE329/DGPTIjcFCFKvOL2fc waBY457r+IHsKV/g73wLv6jiISq1g4WzqnlSLLL+itDsNRePKzGoj0QDLJhWoKiUXPv/ doLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rwet9tcB6m+d7EppTvzCZbj3uAtRZWmz7vvXBHa72U0=; b=H+VgFwU9SXc6vQ0UlM4RtcBR6vLGvT5yYFXVkMSmuI4XDYaHkQMR40diGqECpK1+wD /4lipLSCJllkUPUWWzICI4S/P0qUJDvwXK929yqWuPuFupAMNKPcuzmzyxk+S5Sas1/S tR6mBFHNl4+KbALfflfiLaEKPWHBsdFk4DnxsRqrtpQGSLg5p4aLd0xCPhlWwhj8n8Tz XjwoP/SbvaEpJUJv+sIkWbc92onvfTIi2jUdEbS4+m+Q9oC+5K2PnTaemvVyNZWDGXh4 iW9rQW3vEujOarnRbF6oljW4nqvsMoHybthwuHl7K8+ba8ZucCj5WrGo+5qM+iklBWIL kygQ== X-Gm-Message-State: AMCzsaWFwruQuj2mC+kDN/bz7gKBdA6uKk0wWOH/xC4n6pUG5wGGva1q nQU3909OBXWrSa/lpiGlql6vcTcAGic= X-Google-Smtp-Source: ABhQp+Ta9ylpCxd77JJvkRwZG5FSKKPOVthMVIwU3v8NniX3Dhbl5TeEAXCI4DWmzgi4NEu6Ahjs0Q== X-Received: by 10.46.4.29 with SMTP id 29mr487328lje.82.1509121963761; Fri, 27 Oct 2017 09:32:43 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:50 +0200 Message-Id: <1509121913-12937-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 07/10] Marvell/Drivers: Pp2Dxe: Change settings for the always-up link X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Currently initial forcing link status happened for all ports, not only marked as 'always-up'. Although this didn't actually matter for the MAC settings, because MAC is automatically updated with PHY HW polling feature of the controller, perform mv_gop110_fl_cfg only when the appropriate flag is true. Also in such case, force the link as up, using a new library routine. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c | 19 +++++++++++++++++++ Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h | 5 +++++ Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 6 +++++- 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c index 53154db..0c9f00c 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c @@ -4804,6 +4804,25 @@ MvGop110PortEventsMask ( return 0; } =20 +/* + * Sets "Force Link Pass" and clears "Do Not Force Link Fail" bits. + * This function should only be called when the port is disabled. + */ +VOID +MvGop110GmacForceLinkUp ( + IN PP2DXE_PORT *Port + ) +{ + UINT32 RegVal; + + RegVal =3D MvGop110GmacRead (Port, MVPP2_PORT_AUTO_NEG_CFG_REG); + + RegVal |=3D MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_UP_MASK; + RegVal &=3D ~MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN_MASK; + + MvGop110GmacWrite (Port, MVPP2_PORT_AUTO_NEG_CFG_REG, RegVal); +} + INT32 MvGop110FlCfg ( IN PP2DXE_PORT *Port diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h index a7011f7..3dc9ecd 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h @@ -504,6 +504,11 @@ MvGop110XlgPortLinkEventMask ( IN PP2DXE_PORT *Port ); =20 +VOID +MvGop110GmacForceLinkUp ( + IN PP2DXE_PORT *Port + ); + INT32 MvGop110FlCfg ( IN PP2DXE_PORT *Port diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 2827976..b0a38b3 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -1310,7 +1310,11 @@ Pp2DxeInitialiseController ( NetCompConfig |=3D MvpPp2xGop110NetcCfgCreate(&Pp2Context->Port); =20 MvGop110PortInit(&Pp2Context->Port); - MvGop110FlCfg(&Pp2Context->Port); + + if (Pp2Context->Port.AlwaysUp =3D=3D TRUE) { + MvGop110GmacForceLinkUp (&Pp2Context->Port); + MvGop110FlCfg (&Pp2Context->Port); + } =20 Status =3D gBS->CreateEvent ( EVT_SIGNAL_EXIT_BOOT_SERVICES, --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 02:21:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509121985266579.7348645536523; Fri, 27 Oct 2017 09:33:05 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4F05F21F3B3EB; Fri, 27 Oct 2017 09:29:01 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 923CE21CEB12D for ; Fri, 27 Oct 2017 09:28:59 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id a2so8008530lfh.11 for ; Fri, 27 Oct 2017 09:32:47 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:44 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3v51cHjrkjzSw17z7N1NL//F+XXQit20BV77H8Cdx5o=; b=lXES6NDZ3j6O4lYynhVx/6rYZAFZ7j4tyS3uq/8RDqfYmSgoXGPomuP1zZ/8MlGSe5 gDcGA6Vr4gRtnttO+zIGKDK3yXVBNfr2BCDC9UeGxBE/WjVqqz15RkcWdNWM2xiCy4Cy 8tKuvDReBN2W/m6YF9sM98/IlOCsnqBkDKNTL8zsUcWQRMK7Ktq8UmfmlKW7rHmgbiKc 36mcIRZAjJ0mT/y1mJzY4spL50GjsTeV0b6Dy/gddzdgA+goZFyXZM4RHZQklXl60fFZ jqD/eXcNkzxabSgbMUcr/7wLVBHf9RpkJcPOzisEZoDqplrCLS7kHvFSWFe8NM2mYst4 UeeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3v51cHjrkjzSw17z7N1NL//F+XXQit20BV77H8Cdx5o=; b=gOtwBrFGIrmuk02GqNnX8XiLCFjK6arbmHgrs9cDmUgGUZe8R+snTluTott6d2pGGF 2EDzIoDSjqvpVJ27pXLytIb7Pq8T+QhpCwhbUggoB4D55JN/CsSLRAuM3OirbtMV8ga1 ozkc/r2YnEzqulZk5vQq+5dpEM3lc/PPPkBX1y5TTqmoKbbYDVD+WurlO6ly+IdTr5ce TKdqf23aXf2y/fGkOEibHCqcOIcdWlIx/iXRJ2zzd9u1BGOqSXBvWn2QGUS5W7H4Ua1P LRFnOvBe8QZOYLTVjdZYs/wqmg6Qtk0paNAJOj0TTTI8n9VyJh4WjC2bJtkZuJYmWIfW ScRg== X-Gm-Message-State: AMCzsaXBNw3X52m9FPlpWkyEWkfF7dP5CVMUCCawujvDGjsSGlO3HQxJ 8cCLRdiE7FSTiWqwefQN6yqGlgKbgpk= X-Google-Smtp-Source: ABhQp+SVikVMBzRz8D0VMjX/SfP6RNLlEKqsrJVcn7nlAIJG4mhtLBnI77V+VGx/UXRn+fIjngh0IA== X-Received: by 10.46.83.67 with SMTP id t3mr418231ljd.135.1509121965200; Fri, 27 Oct 2017 09:32:45 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:51 +0200 Message-Id: <1509121913-12937-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch fixes incorrect settings for UHS mode in SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which the latter was missing. This field should be set to: 0x4 for DDR52 0x2 for SDR50 0x1 for SDR25 0x0 for others. This way EmmcSwitchToHighSpeed function is on par with Linux set_uhs_signaling routine in the Xenon driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platfor= m/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 3f73194..4d4833f 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -772,6 +772,8 @@ EmmcSwitchToHighSpeed ( if (IsDdr) { HostCtrl2 =3D BIT2; } else if (ClockFreq =3D=3D 52) { + HostCtrl2 =3D BIT1; + } else if (ClockFreq =3D=3D 26) { HostCtrl2 =3D BIT0; } else { HostCtrl2 =3D 0; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 02:21:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150912198887990.15701628171826; Fri, 27 Oct 2017 09:33:08 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 839BB21F3B3EF; Fri, 27 Oct 2017 09:29:05 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 24C7521F3B3E8 for ; Fri, 27 Oct 2017 09:29:01 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id a69so8037318lfe.5 for ; Fri, 27 Oct 2017 09:32:48 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:45 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5eoO2lE9vcr0fSZJTRSc9fucnSFsvOK1bm2fDgxlbe0=; b=L5ziICL4WR8U3PE8EhwuV7Lj7ymXHDhElAKYcYU+4vF1C6QH88AZRnIgduwDUN8wvL WmPle9q/RDX7scconzFzroejiaY48wlhQhQzRVi3EmmLkirCXfXKjrcTkK2Xrw6+WOQ3 iQlG+8cTj1nOF+hbGU4VJckOmjN9qg7+14dHwAmyFxRi1GnL5TRxYsqfpjBCelcIiKG5 Z4dJdrPcW3XLi+rn/Qjog+zvaN+HctwDxHcqJfhAd3IxO9zYYU0+/xdTbrFQCT+kqEdD FAgPbwP5rFiGje+FDgkbhoHRmn1MYAdvKtwSUr0jiUYSjvNFLkK4mSGQCb67TSn6VZ99 WL0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5eoO2lE9vcr0fSZJTRSc9fucnSFsvOK1bm2fDgxlbe0=; b=EeJyjmGbF4nr3u2dck0SFeGUn1+4GGJNxGCX2PwtCPWh5TTV1Mra6clwQjoz54khiu J07N/HSfxkAI6H/JKFbF5d6LcgQZIxad2u9nA/LyOKc4G9zaS7c2WCX2/1Dywb+1R7Tc bjGlGAPhXZnc+cPWg1lVQwi33pz9ywsDYyqmGVwyrz1cuvraYl3BMB14CTf3W26A/cEt ir0Kyua7vqm8O3xgt7K0KA006MJIPtV4x1E4n+QB0SkKdkdiBJDhs7tMO7IL6/9xbY+m GS146pS/eWYqIMgRjeYDqDagVXavbTSYHM9qKI47KP6W+OEkHh3YFgpIxljiA0R/WkcD V7hA== X-Gm-Message-State: AMCzsaVfD3A5U6ES3F8volBGikn1c6/UI01rSjLSVU+4Eznh7GoHm4EU KBSb57XirBKP0uGgjZBAcEv2JGezdEs= X-Google-Smtp-Source: ABhQp+QAoXsUjL0MPXJuHDfPsKaBMfv2oNEg0cSQGthS3OYBsNvkkO4Q4bKFBblrT5mGU/Wm46lVhg== X-Received: by 10.46.20.91 with SMTP id 27mr455439lju.23.1509121966562; Fri, 27 Oct 2017 09:32:46 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:52 +0200 Message-Id: <1509121913-12937-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 09/10] Marvell/Drivers: XenonDxe: Allow overriding base clock frequency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Some SdMmc host controllers are run by clocks with different frequency than it is reflected in Capabilities Register 1. Because the bitfield is only 8 bits wide, a maximum value that could be obtained from hardware is 255(MHz). In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq member of SD_MMC_HC_SLOT_CAP structure occurs to be not sufficient to be used for setting the clock speed in SdMmcHcClockSupply function. This patch adds new UINT32 array ('BaseClkFreq[]') to SD_MMC_HC_PRIVATE_DATA structure for specifying the input clock speed for each slot of the host controller. All routines that are used for clock configuration are updated accordingly. Thanks to above the Xenon host controller driver could be modified to configure clock speed relatively to actual 400MHz input. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 4 +-- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c | 4 +-- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 15 ++++++---- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h | 6 ++++ Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 31 ++++++++++++-= ------- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h | 16 ++++++---- 6 files changed, 48 insertions(+), 28 deletions(-) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platfor= m/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 4d4833f..530a01c 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -705,7 +705,7 @@ EmmcSwitchClockFreq ( // // Convert the clock freq unit from MHz to KHz. // - Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->C= apability[Slot]); + Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->B= aseClkFreq[Slot]); =20 return Status; } @@ -1007,7 +1007,7 @@ EmmcSetBusMode ( return Status; } =20 - ASSERT (Private->Capability[Slot].BaseClkFreq !=3D 0); + ASSERT (Private->BaseClkFreq[Slot] !=3D 0); // // Check if the Host Controller support 8bits bus width. // diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c b/Platform/= Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c index 9122848..ea7eed7 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c @@ -972,7 +972,7 @@ SdCardSetBusMode ( return Status; } =20 - Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capabilit= y); + Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->B= aseClkFreq[Slot]); if (EFI_ERROR (Status)) { return Status; } @@ -1144,7 +1144,7 @@ SdCardIdentification ( goto Error; } =20 - SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]); + SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]); =20 gBS->Stall (1000); =20 diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Plat= form/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index 981eab5..80159a4 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -291,7 +291,10 @@ SdMmcPciHcEnumerateDevice ( // // Reinitialize slot and restart identification process for the ne= w attached device // - Status =3D SdMmcHcInitHost (Private->PciIo, Slot, Private->Capabil= ity[Slot]); + Status =3D SdMmcHcInitHost (Private->PciIo, + Slot, + Private->Capability[Slot], + Private->BaseClkFreq[Slot]); if (EFI_ERROR (Status)) { continue; } @@ -617,11 +620,13 @@ SdMmcPciHcDriverBindingStart ( Private->Capability[Slot].Sdr50 =3D 0; Private->Capability[Slot].BusWidth8 =3D 0; =20 - if (Private->Capability[Slot].BaseClkFreq =3D=3D 0) { - Private->Capability[Slot].BaseClkFreq =3D 0xff; - } + // + // Override inappropriate base clock frequency from Capabilities Registe= r 1. + // Actual clock speed of Xenon controller is 400MHz. + // + Private->BaseClkFreq[Slot] =3D XENON_MMC_MAX_CLK / 1000 / 1000; =20 - DumpCapabilityReg (Slot, &Private->Capability[Slot]); + DumpCapabilityReg (Slot, &Private->Capability[Slot], Private->BaseClkFre= q[Slot]); =20 Status =3D SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]= ); if (EFI_ERROR (Status)) { diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h b/Plat= form/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h index 6a2a279..067b9ac 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h @@ -115,6 +115,12 @@ typedef struct { UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT]; =20 UINT32 ControllerVersion; + + // + // Some controllers may require to override base clock frequency + // value stored in Capabilities Register 1. + // + UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT]; } SD_MMC_HC_PRIVATE_DATA; =20 #define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T') diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Platfo= rm/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c index ccbf355..1f4abd1 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c @@ -22,12 +22,14 @@ =20 @param[in] Slot The slot number of the SD card to send the c= ommand to. @param[in] Capability The buffer to store the capability data. + @param[in] BaseClkFreq The base clock frequency of host controller = in MHz. =20 **/ VOID DumpCapabilityReg ( IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP *Capability + IN SD_MMC_HC_SLOT_CAP *Capability, + IN UINT32 BaseClkFreq ) { // @@ -35,7 +37,10 @@ DumpCapabilityReg ( // DEBUG ((DEBUG_INFO, " =3D=3D Slot [%d] Capability is 0x%x =3D=3D\n", Slo= t, Capability)); DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFr= eq, (Capability->TimeoutUnit) ? "MHz" : "KHz")); - DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkF= req)); + if (Capability->BaseClkFreq !=3D BaseClkFreq) { + DEBUG ((DEBUG_INFO, " Controller register value overriden:\n")); + } + DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", BaseClkFreq)); DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capabi= lity->MaxBlkLen))); DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ?= "TRUE" : "FALSE")); DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TR= UE" : "FALSE")); @@ -678,7 +683,7 @@ SdMmcHcStopClock ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] ClockFreq The max clock frequency to be set. The unit is= KHz. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -689,11 +694,10 @@ SdMmcHcClockSupply ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, IN UINT64 ClockFreq, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClkFreq ) { EFI_STATUS Status; - UINT32 BaseClkFreq; UINT32 SettingFreq; UINT32 Divisor; UINT32 Remainder; @@ -703,9 +707,8 @@ SdMmcHcClockSupply ( // // Calculate a divisor for SD clock frequency // - ASSERT (Capability.BaseClkFreq !=3D 0); + ASSERT (BaseClkFreq !=3D 0); =20 - BaseClkFreq =3D Capability.BaseClkFreq; if (ClockFreq =3D=3D 0) { return EFI_INVALID_PARAMETER; } @@ -896,7 +899,7 @@ SdMmcHcSetBusWidth ( =20 @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -906,7 +909,7 @@ EFI_STATUS SdMmcHcInitClockFreq ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClkFreq ) { EFI_STATUS Status; @@ -915,7 +918,7 @@ SdMmcHcInitClockFreq ( // // Calculate a divisor for SD clock frequency // - if (Capability.BaseClkFreq =3D=3D 0) { + if (BaseClkFreq =3D=3D 0) { // // Don't support get Base Clock Frequency information via another meth= od // @@ -925,7 +928,7 @@ SdMmcHcInitClockFreq ( // Supply 400KHz clock frequency at initialization phase. // InitFreq =3D 400; - Status =3D SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability); + Status =3D SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq); return Status; } =20 @@ -1024,6 +1027,7 @@ SdMmcHcInitTimeoutCtrl ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The host controller is initialized successfull= y. @retval Others The host controller isn't initialized successf= ully. @@ -1033,12 +1037,13 @@ EFI_STATUS SdMmcHcInitHost ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN SD_MMC_HC_SLOT_CAP Capability, + IN UINT32 BaseClkFreq ) { EFI_STATUS Status; =20 - Status =3D SdMmcHcInitClockFreq (PciIo, Slot, Capability); + Status =3D SdMmcHcInitClockFreq (PciIo, Slot, BaseClkFreq); if (EFI_ERROR (Status)) { return Status; } diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h b/Platfo= rm/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h index fb62758..533f37c 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h @@ -140,12 +140,14 @@ typedef struct { =20 @param[in] Slot The slot number of the SD card to send the c= ommand to. @param[in] Capability The buffer to store the capability data. + @param[in] BaseClkFreq The base clock frequency of host controller = in MHz. =20 **/ VOID DumpCapabilityReg ( IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP *Capability + IN SD_MMC_HC_SLOT_CAP *Capability, + IN UINT32 BaseClkFreq ); =20 /** @@ -414,7 +416,7 @@ SdMmcHcStopClock ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] ClockFreq The max clock frequency to be set. The unit is= KHz. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -425,7 +427,7 @@ SdMmcHcClockSupply ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, IN UINT64 ClockFreq, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClkFreq ); =20 /** @@ -473,7 +475,7 @@ SdMmcHcSetBusWidth ( =20 @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -483,7 +485,7 @@ EFI_STATUS SdMmcHcInitClockFreq ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClkFreq ); =20 /** @@ -531,6 +533,7 @@ SdMmcHcInitTimeoutCtrl ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The host controller is initialized successfull= y. @retval Others The host controller isn't initialized successf= ully. @@ -540,7 +543,8 @@ EFI_STATUS SdMmcHcInitHost ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN SD_MMC_HC_SLOT_CAP Capability, + IN UINT32 BaseClkFreq ); =20 #endif --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 02:21:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509121993040332.60456157361295; Fri, 27 Oct 2017 09:33:13 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C1F2721F3B3F2; Fri, 27 Oct 2017 09:29:05 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4509821F3B3ED for ; Fri, 27 Oct 2017 09:29:02 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id a132so8025513lfa.7 for ; Fri, 27 Oct 2017 09:32:49 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:47 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A7zc2/u0Y4h9ChbtWDS94GyHyj90ZIKnWA4DhvOjBBw=; b=McN2ofe38Dpwhyb5ZzlqbGaGLGnikjI1ysL0UT3/IUsdQ3gHiZDsqNcaoUgUBLSQ3c n3FSl24vPN+Bw2ChsNydga72L9hs0PG4f+2v9Ai2u273tvqJOFPuVB59KF507FnCRRfV HXAqAm9nH66j62ZlBvRreS6ZBMW5PuGPjLRffstMh5tT2NV6uoOOc4ui3aza1UDUJqTv tYbHjMTVfPPt9wS2nfJ6fP85TZuSdKYVQkkm6qY0we0YJEim9q9Sj02Roj85qNAtpt7f 7xUZdhRo9LXlfODLWvVAK5YeuSpEpcaD/l/Jzh9H8JjbzAWFvOtB5sqtBXp9O5dr39Mm 6gVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A7zc2/u0Y4h9ChbtWDS94GyHyj90ZIKnWA4DhvOjBBw=; b=ehmBDNa7r9uPk+QnGlg7Ne6eRt34n+UykqaFRTiDo8oNAYAZMjh3y0Rw5HHF+3seLx feGuzYz+0SFe6nI6uSS/i+7Mk/cZBuEMHLWMZc3P8ncLCaMame7JlfQYPF7njRppCR3U ZXKcVPo/ovWPEBSh3utkoa6N7kK0lzOev7pyLyRKyC2mkI88zFddkcLWojtZn3cJb0q1 OLmNFxYOMYOxPNDaOxkJa0C1ZrO62ny+Y5dvhc3FccWLrvsWkav2bvbtR9WCkFxW4ohj /nv9p9TVLv0Ad6/m91SmPTqMapR4F5w4Z2wd2/+aXugJBhstjNDKKJFudz/B6i0lPA8Y 40Wg== X-Gm-Message-State: AMCzsaVmfu077+JVQzxasfHsDERPjSLGibAVtYKpk8fp/RVg0Td33k2b TwCmRTKsjWgjiKOZlnsuQ5Vi2Yz++5o= X-Google-Smtp-Source: ABhQp+RT5BDNjL2zqQ2chDXd8ra5gYL2whznKNN1gsB+Efr5M9/xlQiL7TimJ1bAGdGXlnktGYg4rA== X-Received: by 10.46.64.82 with SMTP id n79mr451457lja.129.1509121967795; Fri, 27 Oct 2017 09:32:47 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:53 +0200 Message-Id: <1509121913-12937-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 10/10] Marvell/Drivers: XenonDxe: Do not modify FIFO default values X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Changing controller's FIFO default values is not necessary and possibly can cause instabilities, when using some devices. Disable the modification and rely on initial settings. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Platfor= m/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c index 31f207e..6bbe5bc 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c @@ -44,20 +44,6 @@ XenonReadVersion ( SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CTRL_VER, TRUE, SDHC_REG_S= IZE_2B, ControllerVersion); } =20 -STATIC -VOID -XenonSetFifo ( - IN EFI_PCI_IO_PROTOCOL *PciIo - ) -{ - UINTN Data; - - // Set FIFO_RTC, FIFO_WTC, FIFO_CS and FIFO_PDLVMC - Data =3D SDHC_SLOT_FIFO_DEFAULT_CONFIG; - - SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, SDHC_REG= _SIZE_4B, &Data); -} - // Auto Clock Gating STATIC VOID @@ -634,8 +620,6 @@ XenonInit ( // Read XENON version XenonReadVersion (PciIo, &Private->ControllerVersion); =20 - XenonSetFifo (PciIo); - // Disable auto clock generator XenonSetAcg (PciIo, FALSE); =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel