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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:45 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5eoO2lE9vcr0fSZJTRSc9fucnSFsvOK1bm2fDgxlbe0=; b=L5ziICL4WR8U3PE8EhwuV7Lj7ymXHDhElAKYcYU+4vF1C6QH88AZRnIgduwDUN8wvL WmPle9q/RDX7scconzFzroejiaY48wlhQhQzRVi3EmmLkirCXfXKjrcTkK2Xrw6+WOQ3 iQlG+8cTj1nOF+hbGU4VJckOmjN9qg7+14dHwAmyFxRi1GnL5TRxYsqfpjBCelcIiKG5 Z4dJdrPcW3XLi+rn/Qjog+zvaN+HctwDxHcqJfhAd3IxO9zYYU0+/xdTbrFQCT+kqEdD FAgPbwP5rFiGje+FDgkbhoHRmn1MYAdvKtwSUr0jiUYSjvNFLkK4mSGQCb67TSn6VZ99 WL0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5eoO2lE9vcr0fSZJTRSc9fucnSFsvOK1bm2fDgxlbe0=; b=EeJyjmGbF4nr3u2dck0SFeGUn1+4GGJNxGCX2PwtCPWh5TTV1Mra6clwQjoz54khiu J07N/HSfxkAI6H/JKFbF5d6LcgQZIxad2u9nA/LyOKc4G9zaS7c2WCX2/1Dywb+1R7Tc bjGlGAPhXZnc+cPWg1lVQwi33pz9ywsDYyqmGVwyrz1cuvraYl3BMB14CTf3W26A/cEt ir0Kyua7vqm8O3xgt7K0KA006MJIPtV4x1E4n+QB0SkKdkdiBJDhs7tMO7IL6/9xbY+m GS146pS/eWYqIMgRjeYDqDagVXavbTSYHM9qKI47KP6W+OEkHh3YFgpIxljiA0R/WkcD V7hA== X-Gm-Message-State: AMCzsaVfD3A5U6ES3F8volBGikn1c6/UI01rSjLSVU+4Eznh7GoHm4EU KBSb57XirBKP0uGgjZBAcEv2JGezdEs= X-Google-Smtp-Source: ABhQp+QAoXsUjL0MPXJuHDfPsKaBMfv2oNEg0cSQGthS3OYBsNvkkO4Q4bKFBblrT5mGU/Wm46lVhg== X-Received: by 10.46.20.91 with SMTP id 27mr455439lju.23.1509121966562; Fri, 27 Oct 2017 09:32:46 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:52 +0200 Message-Id: <1509121913-12937-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 09/10] Marvell/Drivers: XenonDxe: Allow overriding base clock frequency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Some SdMmc host controllers are run by clocks with different frequency than it is reflected in Capabilities Register 1. Because the bitfield is only 8 bits wide, a maximum value that could be obtained from hardware is 255(MHz). In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq member of SD_MMC_HC_SLOT_CAP structure occurs to be not sufficient to be used for setting the clock speed in SdMmcHcClockSupply function. This patch adds new UINT32 array ('BaseClkFreq[]') to SD_MMC_HC_PRIVATE_DATA structure for specifying the input clock speed for each slot of the host controller. All routines that are used for clock configuration are updated accordingly. Thanks to above the Xenon host controller driver could be modified to configure clock speed relatively to actual 400MHz input. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 4 +-- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c | 4 +-- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 15 ++++++---- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h | 6 ++++ Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 31 ++++++++++++-= ------- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h | 16 ++++++---- 6 files changed, 48 insertions(+), 28 deletions(-) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platfor= m/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 4d4833f..530a01c 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -705,7 +705,7 @@ EmmcSwitchClockFreq ( // // Convert the clock freq unit from MHz to KHz. // - Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->C= apability[Slot]); + Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->B= aseClkFreq[Slot]); =20 return Status; } @@ -1007,7 +1007,7 @@ EmmcSetBusMode ( return Status; } =20 - ASSERT (Private->Capability[Slot].BaseClkFreq !=3D 0); + ASSERT (Private->BaseClkFreq[Slot] !=3D 0); // // Check if the Host Controller support 8bits bus width. // diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c b/Platform/= Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c index 9122848..ea7eed7 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c @@ -972,7 +972,7 @@ SdCardSetBusMode ( return Status; } =20 - Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capabilit= y); + Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->B= aseClkFreq[Slot]); if (EFI_ERROR (Status)) { return Status; } @@ -1144,7 +1144,7 @@ SdCardIdentification ( goto Error; } =20 - SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]); + SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]); =20 gBS->Stall (1000); =20 diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Plat= form/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index 981eab5..80159a4 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -291,7 +291,10 @@ SdMmcPciHcEnumerateDevice ( // // Reinitialize slot and restart identification process for the ne= w attached device // - Status =3D SdMmcHcInitHost (Private->PciIo, Slot, Private->Capabil= ity[Slot]); + Status =3D SdMmcHcInitHost (Private->PciIo, + Slot, + Private->Capability[Slot], + Private->BaseClkFreq[Slot]); if (EFI_ERROR (Status)) { continue; } @@ -617,11 +620,13 @@ SdMmcPciHcDriverBindingStart ( Private->Capability[Slot].Sdr50 =3D 0; Private->Capability[Slot].BusWidth8 =3D 0; =20 - if (Private->Capability[Slot].BaseClkFreq =3D=3D 0) { - Private->Capability[Slot].BaseClkFreq =3D 0xff; - } + // + // Override inappropriate base clock frequency from Capabilities Registe= r 1. + // Actual clock speed of Xenon controller is 400MHz. + // + Private->BaseClkFreq[Slot] =3D XENON_MMC_MAX_CLK / 1000 / 1000; =20 - DumpCapabilityReg (Slot, &Private->Capability[Slot]); + DumpCapabilityReg (Slot, &Private->Capability[Slot], Private->BaseClkFre= q[Slot]); =20 Status =3D SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]= ); if (EFI_ERROR (Status)) { diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h b/Plat= form/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h index 6a2a279..067b9ac 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h @@ -115,6 +115,12 @@ typedef struct { UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT]; =20 UINT32 ControllerVersion; + + // + // Some controllers may require to override base clock frequency + // value stored in Capabilities Register 1. + // + UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT]; } SD_MMC_HC_PRIVATE_DATA; =20 #define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T') diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Platfo= rm/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c index ccbf355..1f4abd1 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c @@ -22,12 +22,14 @@ =20 @param[in] Slot The slot number of the SD card to send the c= ommand to. @param[in] Capability The buffer to store the capability data. + @param[in] BaseClkFreq The base clock frequency of host controller = in MHz. =20 **/ VOID DumpCapabilityReg ( IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP *Capability + IN SD_MMC_HC_SLOT_CAP *Capability, + IN UINT32 BaseClkFreq ) { // @@ -35,7 +37,10 @@ DumpCapabilityReg ( // DEBUG ((DEBUG_INFO, " =3D=3D Slot [%d] Capability is 0x%x =3D=3D\n", Slo= t, Capability)); DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFr= eq, (Capability->TimeoutUnit) ? "MHz" : "KHz")); - DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkF= req)); + if (Capability->BaseClkFreq !=3D BaseClkFreq) { + DEBUG ((DEBUG_INFO, " Controller register value overriden:\n")); + } + DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", BaseClkFreq)); DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capabi= lity->MaxBlkLen))); DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ?= "TRUE" : "FALSE")); DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TR= UE" : "FALSE")); @@ -678,7 +683,7 @@ SdMmcHcStopClock ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] ClockFreq The max clock frequency to be set. The unit is= KHz. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -689,11 +694,10 @@ SdMmcHcClockSupply ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, IN UINT64 ClockFreq, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClkFreq ) { EFI_STATUS Status; - UINT32 BaseClkFreq; UINT32 SettingFreq; UINT32 Divisor; UINT32 Remainder; @@ -703,9 +707,8 @@ SdMmcHcClockSupply ( // // Calculate a divisor for SD clock frequency // - ASSERT (Capability.BaseClkFreq !=3D 0); + ASSERT (BaseClkFreq !=3D 0); =20 - BaseClkFreq =3D Capability.BaseClkFreq; if (ClockFreq =3D=3D 0) { return EFI_INVALID_PARAMETER; } @@ -896,7 +899,7 @@ SdMmcHcSetBusWidth ( =20 @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -906,7 +909,7 @@ EFI_STATUS SdMmcHcInitClockFreq ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClkFreq ) { EFI_STATUS Status; @@ -915,7 +918,7 @@ SdMmcHcInitClockFreq ( // // Calculate a divisor for SD clock frequency // - if (Capability.BaseClkFreq =3D=3D 0) { + if (BaseClkFreq =3D=3D 0) { // // Don't support get Base Clock Frequency information via another meth= od // @@ -925,7 +928,7 @@ SdMmcHcInitClockFreq ( // Supply 400KHz clock frequency at initialization phase. // InitFreq =3D 400; - Status =3D SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability); + Status =3D SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq); return Status; } =20 @@ -1024,6 +1027,7 @@ SdMmcHcInitTimeoutCtrl ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The host controller is initialized successfull= y. @retval Others The host controller isn't initialized successf= ully. @@ -1033,12 +1037,13 @@ EFI_STATUS SdMmcHcInitHost ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN SD_MMC_HC_SLOT_CAP Capability, + IN UINT32 BaseClkFreq ) { EFI_STATUS Status; =20 - Status =3D SdMmcHcInitClockFreq (PciIo, Slot, Capability); + Status =3D SdMmcHcInitClockFreq (PciIo, Slot, BaseClkFreq); if (EFI_ERROR (Status)) { return Status; } diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h b/Platfo= rm/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h index fb62758..533f37c 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h @@ -140,12 +140,14 @@ typedef struct { =20 @param[in] Slot The slot number of the SD card to send the c= ommand to. @param[in] Capability The buffer to store the capability data. + @param[in] BaseClkFreq The base clock frequency of host controller = in MHz. =20 **/ VOID DumpCapabilityReg ( IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP *Capability + IN SD_MMC_HC_SLOT_CAP *Capability, + IN UINT32 BaseClkFreq ); =20 /** @@ -414,7 +416,7 @@ SdMmcHcStopClock ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] ClockFreq The max clock frequency to be set. The unit is= KHz. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -425,7 +427,7 @@ SdMmcHcClockSupply ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, IN UINT64 ClockFreq, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClkFreq ); =20 /** @@ -473,7 +475,7 @@ SdMmcHcSetBusWidth ( =20 @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -483,7 +485,7 @@ EFI_STATUS SdMmcHcInitClockFreq ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClkFreq ); =20 /** @@ -531,6 +533,7 @@ SdMmcHcInitTimeoutCtrl ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The host controller is initialized successfull= y. @retval Others The host controller isn't initialized successf= ully. @@ -540,7 +543,8 @@ EFI_STATUS SdMmcHcInitHost ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN SD_MMC_HC_SLOT_CAP Capability, + IN UINT32 BaseClkFreq ); =20 #endif --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel