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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:44 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3v51cHjrkjzSw17z7N1NL//F+XXQit20BV77H8Cdx5o=; b=lXES6NDZ3j6O4lYynhVx/6rYZAFZ7j4tyS3uq/8RDqfYmSgoXGPomuP1zZ/8MlGSe5 gDcGA6Vr4gRtnttO+zIGKDK3yXVBNfr2BCDC9UeGxBE/WjVqqz15RkcWdNWM2xiCy4Cy 8tKuvDReBN2W/m6YF9sM98/IlOCsnqBkDKNTL8zsUcWQRMK7Ktq8UmfmlKW7rHmgbiKc 36mcIRZAjJ0mT/y1mJzY4spL50GjsTeV0b6Dy/gddzdgA+goZFyXZM4RHZQklXl60fFZ jqD/eXcNkzxabSgbMUcr/7wLVBHf9RpkJcPOzisEZoDqplrCLS7kHvFSWFe8NM2mYst4 UeeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3v51cHjrkjzSw17z7N1NL//F+XXQit20BV77H8Cdx5o=; b=gOtwBrFGIrmuk02GqNnX8XiLCFjK6arbmHgrs9cDmUgGUZe8R+snTluTott6d2pGGF 2EDzIoDSjqvpVJ27pXLytIb7Pq8T+QhpCwhbUggoB4D55JN/CsSLRAuM3OirbtMV8ga1 ozkc/r2YnEzqulZk5vQq+5dpEM3lc/PPPkBX1y5TTqmoKbbYDVD+WurlO6ly+IdTr5ce TKdqf23aXf2y/fGkOEibHCqcOIcdWlIx/iXRJ2zzd9u1BGOqSXBvWn2QGUS5W7H4Ua1P LRFnOvBe8QZOYLTVjdZYs/wqmg6Qtk0paNAJOj0TTTI8n9VyJh4WjC2bJtkZuJYmWIfW ScRg== X-Gm-Message-State: AMCzsaXBNw3X52m9FPlpWkyEWkfF7dP5CVMUCCawujvDGjsSGlO3HQxJ 8cCLRdiE7FSTiWqwefQN6yqGlgKbgpk= X-Google-Smtp-Source: ABhQp+SVikVMBzRz8D0VMjX/SfP6RNLlEKqsrJVcn7nlAIJG4mhtLBnI77V+VGx/UXRn+fIjngh0IA== X-Received: by 10.46.83.67 with SMTP id t3mr418231ljd.135.1509121965200; Fri, 27 Oct 2017 09:32:45 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 18:31:51 +0200 Message-Id: <1509121913-12937-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch fixes incorrect settings for UHS mode in SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which the latter was missing. This field should be set to: 0x4 for DDR52 0x2 for SDR50 0x1 for SDR25 0x0 for others. This way EmmcSwitchToHighSpeed function is on par with Linux set_uhs_signaling routine in the Xenon driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platfor= m/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 3f73194..4d4833f 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -772,6 +772,8 @@ EmmcSwitchToHighSpeed ( if (IsDdr) { HostCtrl2 =3D BIT2; } else if (ClockFreq =3D=3D 52) { + HostCtrl2 =3D BIT1; + } else if (ClockFreq =3D=3D 26) { HostCtrl2 =3D BIT0; } else { HostCtrl2 =3D 0; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel