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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id f21sm107393lja.25.2017.10.30.21.00.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 30 Oct 2017 21:00:01 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gld9rqO5kswB2d11OcJqiNSai8oGSnKuOiKdMb6pREU=; b=YQWnM7MaSU3dJF7JVEq+6oQ7AttCadcm6qKtfNfnpQcDIy5sfEpUokd3ZtRp0XC1VP vZXTQl1BVKeb6E8wLq01KuqWet+LEipYYPgkRxnZkw2V4hsE1frOyWZgNi+lrgXM4U8R L6gp/NmK2aQ9hLnDjOBKvnQgmWPJxg42kZUcZFuhUMRsZkE21MUso0695c+QdsQX/kjq 22sPAYDX6dr5fcUvyrw4QiASRqFIphrN5WiaUlfwJxmxd5w90CCaNsid94qPb5zH4nsa oO5pGLtJkPRKzDBD5tarf+8sJTN8r/jhmXFGQVLqdw9GeZvP9tqf7P7NlTEfkQWaq1TR Nofg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gld9rqO5kswB2d11OcJqiNSai8oGSnKuOiKdMb6pREU=; b=I+U7riccdJQM5jJMzzgRwSfWRpSQ24g2AE63UckPqtNStHd5j4XF6q6QMfWdP+yLrd A8fOHA/ePo5YxETs4FbGXfb+BDEBGj3XSZiV49nXBr80ek+Q/yp1ZSxnSMIc1wfZflSk dYowYjWNZ+enocu3veLeD//wsV+yvYImGXOv0YLtgxs/4CQSHO9xF9Grne+i4rLdaVR4 ppD0AR0WQJR07139f/9Z+QZQPf368tKGtzHW/zg8lltU3bacAhujW7jFykABLMvl7VwY YoRBT/xy5ePJ5jnmlR5TinkcHByQImwtPHJAycWEqek6bS99kN47nYmun0DagKzBYv8d 2QEw== X-Gm-Message-State: AMCzsaUylvAa69nmcD8Vqr9aF4B315/tztioqjm90hWKPASGsVTJy1gS uVkagt2yFqqFlipnOSKKApMfrULPMBQ= X-Google-Smtp-Source: ABhQp+TW9MEqsp2/QPG3GX2r8ENoxPxHiT/OM6dLVBppsKkOazSArImDg5+hJn2qpJtnuPdX5wpiIQ== X-Received: by 10.46.25.87 with SMTP id p84mr262515lje.67.1509422402165; Mon, 30 Oct 2017 21:00:02 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 31 Oct 2017 04:59:35 +0100 Message-Id: <1509422375-20198-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509422375-20198-1-git-send-email-mw@semihalf.com> References: <1509422375-20198-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 6/6] Marvell/Drivers: MvSpiDxe: Keep data in SPI_DEVICE structure X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In the MvSpiDxe driver obtaining host register base address, controller clock and device maximum frequency directly from PCDs was done all over the code. This patch cleans up the parameters' handling and enables accessing them from SPI_DEVICE structure fields. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 48 ++++++++++++-------- Platform/Marvell/Include/Protocol/Spi.h | 2 + 2 files changed, 31 insertions(+), 19 deletions(-) diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index a7db5f2..c60a520 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -38,12 +38,13 @@ SPI_MASTER *mSpiMasterInstance; STATIC EFI_STATUS SpiSetBaudRate ( + IN SPI_DEVICE *Slave, IN UINT32 CpuClock, IN UINT32 MaxFreq ) { UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDi= ff; - UINTN SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 MinBaudDiff =3D 0xFFFFFFFF; BestSppr =3D 0; @@ -93,26 +94,28 @@ SpiSetBaudRate ( STATIC VOID SpiSetCs ( - UINT8 CsId + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg &=3D ~SPI_CS_NUM_MASK; - Reg |=3D (CsId << SPI_CS_NUM_OFFSET); + Reg |=3D (Slave->Cs << SPI_CS_NUM_OFFSET); MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg); } =20 STATIC VOID SpiActivateCs ( - UINT8 IN CsId + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 - SpiSetCs(CsId); + SpiSetCs(Slave); Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg |=3D SPI_CS_EN_MASK; MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg); @@ -121,10 +124,11 @@ SpiActivateCs ( STATIC VOID SpiDeactivateCs ( - VOID + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg &=3D ~SPI_CS_EN_MASK; @@ -139,14 +143,15 @@ SpiSetupTransfer ( ) { SPI_MASTER *SpiMaster; - UINT32 Reg, SpiRegBase, CoreClock, SpiMaxFreq; + UINT32 Reg, CoreClock, SpiMaxFreq; + UINTN SpiRegBase; =20 SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); =20 // Initialize values from PCDs - SpiRegBase =3D PcdGet32 (PcdSpiRegBase); - CoreClock =3D PcdGet32 (PcdSpiClockFrequency); - SpiMaxFreq =3D PcdGet32 (PcdSpiMaxFrequency); + SpiRegBase =3D Slave->HostRegisterBaseAddress; + CoreClock =3D Slave->CoreClock; + SpiMaxFreq =3D Slave->MaxFreq; =20 EfiAcquireLock (&SpiMaster->Lock); =20 @@ -154,9 +159,9 @@ SpiSetupTransfer ( Reg |=3D SPI_BYTE_LENGTH; MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg); =20 - SpiSetCs(Slave->Cs); + SpiSetCs(Slave); =20 - SpiSetBaudRate (CoreClock, SpiMaxFreq); + SpiSetBaudRate (Slave, CoreClock, SpiMaxFreq); =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CONF_REG); Reg &=3D ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_= MASK); @@ -194,21 +199,22 @@ MvSpiTransfer ( { SPI_MASTER *SpiMaster; UINT64 Length; - UINT32 Iterator, Reg, SpiRegBase; + UINT32 Iterator, Reg; UINT8 *DataOutPtr =3D (UINT8 *)DataOut; UINT8 *DataInPtr =3D (UINT8 *)DataIn; UINT8 DataToSend =3D 0; + UINTN SpiRegBase; =20 SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); =20 - SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Length =3D 8 * DataByteCount; =20 EfiAcquireLock (&SpiMaster->Lock); =20 if (Flag & SPI_TRANSFER_BEGIN) { - SpiActivateCs (Slave->Cs); + SpiActivateCs (Slave); } =20 // Set 8-bit mode @@ -245,7 +251,7 @@ MvSpiTransfer ( } =20 if (Flag & SPI_TRANSFER_END) { - SpiDeactivateCs (); + SpiDeactivateCs (Slave); } =20 EfiReleaseLock (&SpiMaster->Lock); @@ -312,6 +318,10 @@ MvSpiSetupSlave ( Slave->Mode =3D Mode; } =20 + Slave->HostRegisterBaseAddress =3D PcdGet32 (PcdSpiRegBase); + Slave->CoreClock =3D PcdGet32 (PcdSpiClockFrequency); + Slave->MaxFreq =3D PcdGet32 (PcdSpiMaxFrequency); + SpiSetupTransfer (This, Slave); =20 return Slave; diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Inc= lude/Protocol/Spi.h index 0cf7914..b8981f3 100644 --- a/Platform/Marvell/Include/Protocol/Spi.h +++ b/Platform/Marvell/Include/Protocol/Spi.h @@ -52,6 +52,8 @@ typedef struct { INTN MaxFreq; SPI_MODE Mode; NOR_FLASH_INFO *Info; + UINTN HostRegisterBaseAddress; + UINTN CoreClock; } SPI_DEVICE; =20 typedef --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel