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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id g29sm1120441lfh.3.2017.11.03.10.57.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 10:57:33 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jkTvaKcMBFd591AN5YKAflZwiCaHHwVusugTfpkIOM4=; b=VKTjyTo9QXFOEwvqfDQMaeBzIcAuSXQPKUY7eim0ZsY/phz7YAo60GjqIlYdb2fPf2 Wz1B5bf8Nv3H/t2SKdmUVc0FrcW8vvhqMHC/vvu+gAE3W0/fWcKeVbUH4MBySuknOY+s bemMi80ZnTgQ8c0BaMK1/MhTCW0m8sn6xCI2p8UzSWitalSMsRJ+bNy+Aq+QqQRMn6aC u9YQtmFmLg5qZgsPJT2zAInoqPjeNIrJdrXZOJSCF9GO5tREmKRpJTCcFeV/ECvGgkrz fUXDh1aWe2m07/Pi5hVGtCKZs6yydFhYwOl68j72bWj5ViuOJYVDT8MbnqxYm347/Jtm m2Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jkTvaKcMBFd591AN5YKAflZwiCaHHwVusugTfpkIOM4=; b=ZnV0Bsrj8liu5xFUd5BES4u1o4vvmJbXJhvW++lj7g6Pawk91cdfd3R7mqDbAS15Yu OlwH8L0c+nPxemXuSkZVkdOTcK/+cOJxMxEaNMQIi4m+qLcjUMYH4FKGfgoISwlc8QpO glGUMclAOC4DJpBNF1bccMcsilvO8iTgtznIEZqXibxM4mYjRPvCLJ+xK/GwkzB0281C Li/JzgcQb+/y+YXhSgtehtXFxYrYsRUgFNbgGtMTpP2De1FLmWwo9ErtWYwSXakcmAsM 4Ku+bObdXw5/0oXqkRUFZ0JBXGKmk2qYmpnU02i2R1sYjpqrfaAYHa7uI2nI7/AsTqlE ZjTg== X-Gm-Message-State: AJaThX6yhTagzLCc3BNb1/wNTAoMsOJ5L1dqOmoco8t83twQDb3F227w DlwFsqxGiViY1ZFLy/T8YZI5G7tgZdQ= X-Google-Smtp-Source: ABhQp+Qvlc9jDgPGBPsL0fKia1bkrkI6l9GhjPYOPX84AkOG4bg4PmAMp1s3QWQN2JGmcVeDrmX/MQ== X-Received: by 10.25.151.17 with SMTP id z17mr2878925lfd.153.1509731853673; Fri, 03 Nov 2017 10:57:33 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 3 Nov 2017 18:57:15 +0100 Message-Id: <1509731835-5664-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509731835-5664-1-git-send-email-mw@semihalf.com> References: <1509731835-5664-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 6/6] Marvell/Drivers: MvSpiDxe: Keep data in SPI_DEVICE structure X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In the MvSpiDxe driver obtaining host register base address, controller clock and device maximum frequency directly from PCDs was done all over the code. This patch cleans up the parameters' handling and enables accessing them from SPI_DEVICE structure fields. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 48 ++++++++++++-------- Platform/Marvell/Include/Protocol/Spi.h | 2 + 2 files changed, 31 insertions(+), 19 deletions(-) diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index a7db5f2..c60a520 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -38,12 +38,13 @@ SPI_MASTER *mSpiMasterInstance; STATIC EFI_STATUS SpiSetBaudRate ( + IN SPI_DEVICE *Slave, IN UINT32 CpuClock, IN UINT32 MaxFreq ) { UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDi= ff; - UINTN SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 MinBaudDiff =3D 0xFFFFFFFF; BestSppr =3D 0; @@ -93,26 +94,28 @@ SpiSetBaudRate ( STATIC VOID SpiSetCs ( - UINT8 CsId + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg &=3D ~SPI_CS_NUM_MASK; - Reg |=3D (CsId << SPI_CS_NUM_OFFSET); + Reg |=3D (Slave->Cs << SPI_CS_NUM_OFFSET); MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg); } =20 STATIC VOID SpiActivateCs ( - UINT8 IN CsId + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 - SpiSetCs(CsId); + SpiSetCs(Slave); Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg |=3D SPI_CS_EN_MASK; MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg); @@ -121,10 +124,11 @@ SpiActivateCs ( STATIC VOID SpiDeactivateCs ( - VOID + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg &=3D ~SPI_CS_EN_MASK; @@ -139,14 +143,15 @@ SpiSetupTransfer ( ) { SPI_MASTER *SpiMaster; - UINT32 Reg, SpiRegBase, CoreClock, SpiMaxFreq; + UINT32 Reg, CoreClock, SpiMaxFreq; + UINTN SpiRegBase; =20 SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); =20 // Initialize values from PCDs - SpiRegBase =3D PcdGet32 (PcdSpiRegBase); - CoreClock =3D PcdGet32 (PcdSpiClockFrequency); - SpiMaxFreq =3D PcdGet32 (PcdSpiMaxFrequency); + SpiRegBase =3D Slave->HostRegisterBaseAddress; + CoreClock =3D Slave->CoreClock; + SpiMaxFreq =3D Slave->MaxFreq; =20 EfiAcquireLock (&SpiMaster->Lock); =20 @@ -154,9 +159,9 @@ SpiSetupTransfer ( Reg |=3D SPI_BYTE_LENGTH; MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg); =20 - SpiSetCs(Slave->Cs); + SpiSetCs(Slave); =20 - SpiSetBaudRate (CoreClock, SpiMaxFreq); + SpiSetBaudRate (Slave, CoreClock, SpiMaxFreq); =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CONF_REG); Reg &=3D ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_= MASK); @@ -194,21 +199,22 @@ MvSpiTransfer ( { SPI_MASTER *SpiMaster; UINT64 Length; - UINT32 Iterator, Reg, SpiRegBase; + UINT32 Iterator, Reg; UINT8 *DataOutPtr =3D (UINT8 *)DataOut; UINT8 *DataInPtr =3D (UINT8 *)DataIn; UINT8 DataToSend =3D 0; + UINTN SpiRegBase; =20 SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); =20 - SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Length =3D 8 * DataByteCount; =20 EfiAcquireLock (&SpiMaster->Lock); =20 if (Flag & SPI_TRANSFER_BEGIN) { - SpiActivateCs (Slave->Cs); + SpiActivateCs (Slave); } =20 // Set 8-bit mode @@ -245,7 +251,7 @@ MvSpiTransfer ( } =20 if (Flag & SPI_TRANSFER_END) { - SpiDeactivateCs (); + SpiDeactivateCs (Slave); } =20 EfiReleaseLock (&SpiMaster->Lock); @@ -312,6 +318,10 @@ MvSpiSetupSlave ( Slave->Mode =3D Mode; } =20 + Slave->HostRegisterBaseAddress =3D PcdGet32 (PcdSpiRegBase); + Slave->CoreClock =3D PcdGet32 (PcdSpiClockFrequency); + Slave->MaxFreq =3D PcdGet32 (PcdSpiMaxFrequency); + SpiSetupTransfer (This, Slave); =20 return Slave; diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Inc= lude/Protocol/Spi.h index 98fcc07..d993021 100644 --- a/Platform/Marvell/Include/Protocol/Spi.h +++ b/Platform/Marvell/Include/Protocol/Spi.h @@ -53,6 +53,8 @@ typedef struct { SPI_MODE Mode; UINT32 AddrSize; NOR_FLASH_INFO *Info; + UINTN HostRegisterBaseAddress; + UINTN CoreClock; } SPI_DEVICE; =20 typedef --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel