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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id a198sm1853649lfb.79.2017.11.05.02.55.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 05 Nov 2017 02:55:57 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vA8WmeWpxT1tdA9JeWO9jDRu5d3ALterRCtId1Mb7iQ=; b=hq2dwekJpWuA2ru1FnligSRWBa3y+ch3RcU/apSW5ExVlQDdYpuU/v+AFKp9C0SE4x rgfaIk2dPgxviT7A/DSkNryi/Fdo5n6eLRrJ4KJDpFTuW5wA4bHuz7VJoFzpTvSVWpz7 xzVVaIBJW95oqjHn1P/Waa5s8ZkvAQEjrDCcAzPfLvJrTLn5PnrSNxBPdzCVj74Yj824 /Q0ecJDyuQpfY6jxbeHylJfXJB3hP7qspaKcJMN0SftXYYjEOcXRe9LwGfT35tLc5ULu DDBiaZkxnNlFyCddti9Q64PPK2OukdI71/2KcD5lS7SMfjJEwDSJAhXePwa47N5TmY7b ++lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vA8WmeWpxT1tdA9JeWO9jDRu5d3ALterRCtId1Mb7iQ=; b=gQf6trxB00zD+MYh6OFkHGKgFDSP00dCRSntmgYjI46iTY3KyRs1UOKxwZT0SKhlcv 4ZaxXyeIlGLSs+y76EB2mE76jDTUknsxN9JkUemkqQxLHHETCShBgj39fR4rwGy9dxWd 8jPdbL8Xf5a8/R6TwCTRnSVpxvrNZsyLAUbT7y6fxw0xOS2Qqswg/ouVJgknSyDZFjic O48a8cNAzetoIT+x1NkXCoPOM1/evypklekL9N3yUvVMS93DzmCgxIdItjI3+N+4quVD YI1/p0eHKIHy8X5U31FBifjRf12gFoUsaADRbj60Jtu84+375bY3YXpb9Kh5wm9rQ465 2AfQ== X-Gm-Message-State: AJaThX7+xrDt8PkquKuh9Cs03sDS/1V7+abjKEcbfTj0lMklijV2HAYk nKNf48kwZWlbzLqUCOnBFXMgsWvBYyA= X-Google-Smtp-Source: ABhQp+QH/uPpERqPooi4/dtM27YqW2RVxvluavKlQdq4VS/rzaruyKmKcT98EKz0Wn3zn88ZAMlbuQ== X-Received: by 10.25.222.80 with SMTP id v77mr4653775lfg.151.1509879358257; Sun, 05 Nov 2017 02:55:58 -0800 (PST) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 5 Nov 2017 11:55:37 +0100 Message-Id: <1509879339-10516-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509879339-10516-1-git-send-email-mw@semihalf.com> References: <1509879339-10516-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 2/4] Marvell/Drivers: MvSpiDxe: Enable using driver in RT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch applies necessary modifications, which allow to use MvSpiDxe driver in variable support as a runtime service. Its type is modified to DXE_RUNTIME_DRIVER, as well as a new callback is introduced as a part of the SpiMasterProtocol. It is supposed to configure the memory space for mmio access to the host controller registers. Moreover gBS locking usage in MvSpiTransfer is limited to the firmware, as the runtime access to the flash is protected within the OS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 50 ++++++++++++++++++-- Platform/Marvell/Drivers/Spi/MvSpiDxe.h | 2 + Platform/Marvell/Drivers/Spi/MvSpiDxe.inf | 4 +- Platform/Marvell/Include/Protocol/Spi.h | 7 +++ 4 files changed, 58 insertions(+), 5 deletions(-) diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index c60a520..bab6cf4 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -211,7 +211,9 @@ MvSpiTransfer ( =20 Length =3D 8 * DataByteCount; =20 - EfiAcquireLock (&SpiMaster->Lock); + if (!EfiAtRuntime ()) { + EfiAcquireLock (&SpiMaster->Lock); + } =20 if (Flag & SPI_TRANSFER_BEGIN) { SpiActivateCs (Slave); @@ -254,7 +256,9 @@ MvSpiTransfer ( SpiDeactivateCs (Slave); } =20 - EfiReleaseLock (&SpiMaster->Lock); + if (!EfiAtRuntime ()) { + EfiReleaseLock (&SpiMaster->Lock); + } =20 return EFI_SUCCESS; } @@ -338,6 +342,44 @@ MvSpiFreeSlave ( return EFI_SUCCESS; } =20 +EFI_STATUS +EFIAPI +MvSpiConfigRuntime ( + IN SPI_DEVICE *Slave + ) +{ + EFI_STATUS Status; + UINTN AlignedAddress; + + // + // Host register base may be not aligned to the page size, + // which is not accepted when setting memory space attributes. + // Add one aligned page of memory space which covers the host + // controller registers. + // + AlignedAddress =3D Slave->HostRegisterBaseAddress & ~(SIZE_4KB - 1); + + Status =3D gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, + AlignedAddress, + SIZE_4KB, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to add memory space\n", __FUNCTION__)= ); + return Status; + } + + Status =3D gDS->SetMemorySpaceAttributes (AlignedAddress, + SIZE_4KB, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes\n", __FUNCTI= ON__)); + gDS->RemoveMemorySpace (AlignedAddress, SIZE_4KB); + return Status; + } + + return EFI_SUCCESS; +} + STATIC EFI_STATUS SpiMasterInitProtocol ( @@ -350,6 +392,7 @@ SpiMasterInitProtocol ( SpiMasterProtocol->FreeDevice =3D MvSpiFreeSlave; SpiMasterProtocol->Transfer =3D MvSpiTransfer; SpiMasterProtocol->ReadWrite =3D MvSpiReadWrite; + SpiMasterProtocol->ConfigRuntime =3D MvSpiConfigRuntime; =20 return EFI_SUCCESS; } @@ -363,8 +406,7 @@ SpiMasterEntryPoint ( { EFI_STATUS Status; =20 - mSpiMasterInstance =3D AllocateZeroPool (sizeof (SPI_MASTER)); - + mSpiMasterInstance =3D AllocateRuntimeZeroPool (sizeof (SPI_MASTER)); if (mSpiMasterInstance =3D=3D NULL) { return EFI_OUT_OF_RESOURCES; } diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.h b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.h index e7e280a..50cdc02 100644 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.h +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.h @@ -38,10 +38,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include #include #include +#include #include #include #include #include +#include =20 #include =20 diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf b/Platform/Marvell/D= rivers/Spi/MvSpiDxe.inf index 08c6c04..9fe246f 100644 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf @@ -33,7 +33,7 @@ INF_VERSION =3D 0x00010005 BASE_NAME =3D SpiMasterDxe FILE_GUID =3D c19dbc8a-f4f9-43b0-aee5-802e3ed03d15 - MODULE_TYPE =3D DXE_DRIVER + MODULE_TYPE =3D DXE_RUNTIME_DRIVER VERSION_STRING =3D 1.0 ENTRY_POINT =3D SpiMasterEntryPoint =20 @@ -53,8 +53,10 @@ TimerLib UefiLib DebugLib + DxeServicesTableLib MemoryAllocationLib IoLib + UefiRuntimeLib =20 [FixedPcd] gMarvellTokenSpaceGuid.PcdSpiRegBase diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Inc= lude/Protocol/Spi.h index d993021..abbad19 100644 --- a/Platform/Marvell/Include/Protocol/Spi.h +++ b/Platform/Marvell/Include/Protocol/Spi.h @@ -101,12 +101,19 @@ EFI_STATUS IN SPI_DEVICE *SpiDev ); =20 +typedef +EFI_STATUS +(EFIAPI *MV_SPI_CONFIG_RT) ( + IN SPI_DEVICE *SpiDev + ); + struct _MARVELL_SPI_MASTER_PROTOCOL { MV_SPI_INIT Init; MV_SPI_READ_WRITE ReadWrite; MV_SPI_TRANSFER Transfer; MV_SPI_SETUP_DEVICE SetupDevice; MV_SPI_FREE_DEVICE FreeDevice; + MV_SPI_CONFIG_RT ConfigRuntime; }; =20 #endif // __MARVELL_SPI_MASTER_PROTOCOL_H__ --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel