SocInit function to initialize peripherals and print board,
soc information.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
 Silicon/NXP/Chassis/Chassis2/Soc.c      | 47 ++++++++++++++++++++++++++++
 Silicon/NXP/Chassis/LS1043aSocLib.inf   |  2 ++
 Silicon/NXP/Chassis/LS1046aSocLib.inf   | 49 +++++++++++++++++++++++++++++
 Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 +++++++++++++++++++++++++++++++++
 4 files changed, 153 insertions(+)
 create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h

diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chassis2/Soc.c
index 2f57929..ebe690a 100644
--- a/Silicon/NXP/Chassis/Chassis2/Soc.c
+++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
@@ -17,6 +17,7 @@
 #include <Chassis.h>
 #include <Library/BaseLib.h>
 #include <Library/BaseMemoryLib/MemLibInternals.h>
+#include <Library/BeIoLib.h>
 #include <Library/DebugLib.h>
 #include <Library/IoLib.h>
 #include <Library/PcdLib.h>
@@ -116,6 +117,42 @@ GetSysInfo (
 }
 
 /**
+   Function to select pins depending upon pcd using supplemental
+   configuration unit(SCFG) extended RCW controlled pinmux control
+   register which contains the bits to provide pin multiplexing control.
+   This register is reset on HRESET.
+ **/
+VOID
+ConfigScfgMux (VOID)
+{
+  CCSR_SCFG *Scfg;
+  UINT32 UsbPwrFault;
+
+  Scfg = (VOID *)PcdGet64 (PcdScfgBaseAddr);
+  // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
+  // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
+
+  // LS1043A
+  // Configures functionality of the IIC4_SCL to USB3_DRVVBUS
+  // Configures functionality of the IIC4_SDA to USB3_PWRFAULT
+
+  // LS1046A
+  // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+  if (PcdGetBool (PcdMuxToUsb3))
+    BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_SELCR_USB);
+  else
+    BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB);
+  BeMmioWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, CCSR_SCFG_USBDRVVBUS_SELCR_USB1);
+  UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
+                CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
+                (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
+                CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
+                (CCSR_SCFG_USBPWRFAULT_SHARED <<
+                CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
+  BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+  BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+}
+/**
   Function to initialize SoC specific constructs
   // CPU Info
   // SoC Personality
@@ -141,5 +178,15 @@ SocInit (
   PrintCpuInfo ();
   PrintRCW ();
 
+  //
+  // Due to the extensive functionality present on the chip and the limited number of external
+  // signals available, several functional blocks share signal resources through multiplexing.
+  // In this case when there is alternate functionality between multiple functional blocks,
+  // the signal's function is determined at the chip level (rather than at the block level)
+  // typically by a reset configuration word (RCW) option. Some of the signals' function are
+  // determined externel to RCW at Power-on Reset Sequence.
+  //
+  ConfigScfgMux ();
+
   return;
 }
diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS1043aSocLib.inf
index e6e7ac4..4b1880e 100644
--- a/Silicon/NXP/Chassis/LS1043aSocLib.inf
+++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
@@ -45,3 +45,5 @@
   gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
   gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
   gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
+  gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
diff --git a/Silicon/NXP/Chassis/LS1046aSocLib.inf b/Silicon/NXP/Chassis/LS1046aSocLib.inf
new file mode 100644
index 0000000..9422a2a
--- /dev/null
+++ b/Silicon/NXP/Chassis/LS1046aSocLib.inf
@@ -0,0 +1,49 @@
+#  @file
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = SocLib
+  FILE_GUID                      = 5e9a2b48-a92a-4d55-87ec-e5e14a292f35
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SocLib
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/NXP/NxpQoriqLs.dec
+  Silicon/NXP/Chassis/Chassis2/Chassis2.dec
+  Silicon/NXP/LS1046A/LS1046A.dec
+
+[LibraryClasses]
+  BaseLib
+  BeIoLib
+  DebugLib
+  SerialPortLib
+
+[Sources.common]
+  Chassis.c
+  Chassis2/Soc.c
+  SerDes.c
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+  gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+  gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
+  gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+  gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
+  gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/Include/SocSerDes.h
new file mode 100644
index 0000000..4bc5e28
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h
@@ -0,0 +1,55 @@
+/** @file
+ The Header file of SerDes Module
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __LS1046A_SERDES_H__
+#define __LS1046A_SERDES_H__
+
+#include <SerDes.h>
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+        // SerDes 1
+        {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+        {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+        {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+        {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+        {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+        {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } },
+        {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } },
+        {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } },
+        {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6 } },
+        {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTSEC6 } },
+        {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+        {}
+};
+
+SERDES_CONFIG SerDes2ConfigTbl[] = {
+        // SerDes 2
+        {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+        {0x5559, {PCIE1, PCIE2, PCIE3, SATA } },
+        {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } },
+        {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } },
+        {0x0506, {NONE, PCIE2, NONE, PCIE3 } },
+        {0x0559, {NONE, PCIE2, PCIE3, SATA } },
+        {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } },
+        {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } },
+        {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+        SerDes1ConfigTbl,
+        SerDes2ConfigTbl
+};
+
+#endif /* __LS1046A_SERDES_H */
-- 
1.9.1

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