Adding support of ArmPlatformLib for NXP LS1046ARDB board

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
 .../Library/PlatformLib/ArmPlatformLib.c           | 106 ++++++++++++
 .../Library/PlatformLib/ArmPlatformLib.inf         |  70 ++++++++
 .../Library/PlatformLib/NxpQoriqLsHelper.S         |  39 +++++
 .../Library/PlatformLib/NxpQoriqLsMem.c            | 181 +++++++++++++++++++++
 4 files changed, 396 insertions(+)
 create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
 create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
 create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
 create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c

diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..795c7a9
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,106 @@
+/** ArmPlatformLib.c
+*
+*  Contains board initialization functions.
+*
+*  Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+ SocInit ();
+ return RETURN_SUCCESS;
+}
+
+ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (UINT64)0xFFFFFFFF
+  },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  *CoreCount    = sizeof (LS1046aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
+  *ArmCoreTable = LS1046aMpCoreInfoCTA72x4;
+
+  return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof (gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+  IN UINTN MpId
+  )
+{
+  return 1;
+}
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..13a0ffb
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,70 @@
+#/* @file
+#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = ArmPlatformLib
+  FILE_GUID                      = 177a95a8-27c2-4582-8ba9-c87aa3e0ba75
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  Platform/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ArmLib
+  SocLib
+
+[Sources.common]
+  NxpQoriqLsHelper.S    | GCC
+  ArmPlatformLib.c
+  NxpQoriqLsMem.c
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
+  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+  gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+  gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+  gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
+  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..55e750f
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,39 @@
+#  @file
+#
+#  Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardHelper.S
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  tst x0, #3
+  cset x0, eq
+  ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+EL1_OR_EL2(x0)
+1:
+2:
+  ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+  ldrh   w0, [x0]
+  ret
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..7022528
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,181 @@
+/** NxpQoriqLsMem.c
+*
+*  Board memory specific Library.
+*
+*  Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          25
+
+#define CCSR_BASE_ADDR            FixedPcdGet64 (PcdCcsrBaseAddr)
+#define CCSR_SIZE                 FixedPcdGet64 (PcdCcsrSize)
+#define IFC_REGION1_BASE_ADDR     FixedPcdGet64 (PcdIfcRegion1BaseAddr)
+#define IFC_REGION1_SIZE          FixedPcdGet64 (PcdIfcRegion1Size)
+#define IFC_REGION2_BASE_ADDR     FixedPcdGet64 (PcdIfcRegion2BaseAddr)
+#define IFC_REGION2_SIZE          FixedPcdGet64 (PcdIfcRegion2Size)
+#define QMAN_SWP_BASE_ADDR        FixedPcdGet64 (PcdQmanSwpBaseAddr)
+#define QMAN_SWP_SIZE             FixedPcdGet64 (PcdQmanSwpSize)
+#define BMAN_SWP_BASE_ADDR        FixedPcdGet64 (PcdBmanSwpBaseAddr)
+#define BMAN_SWP_SIZE             FixedPcdGet64 (PcdBmanSwpSize)
+#define PCI_EXP1_BASE_ADDR        FixedPcdGet64 (PcdPciExp1BaseAddr)
+#define PCI_EXP1_BASE_SIZE        FixedPcdGet64 (PcdPciExp1BaseSize)
+#define PCI_EXP2_BASE_ADDR        FixedPcdGet64 (PcdPciExp2BaseAddr)
+#define PCI_EXP2_BASE_SIZE        FixedPcdGet64 (PcdPciExp2BaseSize)
+#define PCI_EXP3_BASE_ADDR        FixedPcdGet64 (PcdPciExp3BaseAddr)
+#define PCI_EXP3_BASE_SIZE        FixedPcdGet64 (PcdPciExp3BaseSize)
+#define DRAM1_BASE_ADDR           FixedPcdGet64 (PcdDram1BaseAddr)
+#define DRAM1_SIZE                FixedPcdGet64 (PcdDram1Size)
+#define DRAM2_BASE_ADDR           FixedPcdGet64 (PcdDram2BaseAddr)
+#define DRAM2_SIZE                FixedPcdGet64 (PcdDram2Size)
+#define DRAM3_BASE_ADDR           FixedPcdGet64 (PcdDram3BaseAddr)
+#define DRAM3_SIZE                FixedPcdGet64 (PcdDram3Size)
+#define QSPI_REGION_BASE_ADDR     FixedPcdGet64 (PcdQspiRegionBaseAddr)
+#define QSPI_REGION_SIZE          FixedPcdGet64 (PcdQspiRegionSize)
+
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
+  UINTN                         Index = 0;
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+
+  ASSERT (VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+  if (VirtualMemoryTable == NULL) {
+    return;
+  }
+
+  if (FeaturePcdGet (PcdCacheEnable) == TRUE) {
+    CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+  } else {
+    CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+  }
+
+  // DRAM1 (Must be 1st entry)
+  VirtualMemoryTable[Index].PhysicalBase = DRAM1_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = DRAM1_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = DRAM1_SIZE;
+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+
+  // CCSR Space
+  VirtualMemoryTable[++Index].PhysicalBase = CCSR_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = CCSR_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = CCSR_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // IFC region 1
+  //
+  // A-009241   : Unaligned write transactions to IFC may result in corruption of data
+  // Affects    : IFC
+  // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+  //              writes on external IFC interface that can corrupt data on external flash.
+  // Impact     : Data corruption on external flash may happen in case of unaligned writes to
+  //              IFC memory space.
+  // Workaround: Following are the workarounds:
+  //             � For write transactions from core, IFC interface memories (including IFC SRAM)
+  //                should be configured as �device type" memory in MMU.
+  //             � For write transactions from non-core masters (like system DMA), the address
+  //                should be 16 byte aligned and the data size should be multiple of 16 bytes.
+  //
+  VirtualMemoryTable[++Index].PhysicalBase = IFC_REGION1_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = IFC_REGION1_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = IFC_REGION1_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // QMAN SWP
+  VirtualMemoryTable[++Index].PhysicalBase = QMAN_SWP_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = QMAN_SWP_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = QMAN_SWP_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+  // BMAN SWP
+  VirtualMemoryTable[++Index].PhysicalBase = BMAN_SWP_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = BMAN_SWP_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = BMAN_SWP_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+  // IFC region 2
+  VirtualMemoryTable[++Index].PhysicalBase = IFC_REGION2_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = IFC_REGION2_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = IFC_REGION2_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // DRAM2
+  VirtualMemoryTable[++Index].PhysicalBase = DRAM2_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = DRAM2_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = DRAM2_SIZE;
+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+
+  // PCIe1
+  VirtualMemoryTable[++Index].PhysicalBase = PCI_EXP1_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = PCI_EXP1_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = PCI_EXP1_BASE_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // PCIe2
+  VirtualMemoryTable[++Index].PhysicalBase = PCI_EXP2_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = PCI_EXP2_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = PCI_EXP2_BASE_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // PCIe3
+  VirtualMemoryTable[++Index].PhysicalBase = PCI_EXP3_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = PCI_EXP3_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = PCI_EXP3_BASE_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // DRAM3
+  VirtualMemoryTable[++Index].PhysicalBase = DRAM3_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = DRAM3_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = DRAM3_SIZE;
+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+
+  // QSPI region
+  VirtualMemoryTable[++Index].PhysicalBase = QSPI_REGION_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = QSPI_REGION_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = QSPI_REGION_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase = 0;
+  VirtualMemoryTable[Index].VirtualBase  = 0;
+  VirtualMemoryTable[Index].Length       = 0;
+  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+  ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
-- 
1.9.1

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