On NXP Layerscape SoCs,NOR Flash device interfacing is
via IFC and IfcFlashLib provides helper functions to be
used by NXP NOR flash library

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
 Platform/NXP/Include/Library/Ifc.h                 | 147 +++++++++++++++++++++
 Platform/NXP/Include/Library/IfcBase.h             | 139 +++++++++++++++++++
 .../Include/Library/IfcBoardSpecificLib.h          |  50 +++++++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc       |   2 +
 Platform/NXP/Library/IfcFlashLib/IfcFlashLib.c     |  70 ++++++++++
 Platform/NXP/Library/IfcFlashLib/IfcFlashLib.inf   |  33 +++++
 Platform/NXP/NxpQoriqLs.dec                        |   1 +
 7 files changed, 442 insertions(+)
 create mode 100755 Platform/NXP/Include/Library/Ifc.h
 create mode 100644 Platform/NXP/Include/Library/IfcBase.h
 create mode 100755 Platform/NXP/LS1043aRdbPkg/Include/Library/IfcBoardSpecificLib.h
 create mode 100644 Platform/NXP/Library/IfcFlashLib/IfcFlashLib.c
 create mode 100644 Platform/NXP/Library/IfcFlashLib/IfcFlashLib.inf

diff --git a/Platform/NXP/Include/Library/Ifc.h b/Platform/NXP/Include/Library/Ifc.h
new file mode 100755
index 0000000..dd36fd8
--- /dev/null
+++ b/Platform/NXP/Include/Library/Ifc.h
@@ -0,0 +1,147 @@
+/** @Ifc.h
+
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __IFC_H__
+#define __IFC_H__
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IfcBase.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define IFC_BANK_COUNT        4
+
+#define IFC_CSPR_REG_LEN      148
+#define IFC_AMASK_REG_LEN     144
+#define IFC_CSOR_REG_LEN      144
+#define IFC_FTIM_REG_LEN      576
+
+#define IFC_CSPR_USED_LEN     sizeof (IFC_CSPR) * \
+                              IFC_BANK_COUNT
+
+#define IFC_AMASK_USED_LEN    sizeof (IFC_AMASK) * \
+                              IFC_BANK_COUNT
+
+#define IFC_CSOR_USED_LEN     sizeof (IFC_CSOR) * \
+                              IFC_BANK_COUNT
+
+#define IFC_FTIM_USED_LEN     sizeof (IFC_FTIM) * \
+                              IFC_BANK_COUNT
+
+typedef enum {
+  IFC_CS0 = 0,
+  IFC_CS1,
+  IFC_CS2,
+  IFC_CS3,
+  IFC_CS4,
+  IFC_CS5,
+  IFC_CS6,
+  IFC_CS7,
+} IFC_CHIP_SEL;
+
+typedef enum {
+  IFC_FTIM0 = 0,
+  IFC_FTIM1,
+  IFC_FTIM2,
+  IFC_FTIM3,
+} IFC_FTIMS;
+
+typedef struct {
+  UINT32 CsprExt;
+  UINT32 Cspr;
+  UINT32 Res;
+} IFC_CSPR;
+
+typedef struct {
+  UINT32 Amask;
+  UINT32 Res[0x2];
+} IFC_AMASK;
+
+typedef struct {
+  UINT32 Csor;
+  UINT32 CsorExt;
+  UINT32 Res;
+} IFC_CSOR;
+
+typedef struct {
+  UINT32 Ftim[4];
+  UINT32 Res[0x8];
+}IFC_FTIM ;
+
+/*
+ * IFC controller NOR Machine registers
+ */
+typedef struct {
+  UINT32 NorEvterStat;
+  UINT32 Res1[0x2];
+  UINT32 NorEvterEn;
+  UINT32 Res2[0x2];
+  UINT32 NorEvterIntrEn;
+  UINT32 Res3[0x2];
+  UINT32 NorErattr0;
+  UINT32 NorErattr1;
+  UINT32 NorErattr2;
+  UINT32 Res4[0x4];
+  UINT32 NorCr;
+  UINT32 Res5[0xEF];
+} IFC_NOR;
+
+/*
+ * IFC Controller Registers
+ */
+typedef struct {
+  UINT32      IfcRev;
+  UINT32      Res1[0x2];
+  IFC_CSPR    CsprCs[IFC_BANK_COUNT];
+  UINT8       Res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
+  IFC_AMASK   AmaskCs[IFC_BANK_COUNT];
+  UINT8       Res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
+  IFC_CSOR    CsorCs[IFC_BANK_COUNT];
+  UINT8       Res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
+  IFC_FTIM    FtimCs[IFC_BANK_COUNT];
+  UINT8       Res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
+  UINT32      RbStat;
+  UINT32      RbMap;
+  UINT32      WpMap;
+  UINT32      IfcGcr;
+  UINT32      Res7[0x2];
+  UINT32      CmEvter_stat;
+  UINT32      Res8[0x2];
+  UINT32      CmEvterEn;
+  UINT32      Res9[0x2];
+  UINT32      CmEvterIntrEn;
+  UINT32      Res10[0x2];
+  UINT32      CmErattr0;
+  UINT32      CmErattr1;
+  UINT32      Res11[0x2];
+  UINT32      IfcCcr;
+  UINT32      IfcCsr;
+  UINT32      DdrCcrLow;
+  UINT32      Res12[0x2EA];
+  IFC_NOR     IfcNor;
+} IFC_REGS;
+
+typedef struct {
+  UINT32 Ftim[IFC_BANK_COUNT];
+  UINT32 CsprExt;
+  UINT32 Cspr;
+  UINT32 Csor;
+  UINT32 Amask;
+} IfcTimings;
+
+#endif //__IFC_H__
diff --git a/Platform/NXP/Include/Library/IfcBase.h b/Platform/NXP/Include/Library/IfcBase.h
new file mode 100644
index 0000000..7020a29
--- /dev/null
+++ b/Platform/NXP/Include/Library/IfcBase.h
@@ -0,0 +1,139 @@
+/** @IfcLib.h
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __IFC_COMMON_H__
+#define __IFC_COMMON_H__
+
+#define NOR_FLASH_DEVICE_COUNT      1
+
+#define MAX_RETRY_COUNT           150000
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+
+#define IFC_CSPR_BA               0xFFFF0000
+#define IFC_CSPR_BA_SHIFT         16
+#define IFC_CSPR_PORT_SIZE        0x00000180
+#define IFC_CSPR_PORT_SIZE_SHIFT  7
+
+// Port Size 8 bit
+#define IFC_CSPR_PORT_SIZE_8      0x00000080
+
+// Port Size 16 bit
+#define IFC_CSPR_PORT_SIZE_16     0x00000100
+
+// Port Size 32 bit
+#define IFC_CSPR_PORT_SIZE_32     0x00000180
+
+// Write Protect
+#define IFC_CSPR_WP           0x00000040
+#define IFC_CSPR_WP_SHIFT     6
+
+// Machine Select
+#define IFC_CSPR_MSEL         0x00000006
+#define IFC_CSPR_MSEL_SHIFT   1
+
+// NOR
+#define IFC_CSPR_MSEL_NOR     0x00000000
+
+// Bank Valid
+#define IFC_CSPR_V            0x00000001
+#define IFC_CSPR_V_SHIFT      0
+
+/*
+ * Chip Select Option Register - NOR Flash Mode
+ */
+
+// Enable Address shift Mode
+#define IFC_CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
+
+// Page Read Enable from NOR device
+#define IFC_CSOR_NOR_PGRD_EN          0x10000000
+
+// AVD Toggle Enable during Burst Program
+#define IFC_CSOR_NOR_AVD_TGL_PGM_EN   0x01000000
+
+// Address Data Multiplexing Shift
+#define IFC_CSOR_NOR_ADM_MASK         0x0003E000
+#define IFC_CSOR_NOR_ADM_SHIFT_SHIFT  13
+#define IFC_CSOR_NOR_ADM_SHIFT(n)     ((n) << IFC_CSOR_NOR_ADM_SHIFT_SHIFT)
+
+// Type of the NOR device hooked
+#define IFC_CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
+#define IFC_CSOR_NOR_NOR_MODE_AVD_NOR   0x00000020
+
+// Time for Read Enable High to Output High Impedance
+#define IFC_CSOR_NOR_TRHZ_MASK    0x0000001C
+#define IFC_CSOR_NOR_TRHZ_SHIFT   2
+#define IFC_CSOR_NOR_TRHZ_20      0x00000000
+#define IFC_CSOR_NOR_TRHZ_40      0x00000004
+#define IFC_CSOR_NOR_TRHZ_60      0x00000008
+#define IFC_CSOR_NOR_TRHZ_80      0x0000000C
+#define IFC_CSOR_NOR_TRHZ_100     0x00000010
+
+// Buffer control disable
+#define IFC_CSOR_NOR_BCTLD        0x00000001
+
+/*
+ * FTIM0 - NOR Flash Mode
+ */
+#define IFC_FTIM0_NOR               0xF03F3F3F
+#define IFC_FTIM0_NOR_TACSE_SHIFT   28
+#define IFC_FTIM0_NOR_TACSE(n)      ((n) << IFC_FTIM0_NOR_TACSE_SHIFT)
+#define IFC_FTIM0_NOR_TEADC_SHIFT   16
+#define IFC_FTIM0_NOR_TEADC(n)      ((n) << IFC_FTIM0_NOR_TEADC_SHIFT)
+#define IFC_FTIM0_NOR_TAVDS_SHIFT   8
+#define IFC_FTIM0_NOR_TAVDS(n)      ((n) << IFC_FTIM0_NOR_TAVDS_SHIFT)
+#define IFC_FTIM0_NOR_TEAHC_SHIFT   0
+#define IFC_FTIM0_NOR_TEAHC(n)      ((n) << IFC_FTIM0_NOR_TEAHC_SHIFT)
+
+/*
+ * FTIM1 - NOR Flash Mode
+ */
+#define IFC_FTIM1_NOR                   0xFF003F3F
+#define IFC_FTIM1_NOR_TACO_SHIFT        24
+#define IFC_FTIM1_NOR_TACO(n)           ((n) << IFC_FTIM1_NOR_TACO_SHIFT)
+#define IFC_FTIM1_NOR_TRAD_NOR_SHIFT    8
+#define IFC_FTIM1_NOR_TRAD_NOR(n)       ((n) << IFC_FTIM1_NOR_TRAD_NOR_SHIFT)
+#define IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
+#define IFC_FTIM1_NOR_TSEQRAD_NOR(n)    ((n) << IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT)
+
+/*
+ * FTIM2 - NOR Flash Mode
+ */
+#define IFC_FTIM2_NOR                   0x0F3CFCFF
+#define IFC_FTIM2_NOR_TCS_SHIFT         24
+#define IFC_FTIM2_NOR_TCS(n)            ((n) << IFC_FTIM2_NOR_TCS_SHIFT)
+#define IFC_FTIM2_NOR_TCH_SHIFT         18
+#define IFC_FTIM2_NOR_TCH(n)            ((n) << IFC_FTIM2_NOR_TCH_SHIFT)
+#define IFC_FTIM2_NOR_TWPH_SHIFT        10
+#define IFC_FTIM2_NOR_TWPH(n)           ((n) << IFC_FTIM2_NOR_TWPH_SHIFT)
+#define IFC_FTIM2_NOR_TWP_SHIFT         0
+#define IFC_FTIM2_NOR_TWP(n)            ((n) << IFC_FTIM2_NOR_TWP_SHIFT)
+
+/* Convert an address into the right format for the CSPR Registers */
+#define IFC_CSPR_PHYS_ADDR(x)   (((UINTN)x) & 0xffff0000)
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK      0xFFFF0000
+#define IFC_AMASK_SHIFT     16
+#define IFC_AMASK(n)        (IFC_AMASK_MASK << \
+                            (HighBitSet32(n) - IFC_AMASK_SHIFT))
+
+VOID IfcNorInit(VOID);
+
+#endif //__IFC_COMMON_H__
diff --git a/Platform/NXP/LS1043aRdbPkg/Include/Library/IfcBoardSpecificLib.h b/Platform/NXP/LS1043aRdbPkg/Include/Library/IfcBoardSpecificLib.h
new file mode 100755
index 0000000..aaef340
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Include/Library/IfcBoardSpecificLib.h
@@ -0,0 +1,50 @@
+/** IfcBoardSpecificLib.h
+  IFC Flash Board Specific library
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __IFC__BOARD_SPECIFIC_LIB_H__
+#define __IFC__BOARD_SPECIFIC_LIB_H__
+
+// On board flash support,endianness
+#define NOR_SUPPORT
+#define IFC_REG_BASE         0x1530000
+#define IFC_NOR_BUF_BASE     0x60000000
+
+// On board Inegrated flash Controller chip select configuration
+#define IFC_NOR_CS    IFC_CS0
+
+// board-specific NOR flash timing
+#define NOR_FTIM0     (IFC_FTIM0_NOR_TACSE(0x1) | \
+                      IFC_FTIM0_NOR_TEADC(0x1) | \
+                      IFC_FTIM0_NOR_TAVDS(0x0) | \
+                      IFC_FTIM0_NOR_TEAHC(0xc))
+#define NOR_FTIM1     (IFC_FTIM1_NOR_TACO(0x1c) | \
+                      IFC_FTIM1_NOR_TRAD_NOR(0xb) |\
+                      IFC_FTIM1_NOR_TSEQRAD_NOR(0x9))
+#define NOR_FTIM2     (IFC_FTIM2_NOR_TCS(0x1) | \
+                      IFC_FTIM2_NOR_TCH(0x4) | \
+                      IFC_FTIM2_NOR_TWPH(0x8) | \
+                      IFC_FTIM2_NOR_TWP(0x10))
+#define NOR_FTIM3     0x0
+
+#define NOR_CSPR      (IFC_CSPR_PHYS_ADDR(IFC_NOR_BUF_BASE) \
+                      | IFC_CSPR_PORT_SIZE_16 \
+                      | IFC_CSPR_MSEL_NOR        \
+                      | IFC_CSPR_V)
+
+#define NOR_CSPR_EXT  0x0
+#define NOR_AMASK     IFC_AMASK(128*1024*1024)
+#define NOR_CSOR      (IFC_CSOR_NOR_ADM_SHIFT(4) | \
+                      IFC_CSOR_NOR_TRHZ_80)
+
+#endif //__IFC__BOARD_SPECIFIC_LIB_H__
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 1951e82..7a72338 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -47,12 +47,14 @@
   #
   gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
   gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcNorEnabled|1
 
   #
   # Big Endian IPs
   #
   gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
   gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
 
   #
   # I2C controller Pcds
diff --git a/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.c b/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.c
new file mode 100644
index 0000000..c9e8bc4
--- /dev/null
+++ b/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.c
@@ -0,0 +1,70 @@
+/** @IfcFlashLib.c
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BeIoLib.h>
+#include <Library/NorFlashLib.h>
+// Include board specific file for Flash timing
+#include <LS1043aRdbPkg/Include/Library/IfcBoardSpecificLib.h>
+
+#ifdef NOR_SUPPORT
+VOID
+GetIfcNorFlashInfo (
+  IN NorFlashInfo *NorFlashInfo
+  )
+{
+  NorFlashInfo->IfcRegs = (IFC_REGS*) IFC_REG_BASE;
+  NorFlashInfo->ChipSelect = IFC_NOR_CS;
+  return ;
+}
+
+VOID
+GetIfcNorFlashTimings (
+  IN IfcTimings * NorIfcTimings
+  )
+{
+  NorIfcTimings->Ftim[0] = NOR_FTIM0;
+  NorIfcTimings->Ftim[1] = NOR_FTIM1;
+  NorIfcTimings->Ftim[2] = NOR_FTIM2;
+  NorIfcTimings->Ftim[3] = NOR_FTIM3;
+  NorIfcTimings->Cspr = NOR_CSPR;
+  NorIfcTimings->CsprExt = NOR_CSPR_EXT;
+  NorIfcTimings->Amask = NOR_AMASK;
+  NorIfcTimings->Csor = NOR_CSOR;
+  return ;
+}
+
+VOID IfcNorWrite32 (VOID *a, UINT32 v) {
+
+  if (FixedPcdGetBool (PcdIfcBigEndian)) {
+    BeMmioWrite32 ((UINTN)a, v);
+  } else {
+    MmioWrite32 ((UINTN)a, v);
+  }
+
+}
+
+FLASH_DATA
+IfcNorFlashData (
+  FLASH_DATA Value
+  )
+{
+
+  if (FixedPcdGetBool (PcdIfcBigEndian)) {
+    return SwapBytes16 (Value);
+  } else {
+    return Value;
+  }
+
+}
+#endif //NOR_SUPPORT
diff --git a/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.inf b/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.inf
new file mode 100644
index 0000000..8447c7f
--- /dev/null
+++ b/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.inf
@@ -0,0 +1,33 @@
+#/** IfcFlashLib.inf
+#
+#  Component description file for IFC FLASH Library
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = IfcFlashLib
+  FILE_GUID                      = 8ecefc8f-a2c4-4091-b80f-92da7c4ab37f
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = IfcFlashLib
+
+[Sources.common]
+  IfcFlashLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Platform/NXP/NxpQoriqLs.dec
+
+[Pcd]
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian
diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec
index fd07eee..e773bcd 100644
--- a/Platform/NXP/NxpQoriqLs.dec
+++ b/Platform/NXP/NxpQoriqLs.dec
@@ -240,6 +240,7 @@
   gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
   gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
   gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|FALSE|BOOLEAN|0x00000313
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
 
   #
   # System ID Eeprom Pcds
-- 
1.9.1

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