From nobody Mon Dec 23 14:27:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1517991937926891.9641901972692; Wed, 7 Feb 2018 00:25:37 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4E51721F0DA69; Wed, 7 Feb 2018 00:19:53 -0800 (PST) Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EADEB223972A1 for ; Wed, 7 Feb 2018 00:19:51 -0800 (PST) Received: by mail-pl0-x241.google.com with SMTP id p5so32905plo.12 for ; Wed, 07 Feb 2018 00:25:35 -0800 (PST) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id k127sm1984999pga.92.2018.02.07.00.25.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Feb 2018 00:25:34 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yoVVwN/uzRWucY9XI1V3sx6klaNIUWZHRjNwPhGIbGs=; b=HP/3G2ZqpkNu0uNxUv78WZbdJZaRrl/1NeTVDaAFJ73Vz7vo+8X4KS8aU8OkKncxo3 /KDxavqMJSP+WUO1X9vHkK5Fu0oeKscI2dkOZDtFYP4jtF3C+PvrDlRZ/uXblZ1K+sFf XPp8HazH8Oj6Hp6SmKwpXApEygv/sve6QDcwQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yoVVwN/uzRWucY9XI1V3sx6klaNIUWZHRjNwPhGIbGs=; b=JhFo+lyQw4K38S6sQBNAQfGwz9tJ8N8gd23YGqg4SekT3TMh6pJw33vvqITOdqE8QW YzBSsJZz/5bobnJZ/WtJihPgmXTQ1Ii2B+JLZtOh1+9JN4YuikID4hERN2ikm4NUMeq6 UfOcC1oawQid+aiduEcEzJ7XbO/WD/mi8zLK+I/tfQPnMTkJ71My+ngCrtZnbqLqGTRH oOIKZNhCIRKzpLPFdCEFYTlS19UEnfLyxT/qQrVbcvzKbtJ79mgfnRMDe4RvuTjTyrK+ gn9rAMm+ltIuO9B1CxsMNLUDe0zFmMQ9XGdoCnqZmDWakBgd1XRNxMaaRNzIjQcrZ/pg PFcw== X-Gm-Message-State: APf1xPBmeoHoRI9ku0WjXV5x21SUpbhujWelF8CzkcDr99oLv+Sl2n8M 2OcH83zB8LMOH3Ogrq6mYMRI9w== X-Google-Smtp-Source: AH8x227XxN5GzFyfgJr/SWVcoCgKuMV9U+WAPN/t1pq7LhZvgGCGPVLUDlDdZFDT5Sy42guHl5M8YQ== X-Received: by 2002:a17:902:3103:: with SMTP id w3-v6mr5342867plb.3.1517991935292; Wed, 07 Feb 2018 00:25:35 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 7 Feb 2018 16:22:44 +0800 Message-Id: <1517991769-5485-11-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> References: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 10/15] Hisilicon/PCIe: Disable PCIe ASPM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Yan Zhang , Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In order to replace command line parameter pcie_aspm=3Doff, BIOS needs to disable Pcie Aspm support during Pcie initilization. D03 and D05 do not support PCIe ASPM, so we disable it in BIOS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Signed-off-by: Yan Zhang Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 ++++++++= ++++++++++++ Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 + Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 + 3 files changed, 107 insertions(+) diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/= Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index f420c91..c1c3fbb 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -1033,6 +1033,106 @@ DisableRcOptionRom ( return; } =20 +STATIC +VOID +PcieDbiCs2Enable ( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN BOOLEAN Val + ) +{ + UINT32 RegVal; + + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_S= YS_CTRL21, + RegVal + ); + if (Val) { + RegVal =3D RegVal | BIT2; + /* BIT2: DBI Chip Select indicator. 0 indicates CS, 1 indicates CS2.*/ + } else { + RegVal =3D RegVal & (~BIT2); + } + RegWrite ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_S= YS_CTRL21, + RegVal + ); +} + +STATIC +BOOLEAN +PcieDBIReadOnlyWriteEnable ( + IN UINT32 HostBridgeNum, + IN UINT32 Port + ) +{ + UINT32 Val; + + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRI= TE_ENABLE, + Val + ); + if (Val =3D=3D 0x1) { + return TRUE; + } else { + RegWrite ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_W= RITE_ENABLE, + 0x1 + ); + /* Delay 10us to make sure the PCIE device have enouph time to respons= e. */ + MicroSecondDelay(10); + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_W= RITE_ENABLE, + Val + ); + if (Val =3D=3D 0x1) { + return TRUE; + } + } + DEBUG ((DEBUG_ERROR,"PcieDBIReadOnlyWriteEnable Fail!!!\n")); + return FALSE; +} + +STATIC +VOID +SwitchPcieASPMSupport ( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN UINT8 Val + ) +{ + PCIE_EP_PCIE_CAP3_U PcieCap3; + + if (Port >=3D PCIE_MAX_ROOTBRIDGE) { + DEBUG ((DEBUG_ERROR, "Port is not valid\n")); + return; + } + if (!PcieDBIReadOnlyWriteEnable (HostBridgeNum, Port)) { + DEBUG ((DEBUG_INFO, "PcieDBI ReadOnly Reg do not Enable!!!\n")); + return; + } + PcieDbiCs2Enable (HostBridgeNum, Port, FALSE); + + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, + PcieCap3.UInt32 + ); + PcieCap3.Bits.active_state_power_management =3D Val; + RegWrite ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, + PcieCap3.UInt32 + ); + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, + PcieCap3.UInt32 + ); + DEBUG ((DEBUG_INFO, + "ASPI active state power management: %d\n", + PcieCap3.Bits.active_state_power_management)); + + PcieDbiCs2Enable (HostBridgeNum, Port, TRUE); +} + EFI_STATUS EFIAPI PciePortInit ( @@ -1090,6 +1190,9 @@ PciePortInit ( /* disable link up interrupt */ (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex); =20 + /* disable ASPM */ + SwitchPcieASPMSupport (HostBridgeNum, PortIndex, PCIE_ASPM_DISABLE); + /* Pcie Equalization*/ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex); =20 diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/= Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 9a0f636..e96c53c 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -77,6 +77,8 @@ #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) =3D MmioRead32 (addr)) =20 +#define PCIE_ASPM_DISABLE 0x0 +#define PCIE_ASPM_ENABLE 0x1 =20 typedef struct tagPcieDebugInfo { diff --git a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Silicon= /Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index bf57652..c8b9781 100644 --- a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -135,6 +135,7 @@ #define PCIE_EEP_PORTLOGIC53_REG (0x888) #define PCIE_EEP_GEN3_CONTRL_REG (0x890) #define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8) +#define PCIE_DBI_READ_ONLY_WRITE_ENABLE (0x8BC) #define PCIE_EEP_PORTLOGIC54_REG (0x900) #define PCIE_EEP_PORTLOGIC55_REG (0x904) #define PCIE_EEP_PORTLOGIC56_REG (0x908) @@ -12556,6 +12557,7 @@ typedef union tagPortlogic93 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (PCIE_SUBCTRL_B= ASE + 0x1018) #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (PCIE_SUBCTRL_B= ASE + 0x101C) #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG (PCIE_SUBCTRL_B= ASE + 0x1020) +#define PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21 (PCIE_SUBCTRL_B= ASE + 0x1024) #define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG (PCIE_SUBCTRL_B= ASE + 0x1030) #define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG (PCIE_SUBCTRL_B= ASE + 0x1100) #define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG (PCIE_SUBCTRL_B= ASE + 0x1104) --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel