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charset="utf-8" From: Meenakshi Aggarwal Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- .../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++ .../Library/PlatformLib/ArmPlatformLib.inf | 67 +++++++++ .../Library/PlatformLib/NxpQoriqLsHelper.S | 38 ++++++ .../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++= ++++ 4 files changed, 362 insertions(+) create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.c create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.inf create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriq= LsHelper.S create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriq= LsMem.c diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c new file mode 100644 index 0000000..ab4815d --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c @@ -0,0 +1,105 @@ +/** ArmPlatformLib.c +* +* Contains board initialization functions. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include + +extern VOID SocInit (VOID); + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Placeholder for Platform Initialization +**/ +EFI_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + SocInit (); + + return EFI_SUCCESS; +} + +ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, +}; + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_I= NFO); + *ArmCoreTable =3D LS1043aMpCoreInfoCTA53x4; + + return EFI_SUCCESS; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} + + +UINTN +ArmPlatformGetCorePosition ( + IN UINTN MpId + ) +{ + return 1; +} diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf new file mode 100644 index 0000000..7feac56 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -0,0 +1,67 @@ +# @file +# +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformLib + FILE_GUID =3D 736343a0-1d96-11e0-aaaa-0002a5d5c51b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ArmLib + SocLib + +[Sources.common] + NxpQoriqLsHelper.S | GCC + NxpQoriqLsMem.c + ArmPlatformLib.c + +[Ppis] + gArmMpCoreInfoPpiGuid + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelpe= r.S b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S new file mode 100644 index 0000000..205c0d8 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S @@ -0,0 +1,38 @@ +# @file +# +# Copyright (c) 2012-2013, ARM Limited. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +#include +#include + +.text +.align 2 + +GCC_ASM_IMPORT(ArmReadMpidr) + +ASM_FUNC(ArmPlatformIsPrimaryCore) + tst x0, #3 + cset x0, eq + ret + +ASM_FUNC(ArmPlatformPeiBootAction) +EL1_OR_EL2(x0) +1: +2: + ret + +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore)) + ldrh w0, [x0] + ret diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c new file mode 100644 index 0000000..64c5612 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -0,0 +1,152 @@ +/** NxpQoriqLsMem.c +* +* Board memory specific Library. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may b= e found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing a Physical-to- + Virtual Memory mapping. This array must be = ended by a zero-filled + entry + +**/ + +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + UINTN Index; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + Index =3D 0; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages ( + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_V= IRTUAL_MEMORY_MAP_DESCRIPTORS)); + + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + // DRAM1 (Must be 1st entry) + VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64 (PcdDram1BaseAd= dr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram1BaseAd= dr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDram1Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // CCSR Space + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdCcsrBaseA= ddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdCcsrBaseAdd= r); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdCcsrSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // IFC region 1 + // + // A-009241 : Unaligned write transactions to IFC may result in corrup= tion of data + // Affects : IFC + // Description: 16 byte unaligned write from system bus to IFC may resul= t in extra unintended + // writes on external IFC interface that can corrupt data o= n external flash. + // Impact : Data corruption on external flash may happen in case of = unaligned writes to + // IFC memory space. + // Workaround: Following are the workarounds: + // For write transactions from core, IFC interface memories = (including IFC SRAM) + // should be configured as device type memory in MMU. + // For write transactions from non-core masters (like system= DMA), the address + // should be 16 byte aligned and the data size should be = multiple of 16 bytes. + // + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 1BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion1B= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion1S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // QMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQmanSwpBa= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQmanSwpBase= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQmanSwpSize= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // BMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdBmanSwpBa= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdBmanSwpBase= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdBmanSwpSize= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // IFC region 2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 2BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion2B= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion2S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DRAM2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDram2Base= Addr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram2BaseAd= dr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDram2Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // PCIe1 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp1Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp1Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp1Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp2Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp2Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp2Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe3 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp3Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp3Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp3Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DRAM3 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDram3Base= Addr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram3BaseAd= dr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDram3Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // QSPI region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQspiRegio= nBaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQspiRegionB= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQspiRegionS= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + ASSERT ((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel