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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p83sm3775112lfg.41.2018.02.16.08.35.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Feb 2018 08:35:34 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PaW6rg2XOM1ndgxHE9YazQ+ZMvC15+a3YUA4/UgIMb4=; b=YgZ/URTIrqfjOTbRzGO9puYgumiDEf6ejj4AWB+a20Rgi+VJ0v7Rxphd1nJXbDIt31 cGj/fHs/SuDDpkUJ9t5N/yUsF5ryUWFehNemZYqqxRehASfNtW6cAlh6g6EgLWaDHXj2 QSgD3AfRNw6IWHNP+mDlj3tOXikqOtZZZUdKrH1SFEO5PwnNw5CKsUg5g5z5IcNce8Ox Ht8haZD0NzBJM+ofZah1tXetICdASiP71/0ByOFNMGOr8e8CB92XDwLMHsF7CII9GVZx z3EE9UKKycgUjHsKqgBqB8IzskqjnHHjVM2QR4TSktPSTWuFd1B0+I9PNE/uZbyVU8y2 zJqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PaW6rg2XOM1ndgxHE9YazQ+ZMvC15+a3YUA4/UgIMb4=; b=snraLI0Y8cTcEQHPumx1o/I+ZKMddT8Ufk/m9DmSxy4Ni/ehpMWXthp9clKGnn13jD f2jhy1l0HOflWO/O+Unz58XxKEHUPs+/3ju0Rv6VYK83+GbcJlJq0ANU8qcMWTVOp4ZI bHi2FjYaNYJG5fkGd5hRCT9Cl6m/dsiJOdv00zztM+EYWG/GGB+AzYB6dxCPUYmErsgI KH65/tZ77ZSO8aPQ+1O/HnETvVwFdvd4YHdXOnTcRVmx3tIZAD+91ypnwwa0tbPXWGOe gLQaMACrXe0yW/jeUIeiRQKa0AeE6RKFFWq/4ztXrkPmQFwrzJerRo6srvu9Fq9nnvD8 kULA== X-Gm-Message-State: APf1xPDIiDglFg4/lKwloR168qh8uOCrO+jYf0pjgY9Ck8JZFZAn9EEx hhlpGUWLzt/+4Yot6w/pBl7qfjGl81s= X-Google-Smtp-Source: AH8x2246TVI+nFyR+rh2k/w5z70kstrOUfDnnrk5yiD7kOg59kaHXY8b0mqXor4mmSJe6PMKKAYzTA== X-Received: by 10.46.16.74 with SMTP id j71mr4266881lje.139.1518798936153; Fri, 16 Feb 2018 08:35:36 -0800 (PST) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 16 Feb 2018 17:35:26 +0100 Message-Id: <1518798927-8248-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518798927-8248-1-git-send-email-mw@semihalf.com> References: <1518798927-8248-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 1/2] Marvell/Armada7k8k: Add basic sample at reset library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, xswang@marvell.com, nadavh@marvell.com, neta@marvell.com, leif.lindholm@linaro.org, igall@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Igal Liberman The sample at reset library adds the following functionalities: - MvSARGetCpuFreq - Get the CPU frequency - MvSARGetDramFreq - Get the DRAM frequency - MvSARGetPcieClkDirection - Determine the PCIe clock direction for two types specified in CP110 HW block. It will be needed for proper configuration during the PCIE SerDes training. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Igal Liberman Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8kSARLib.c |= 166 ++++++++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8kSARLib.inf |= 54 +++++++ Silicon/Marvell/Include/Library/MvSARLib.h |= 57 +++++++ Silicon/Marvell/Marvell.dec |= 3 + 4 files changed, 280 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Arm= ada7k8kSARLib.c create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Arm= ada7k8kSARLib.inf create mode 100644 Silicon/Marvell/Include/Library/MvSARLib.h diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8k= SARLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8kSA= RLib.c new file mode 100644 index 0000000..27ada6f --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8kSARLib.c @@ -0,0 +1,166 @@ +/*************************************************************************= ******* +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must Retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ + +#include + +#include +#include +#include + +#define SAR_MAX_OPTIONS 16 + +#define CPU_CLOCK_ID 0 +#define DDR_CLOCK_ID 1 +#define RING_CLOCK_ID 2 + +#define MV_AP_SAR_BASE 0xf06f8200 +#define SAR_CLOCK_FREQ_MODE_MASK 0x1f + +#define MV_CP_SAR_BASE(_CpIndex) (0xf2000000 + (0x2000000 * _CpIndex) + 0= x400200) + +#define MAX_CP_COUNT 2 +#define MAX_PCIE_CLK_TYPE_COUNT 2 + +#define CP0_PCIE0_CLK_MASK 0x4 +#define CP0_PCIE1_CLK_MASK 0x8 +#define CP1_PCIE0_CLK_MASK 0x1 +#define CP1_PCIE1_CLK_MASK 0x2 +#define CP0_PCIE0_CLK_OFFSET 2 +#define CP0_PCIE1_CLK_OFFSET 3 +#define CP1_PCIE0_CLK_OFFSET 0 +#define CP1_PCIE1_CLK_OFFSET 1 + +typedef enum { + CPU_2000_DDR_1200_RCLK_1200 =3D 0x0, + CPU_2000_DDR_1050_RCLK_1050 =3D 0x1, + CPU_1600_DDR_800_RCLK_800 =3D 0x4, + CPU_1800_DDR_1200_RCLK_1200 =3D 0x6, + CPU_1800_DDR_1050_RCLK_1050 =3D 0x7, + CPU_1600_DDR_1050_RCLK_1050 =3D 0x0d, + CPU_1000_DDR_650_RCLK_650 =3D 0x13, + CPU_1300_DDR_800_RCLK_800 =3D 0x14, + CPU_1300_DDR_650_RCLK_650 =3D 0x17, + CPU_1200_DDR_800_RCLK_800 =3D 0x19, + CPU_1400_DDR_800_RCLK_800 =3D 0x1a, + CPU_600_DDR_800_RCLK_800 =3D 0x1b, + CPU_800_DDR_800_RCLK_800 =3D 0x1c, + CPU_1000_DDR_800_RCLK_800 =3D 0x1d, +} ClockingOptions; + +static const UINT32 PllFreqTbl[SAR_MAX_OPTIONS][4] =3D { + /* CPU DDR Ring [MHz] */ + {2000, 1200, 1200, CPU_2000_DDR_1200_RCLK_1200}, + {2000, 1050, 1050, CPU_2000_DDR_1050_RCLK_1050}, + {1800, 1200, 1200, CPU_1800_DDR_1200_RCLK_1200}, + {1800, 1050, 1050, CPU_1800_DDR_1050_RCLK_1050}, + {1600, 1050, 1050, CPU_1600_DDR_1050_RCLK_1050}, + {1300, 800 , 800 , CPU_1300_DDR_800_RCLK_800}, + {1300, 650 , 650 , CPU_1300_DDR_650_RCLK_650}, + {1600, 800 , 800 , CPU_1600_DDR_800_RCLK_800}, + {1000, 650 , 650 , CPU_1000_DDR_650_RCLK_650}, + {1200, 800 , 800 , CPU_1200_DDR_800_RCLK_800}, + {1400, 800 , 800 , CPU_1400_DDR_800_RCLK_800}, + {600 , 800 , 800 , CPU_600_DDR_800_RCLK_800}, + {800 , 800 , 800 , CPU_800_DDR_800_RCLK_800}, + {1000, 800 , 800 , CPU_1000_DDR_800_RCLK_800} +}; + +static const UINT32 PcieClkMask[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] =3D= { + {CP0_PCIE0_CLK_MASK, CP0_PCIE1_CLK_MASK}, + {CP1_PCIE0_CLK_MASK, CP1_PCIE1_CLK_MASK} +}; + +static const UINT32 PcieClkOffset[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = =3D { + {CP0_PCIE0_CLK_OFFSET, CP0_PCIE1_CLK_OFFSET}, + {CP1_PCIE0_CLK_OFFSET, CP1_PCIE1_CLK_OFFSET} +}; + +UINT32 +EFIAPI +MvSARGetCpuFreq ( + VOID + ) +{ + UINT32 ClkVal; + UINT32 Index; + + ClkVal =3D MmioAnd32 (MV_AP_SAR_BASE, SAR_CLOCK_FREQ_MODE_MASK); + + for (Index =3D 0; Index < SAR_MAX_OPTIONS; Index++) { + if (PllFreqTbl[Index][3] =3D=3D ClkVal) { + break; + } + } + + return PllFreqTbl[Index][CPU_CLOCK_ID]; +} + +UINT32 +EFIAPI +MvSARGetDramFreq ( + VOID + ) +{ + UINT32 ClkVal; + UINT32 Index; + + ClkVal =3D MmioAnd32 (MV_AP_SAR_BASE, SAR_CLOCK_FREQ_MODE_MASK); + + for (Index =3D 0; Index < SAR_MAX_OPTIONS; Index++) { + if (PllFreqTbl[Index][3] =3D=3D ClkVal) { + break; + } + } + + return PllFreqTbl[Index][DDR_CLOCK_ID]; +} + +UINT32 +EFIAPI +MvSARGetPcieClkDirection ( + IN UINT32 CpIndex, + IN UINT32 PcieIndex + ) +{ + UINT32 ClkDir; + + ASSERT (CpIndex < MAX_CP_COUNT); + ASSERT (PcieIndex < MAX_PCIE_CLK_TYPE_COUNT); + + ClkDir =3D MmioAnd32 (MV_CP_SAR_BASE (CpIndex), + PcieClkMask[CpIndex][PcieIndex] >> + PcieClkOffset[CpIndex][PcieIndex]); + + return ClkDir; +} diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8k= SARLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8k= SARLib.inf new file mode 100644 index 0000000..32b3fec --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8kSARLib.= inf @@ -0,0 +1,54 @@ +# Copyright (C) 2018 Marvell International Ltd. +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute= and/or +# modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without modif= ication, +# are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS = IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IM= PLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIA= BLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL D= AMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVI= CES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF= THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D Armada7k8kSARLib + FILE_GUID =3D 03e022c7-9bd7-4608-aa21-379deaac2430 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MvSARLib + +[Sources] + Armada7k8kSARLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib + +[Depex] + TRUE diff --git a/Silicon/Marvell/Include/Library/MvSARLib.h b/Silicon/Marvell/I= nclude/Library/MvSARLib.h new file mode 100644 index 0000000..1985a84 --- /dev/null +++ b/Silicon/Marvell/Include/Library/MvSARLib.h @@ -0,0 +1,57 @@ +/*************************************************************************= ******* +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must Retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ + +#ifndef __MV_SAR_LIB_H__ +#define __MV_SAR_LIB_H__ + +UINT32 +EFIAPI +MvSARGetCpuFreq ( + VOID + ); + +UINT32 +EFIAPI +MvSARGetDramFreq ( + VOID + ); + +UINT32 +EFIAPI +MvSARGetPcieClkDirection ( + IN UINT32 CpIndex, + IN UINT32 PcieIndex + ); + +#endif /* __MV_SAR_LIB_H__ */ diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 2eb6238..b188882 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -59,6 +59,9 @@ gMarvellFvbDxeGuid =3D { 0x42903750, 0x7e61, 0x4aaf, { 0x83, 0x29, 0xbf,= 0x42, 0x36, 0x4e, 0x24, 0x85 } } gMarvellSpiFlashDxeGuid =3D { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, = 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } } =20 +[LibraryClasses] + MvSARLib|Include/Library/MvSARLib.h + [Protocols] # installed as a protocol by PlatInitDxe to force ordering between DXE d= rivers # that depend on the lowlevel platform initialization having been comple= ted --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel