From nobody Mon Dec 23 09:56:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518798946077536.9806905117723; Fri, 16 Feb 2018 08:35:46 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4E6AF21CF1D1F; Fri, 16 Feb 2018 08:29:48 -0800 (PST) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CD571223230FD for ; Fri, 16 Feb 2018 08:29:45 -0800 (PST) Received: by mail-lf0-x242.google.com with SMTP id f136so4811192lff.8 for ; Fri, 16 Feb 2018 08:35:39 -0800 (PST) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p83sm3775112lfg.41.2018.02.16.08.35.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Feb 2018 08:35:36 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cdzh3geiF0s/VbLSq9C2yXWbzdOIphx++Wiw77h5YmM=; b=fgg7xnIFpN0TQ2rXIQ21zdRV2Rj1yye6BNgM4Aej7wIn5inb3bNYxOHMo84NjVaahA T44XHfi1w7xnfyxLpwMmBPvyEEhovCqdXD82SaJ+i6JjyrVkErROU4a1kIpphUdBLLR9 Xc2HaJDmOzfXBy0j35CoUZ61vJiImJP7hh8K/bM7XzAkqztjpkewOMxh10tb+z1BQydT mX7i+oysuX7zNb1y25B+3vDhFx3omllgLw6me1qbrNprxq7cdDb425JyYiNOzlwloIJN s4HTYJ075ou/MvoYeCnHtuU0b3yFnAAlFd7eU7Xlydj1NFNZtKF3uxjXjv3X6wicKOKC P4+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cdzh3geiF0s/VbLSq9C2yXWbzdOIphx++Wiw77h5YmM=; b=j6unRQrye2zzrxuE+6hsaSXUJDSw0bD5WxjKPL+t2sPZsXegRqazr5/LEHXN4UHIv3 RkeEJ6b4TJoiH+wJ419cOMUWl8CqkB917vHxlwkj3CHWGHdNri54KjcOsEUM6eWHhZPx EmIvurl7MoIbLLRs36uffYDKJ7dl+LNLiQrp3gOCJDbYGzwYlju1u3ynddLaqsOwTkHr Acgej92ZQHmywg6ZHwiT3H6e09g71vUTqOxob/o4yF77DoD1IOIRdxX56RBi0cZwiyjV utU2irBbDw+xsXEyLjcl4inSIDu5DY/mQ/qLqaqWjDNpvsh3aMr5B+qv5iMHbY3FviN+ g1Kw== X-Gm-Message-State: APf1xPAX025ziLGBoy70JkREv2DhF5HfedHvcCMbFaEvja8QeMw1li21 YOS43rwQ8pxx3Vgj+ILeoMg8bNQXFzY= X-Google-Smtp-Source: AH8x227fpVRnxEGPVigbmOhefds5qLZSXbPZ2PbbFNXTNZuW5O3H2gcoFq+AzdaSFxvMbEAkpZKMhQ== X-Received: by 10.46.64.91 with SMTP id n88mr2087675lja.92.1518798937728; Fri, 16 Feb 2018 08:35:37 -0800 (PST) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 16 Feb 2018 17:35:27 +0100 Message-Id: <1518798927-8248-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518798927-8248-1-git-send-email-mw@semihalf.com> References: <1518798927-8248-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 2/2] Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, xswang@marvell.com, nadavh@marvell.com, neta@marvell.com, leif.lindholm@linaro.org, igall@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Evan Wang PCIE clock direction (input/output) has implications on comphy settings. There are 2 PCIe clocks in CP110: - Ref clock 0 for lanes 1,2 and 3 - Ref clock 1 for lanes 4 and 5 A proper handling of above had to be added, using newly introduced sample at reset library class for Marvell SoCs. Other than that, update HPIPE settings and the reset sequence, which differ from one used in x1 link. This patch fixes PCIE x4 and x2 configuration, which helps to overcome link establishing issue for multi-lane end points. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Evan Wang Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 + Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 216 +++++++++++++++----- Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 1 + Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 20 ++ Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 + 5 files changed, 187 insertions(+), 52 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index ef70b52..bb2ec6c 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -35,6 +35,7 @@ ArmPlatformLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k= 8kLib.inf ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf MppLib|Silicon/Marvell/Library/MppLib/MppLib.inf + MvSARLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8kS= ARLib.inf NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf UtmiPhyLib|Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf =20 diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyCp110.c index 40a7b99..25b8b7c 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -34,6 +34,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "ComPhyLib.h" #include +#include =20 #define SD_LANE_ADDR_WIDTH 0x1000 #define HPIPE_ADDR_OFFSET 0x800 @@ -42,6 +43,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFS= ET) #define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane) =20 +#define CP110_PCIE_REF_CLK_TYPE0 0 +#define CP110_PCIE_REF_CLK_TYPE12 1 + DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; =20 /* @@ -99,11 +103,26 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] =3D { STATIC VOID ComPhyPcieRFUConfiguration ( + IN UINT32 Lane, + IN UINT32 PcieWidth, IN EFI_PHYSICAL_ADDRESS ComPhyAddr ) { UINT32 Mask, Data; =20 + /* Enable PCIe by4 and by2 */ + if (Lane =3D=3D 0) { + if (PcieWidth =3D=3D 4) { + RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1, + 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET, + COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); + } else if (PcieWidth =3D=3D 2) { + RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1, + 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET, + COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); + } + } + /* RFU configurations - hard reset ComPhy */ Mask =3D COMMON_PHY_CFG1_PWR_UP_MASK; Data =3D 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; @@ -132,11 +151,14 @@ ComPhyPcieRFUConfiguration ( STATIC VOID ComPhyPciePhyConfiguration ( + IN UINT32 Lane, + IN UINT32 PcieWidth, + IN UINT32 PcieClk, IN EFI_PHYSICAL_ADDRESS ComPhyAddr, IN EFI_PHYSICAL_ADDRESS HpipeAddr ) { - UINT32 Mask, Data, PcieClk =3D 0; + UINT32 Mask, Data; =20 /* Set PIPE soft reset */ Mask =3D HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; @@ -156,13 +178,31 @@ ComPhyPciePhyConfiguration ( RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask); =20 /* Set PLL ready delay for 0x2 */ - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); + Data =3D 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; + Mask =3D HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; + if (PcieWidth !=3D 1) { + Data |=3D 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET | + 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; + Mask |=3D HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK | + HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; + } + RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask); =20 /* Set PIPE mode interface to PCIe3 - 0x1 */ - RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, - 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET, HPIPE_CLK_SRC_HI_MODE_PIPE_M= ASK); + Data =3D 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; + Mask =3D HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; + if (PcieWidth !=3D 1) { + Mask |=3D HPIPE_CLK_SRC_HI_LANE_STRT_MASK | + HPIPE_CLK_SRC_HI_LANE_MASTER_MASK | + HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; + if (Lane =3D=3D 0) { + Data |=3D 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET | + 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; + } else if (Lane =3D=3D (PcieWidth - 1)) { + Data |=3D 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; + } + } + RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask); =20 /* Config update polarity equalization */ RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG, @@ -172,19 +212,21 @@ ComPhyPciePhyConfiguration ( RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG, 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK); =20 - /* Enable PIN clock 100M_125M */ - Mask =3D HPIPE_MISC_CLK100M_125M_MASK; - Data =3D 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; - /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock = */ - Mask |=3D HPIPE_MISC_TXDCLK_2X_MASK; - Data |=3D 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; + Mask =3D HPIPE_MISC_TXDCLK_2X_MASK; + Data =3D 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; =20 /* Enable 500MHz Clock */ Mask |=3D HPIPE_MISC_CLK500_EN_MASK; Data |=3D 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; =20 if (PcieClk) { + /* + * Enable PIN clock 100M_125M + * Only if clock is output, configure the clock-source mux + */ + Mask |=3D HPIPE_MISC_CLK100M_125M_MASK; + Data |=3D 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; /* Set reference clock comes from group 1 */ Mask |=3D HPIPE_MISC_REFCLK_SEL_MASK; Data |=3D 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; @@ -214,6 +256,13 @@ ComPhyPciePhyConfiguration ( Data |=3D 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask); =20 + /* Ref clock alignment */ + if (PcieWidth !=3D 1) { + RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG, + 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET, + HPIPE_LANE_ALIGN_OFF_MASK); + } + /* * Set the amount of time spent in the LoZ state - set * for 0x7 only if the PCIe clock is output @@ -404,37 +453,86 @@ ComPhyPcieSetAnalogParameters ( } =20 STATIC -VOID -ComPhyPciePhyPowerUp ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr -) -{ - /* Release from PIPE soft reset */ - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); - - /* Wait 15ms - for ComPhy calibration done */ - MicroSecondDelay (15000); - MemoryFence (); -} - -STATIC EFI_STATUS -ComPhyPcieCheckPll ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr +ComPhyPciePhyPowerUp ( + IN UINT32 Lane, + IN UINT32 PcieWidth, + IN EFI_PHYSICAL_ADDRESS ComPhyBase, + IN EFI_PHYSICAL_ADDRESS HpipeBase ) { EFI_STATUS Status =3D EFI_SUCCESS; - UINT32 Data; + UINT8 StartLane, EndLane, Loop; + UINT32 Data, UsecTimout; =20 - /* Read Lane status */ - Data =3D MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG); - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) =3D=3D 0) { - DEBUG((DEBUG_INFO, "ComPhy: Read from reg =3D %p - value =3D 0x%x\n", - HpipeAddr + HPIPE_LANE_STATUS0_REG, Data)); - DEBUG((DEBUG_INFO, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n")); - Status =3D EFI_D_ERROR; + /* + * For PCIe by4 or by2 - release from reset only after finish to + * configure all lanes + */ + if ((PcieWidth =3D=3D 1) || (Lane =3D=3D (PcieWidth - 1))) { + if (PcieWidth !=3D 1) { + /* Allows writing to all lanes in one write */ + RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1, + 0x0 << COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); + StartLane =3D 0; + EndLane =3D PcieWidth; + + /* + * Release from PIPE soft reset + * for PCIe by4 or by2 - release from soft reset + * all lanes - can't use read modify write + */ + RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG, + HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 | HPIPE_RST_CLK_CTRL_MODE_RE= FDIV_4, + HPIPE_RST_CLK_CTRL_CLR_ALL_MASK); + } else { + StartLane =3D Lane; + EndLane =3D Lane + 1; + + /* + * Release from PIPE soft reset + * for PCIe by4 or by2 - release from soft reset + * all lanes + */ + RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG, + 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, + HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); + } + + if (PcieWidth !=3D 1) { + /* Disable writing to all lanes with one write */ + RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1, + 0x3210 << COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); + } + MemoryFence (); + + /* Read lane status */ + for (Loop =3D StartLane; Loop < EndLane; Loop++) { + Data =3D 0; + UsecTimout =3D 15000; + + do { + MicroSecondDelay (1); + Data =3D MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STA= TUS0_REG); + Data &=3D HPIPE_LANE_STATUS0_PCLK_EN_MASK; + } while (Data =3D=3D 0 && --UsecTimout > 0); + + if (UsecTimout =3D=3D 0 && Data =3D=3D 0) { + DEBUG ((DEBUG_ERROR, + "%a: Read from lane%d, reg =3D %p - value =3D 0x%x\n", + __FUNCTION__, + Loop, + HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG, + Data)); + DEBUG ((DEBUG_ERROR, + "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n", + __FUNCTION__)); + Status =3D EFI_D_ERROR; + break; + } + } } =20 return Status; @@ -443,8 +541,9 @@ ComPhyPcieCheckPll ( STATIC EFI_STATUS ComPhyPciePowerUp ( + IN UINT8 ChipId, IN UINT32 Lane, - IN UINT32 PcieBy4, + IN UINT32 PcieWidth, IN EFI_PHYSICAL_ADDRESS HpipeBase, IN EFI_PHYSICAL_ADDRESS ComPhyBase ) @@ -452,26 +551,32 @@ ComPhyPciePowerUp ( EFI_STATUS Status =3D EFI_SUCCESS; EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); + UINT32 PcieClk; + + /* Lane4 and 5 only for PCIe port 1 and 2 */ + if (Lane =3D=3D 4 || Lane =3D=3D 5) { + PcieClk =3D MvSARGetPcieClkDirection (ChipId, CP110_PCIE_REF_CLK_TYPE1= 2); + } else { + PcieClk =3D MvSARGetPcieClkDirection (ChipId, CP110_PCIE_REF_CLK_TYPE0= ); + } + + DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__, ChipId,= PcieClk)); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPh= y\n")); =20 - ComPhyPcieRFUConfiguration (ComPhyAddr); + ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n")); =20 - ComPhyPciePhyConfiguration (ComPhyAddr, HpipeAddr); + ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr, HpipeA= ddr); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n")); =20 ComPhyPcieSetAnalogParameters (HpipeAddr); =20 - DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); + DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n", __FUNC= TION__)); =20 - ComPhyPciePhyPowerUp (HpipeAddr); - - DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); - - Status =3D ComPhyPcieCheckPll (HpipeAddr); + Status =3D ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase, HpipeBase); =20 return Status; } @@ -1780,28 +1885,35 @@ ComPhyCp110Init ( COMPHY_MAP *PtrComPhyMap, *SerdesMap; EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr; UINT32 ComPhyMaxCount, Lane; - UINT32 PcieBy4 =3D 1; // Indicating if first 4 lanes set to PCIE + UINT32 PcieWidth =3D 0; + UINT8 ChipId; =20 ComPhyMaxCount =3D PtrChipCfg->LanesCount; ComPhyBaseAddr =3D PtrChipCfg->ComPhyBaseAddr; HpipeBaseAddr =3D PtrChipCfg->Hpipe3BaseAddr; SerdesMap =3D PtrChipCfg->MapData; + ChipId =3D PtrChipCfg->ChipId; =20 /* Config Comphy mux configuration */ ComPhyMuxCp110(PtrChipCfg, SerdesMap); =20 /* Check if the first 4 Lanes configured as By-4 */ for (Lane =3D 0, PtrComPhyMap =3D SerdesMap; Lane < 4; Lane++, PtrComPhy= Map++) { - if (PtrComPhyMap->Type !=3D COMPHY_TYPE_PCIE0) { - PcieBy4 =3D 0; + if (PtrComPhyMap->Type !=3D COMPHY_TYPE_PCIE0) break; - } + PcieWidth++; } =20 for (Lane =3D 0, PtrComPhyMap =3D SerdesMap; Lane < ComPhyMaxCount; Lane++, PtrComPhyMap++) { DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane)); DEBUG((DEBUG_INFO, "ComPhy: Serdes Type =3D 0x%x\n", PtrComPhyMap->Typ= e)); + + if (Lane >=3D 4) { + /* PCIe lanes above the first 4 lanes, can be only by1 */ + PcieWidth =3D 1; + } + switch (PtrComPhyMap->Type) { case COMPHY_TYPE_UNCONNECTED: continue; @@ -1810,7 +1922,7 @@ ComPhyCp110Init ( case COMPHY_TYPE_PCIE1: case COMPHY_TYPE_PCIE2: case COMPHY_TYPE_PCIE3: - Status =3D ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBas= eAddr); + Status =3D ComPhyPciePowerUp (ChipId, Lane, PcieWidth, HpipeBaseAddr= , ComPhyBaseAddr); break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.c index bf21dca..b03bc35 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -192,6 +192,7 @@ InitComPhyConfig ( ChipConfig->Hpipe3BaseAddr =3D Desc->ComPhyHpipe3BaseAddresses[Id]; ChipConfig->LanesCount =3D Desc->ComPhyLaneCount[Id]; ChipConfig->MuxBitCount =3D Desc->ComPhyMuxBitCount[Id]; + ChipConfig->ChipId =3D Id; =20 /* * Below macro contains variable name concatenation (used to form PCD's = name). diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.h index 5899a4a..710ec80 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -479,16 +479,29 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_F= OM_PRESET_VECTOR_OFFSET) =20 #define HPIPE_RST_CLK_CTRL_REG 0x704 +#define HPIPE_RST_CLK_CTRL_CLR_ALL_MASK 0xffffffff #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CT= RL_PIPE_RST_OFFSET) #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CT= RL_FIXED_PCLK_OFFSET) +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 (0x1 << HPIPE_RST_CLK_CT= RL_FIXED_PCLK_OFFSET) +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_16 (0x0 << HPIPE_RST_CLK_CT= RL_FIXED_PCLK_OFFSET) #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CT= RL_PIPE_WIDTH_OFFSET) +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET 4 +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_MASK (0x3 << HPIPE_RST_CLK_CT= RL_MODE_REFDIV_OFFSET) +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_1 (0x0 << HPIPE_RST_CLK_CT= RL_MODE_REFDIV_OFFSET) +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_2 (0x1 << HPIPE_RST_CLK_CT= RL_MODE_REFDIV_OFFSET) +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_4 (0x2 << HPIPE_RST_CLK_CT= RL_MODE_REFDIV_OFFSET) +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_8 (0x3 << HPIPE_RST_CLK_CT= RL_MODE_REFDIV_OFFSET) #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CT= RL_CORE_FREQ_SEL_OFFSET) =20 #define HPIPE_CLK_SRC_LO_REG 0x70c +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO= _BUNDLE_PERIOD_SEL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO= _BUNDLE_PERIOD_SCALE_OFFSET) #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO= _PLL_RDY_DL_OFFSET) =20 @@ -528,6 +541,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define COMMON_SELECTOR_PIPE_OFFSET 0x144 =20 #define COMMON_PHY_SD_CTRL1 0x148 +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0 +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CT= RL1_PCIE_X4_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CT= RL1_PCIE_X2_EN_OFFSET) #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26 #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CT= RL1_RXAUI1_OFFSET) #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27 @@ -594,6 +613,7 @@ struct _CHIP_COMPHY_CONFIG { COMPHY_CHIP_INIT Init; UINT32 LanesCount; UINT32 MuxBitCount; + UINT8 ChipId; }; =20 VOID diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyLib.inf index a1584b4..f00180c 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -49,6 +49,7 @@ ArmLib DebugLib MemoryAllocationLib + MvSARLib PcdLib IoLib =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel