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From: Heyi Guo <heyi.guo@linaro.org>
To: edk2-devel@lists.01.org
Date: Thu,  1 Mar 2018 14:57:19 +0800
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Subject: [edk2] [PATCH v5 1/6] CorebootPayloadPkg/PciHostBridgeLib: Init PCI
 aperture to 0
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Use ZeroMem to initialize all fields in temporary
PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but
helpful for future extension: when we add new fields to
PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can
safely be zero, this code will not suffer from an additional change.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 5 +++=
++
 1 file changed, 5 insertions(+)

diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSuppo=
rt.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index 6d94ff72c956..c61609b79cce 100644
--- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -319,6 +319,11 @@ ScanForRootBridges (
=20
   *NumberOfRootBridges =3D 0;
   RootBridges =3D NULL;
+  ZeroMem (&Io, sizeof (Io));
+  ZeroMem (&Mem, sizeof (Mem));
+  ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
+  ZeroMem (&PMem, sizeof (PMem));
+  ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
=20
   //
   // After scanning all the PCI devices on the PCI root bridge's primary b=
us,
--=20
2.7.4

_______________________________________________
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https://lists.01.org/mailman/listinfo/edk2-devel
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From: Heyi Guo <heyi.guo@linaro.org>
To: edk2-devel@lists.01.org
Date: Thu,  1 Mar 2018 14:57:20 +0800
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Subject: [edk2] [PATCH v5 2/6] OvmfPkg/PciHostBridgeLib: Init PCI aperture
 to 0
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Cc: Ruiyu Ni <ruiyu.ni@intel.com>, Ard Biesheuvel <ard.biesheuvel@linaro.org>,
 Jordan Justen <jordan.l.justen@intel.com>, Heyi Guo <heyi.guo@linaro.org>,
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Use ZeroMem to initialize all fields in temporary
PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but
is helpful for future extension: when we add new fields to
PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can
safely be zero, this code will not suffer from an additional
change.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Julien Grall <julien.grall@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 4 ++++
 OvmfPkg/Library/PciHostBridgeLib/XenSupport.c       | 5 +++++
 2 files changed, 9 insertions(+)

diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/OvmfPkg/=
Library/PciHostBridgeLib/PciHostBridgeLib.c
index ff837035caff..4a650a4c6df9 100644
--- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -217,6 +217,10 @@ PciHostBridgeGetRootBridges (
   PCI_ROOT_BRIDGE_APERTURE Mem;
   PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
=20
+  ZeroMem (&Io, sizeof (Io));
+  ZeroMem (&Mem, sizeof (Mem));
+  ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
+
   if (PcdGetBool (PcdPciDisableBusEnumeration)) {
     return ScanForRootBridges (Count);
   }
diff --git a/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c b/OvmfPkg/Librar=
y/PciHostBridgeLib/XenSupport.c
index 31c63ae19e0a..aaf101dfcb0e 100644
--- a/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c
+++ b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c
@@ -193,6 +193,11 @@ ScanForRootBridges (
=20
   *NumberOfRootBridges =3D 0;
   RootBridges =3D NULL;
+  ZeroMem (&Io, sizeof (Io));
+  ZeroMem (&Mem, sizeof (Mem));
+  ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
+  ZeroMem (&PMem, sizeof (PMem));
+  ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
=20
   //
   // After scanning all the PCI devices on the PCI root bridge's primary b=
us,
--=20
2.7.4

_______________________________________________
edk2-devel mailing list
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https://lists.01.org/mailman/listinfo/edk2-devel
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From: Heyi Guo <heyi.guo@linaro.org>
To: edk2-devel@lists.01.org
Date: Thu,  1 Mar 2018 14:57:21 +0800
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Subject: [edk2] [PATCH v5 3/6] MdeModulePkg/PciHostBridgeLib.h: add address
 Translation
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Add Translation field to PCI_ROOT_BRIDGE_APERTURE. Translation is used
to represent the difference between device address and host address,
if they are not the same on some platforms.

In UEFI 2.7, "Address Translation Offset" is "Offset to apply to the
Starting address to convert it to a PCI address".  This means:

  Translation =3D device address - host address

So we also use the above calculation for this Translation field to
keep consistent.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 MdeModulePkg/Include/Library/PciHostBridgeLib.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/MdeModulePkg/Include/Library/PciHostBridgeLib.h b/MdeModulePkg=
/Include/Library/PciHostBridgeLib.h
index d42e9ecdd763..18963a0d3821 100644
--- a/MdeModulePkg/Include/Library/PciHostBridgeLib.h
+++ b/MdeModulePkg/Include/Library/PciHostBridgeLib.h
@@ -20,8 +20,27 @@
 // (Base > Limit) indicates an aperture is not available.
 //
 typedef struct {
+  //
+  // Base and Limit are the device address instead of host address when
+  // Translation is not zero
+  //
   UINT64 Base;
   UINT64 Limit;
+  //
+  // According to UEFI 2.7, Device Address =3D Host Address + Translation,
+  // so Translation =3D Device Address - Host Address.
+  // On platforms where Translation is not zero, the subtraction is probab=
ly to
+  // be performed with UINT64 wrap-around semantics, for we may translate =
an
+  // above-4G host address into a below-4G device address for legacy PCIe =
device
+  // compatibility.
+  //
+  // NOTE: The alignment of Translation is required to be larger than any =
BAR
+  // alignment in the same root bridge, so that the same alignment can be
+  // applied to both device address and host address, which simplifies the
+  // situation and makes the current resource allocation code in generic P=
CI
+  // host bridge driver still work.
+  //
+  UINT64 Translation;
 } PCI_ROOT_BRIDGE_APERTURE;
=20
 typedef struct {
--=20
2.7.4

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From: Heyi Guo <heyi.guo@linaro.org>
To: edk2-devel@lists.01.org
Date: Thu,  1 Mar 2018 14:57:22 +0800
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Subject: [edk2] [PATCH v5 4/6] MdeModulePkg/PciHostBridgeDxe: Add support
 for address translation
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Cc: Ruiyu Ni <ruiyu.ni@intel.com>, Eric Dong <eric.dong@intel.com>,
 Ard Biesheuvel <ard.biesheuvel@linaro.org>, Heyi Guo <heyi.guo@linaro.org>,
 Michael D Kinney <michael.d.kinney@intel.com>,
 Laszlo Ersek <lersek@redhat.com>, Star Zeng <star.zeng@intel.com>
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PCI address translation is necessary for some non-x86 platforms. On
such platforms, address value (denoted as "device address" or "address
in PCI view") set to PCI BAR registers in configuration space might be
different from the address which is used by CPU to access the
registers in memory BAR or IO BAR spaces (denoted as "host address" or
"address in CPU view"). The difference between the two addresses is
called "Address Translation Offset" or simply "translation", and can
be represented by "Address Translation Offset" in ACPI QWORD Address
Space Descriptor (Offset 0x1E). However UEFI and ACPI differs on the
definitions of QWORD Address Space Descriptor, and we will follow UEFI
definition on UEFI protocols, such as PCI root bridge IO protocol and
PCI IO protocol. In UEFI 2.7, "Address Translation Offset" is "Offset
to apply to the Starting address to convert it to a PCI address". This
means:

1. Translation =3D device address - host address.

2. PciRootBridgeIo->Configuration should return CPU view address, as
well as PciIo->GetBarAttributes.

Summary of addresses used in protocol interfaces and internal
implementations:

1. *Only* the following protocol interfaces assume Address is Device
   Address:
(1). PciHostBridgeResourceAllocation.GetProposedResources()
     Otherwise PCI bus driver cannot set correct address into PCI
     BARs.
(2). PciRootBridgeIo.Mem.Read() and PciRootBridgeIo.Mem.Write()
(3). PciRootBridgeIo.CopyMem()
UEFI and PI spec have clear statements for all other protocol
interfaces about the address type.

2. Library interfaces and internal implementation:
(1). Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
     It is easy to check whether the address is below 4G or above 4G.
(2). Addresses in PCI_ROOT_BRIDGE_INSTANCE.ResAllocNode are host
     address, for they are allocated from GCD.
(3). Address passed to PciHostBridgeResourceConflict is host address,
     for it comes from PCI_ROOT_BRIDGE_INSTANCE.ResAllocNode.

RESTRICTION: to simplify the situation, we require the alignment of
Translation must be larger than any BAR alignment in the same root
bridge, so that resource allocation alignment can be applied to both
device address and host address.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---

Notes:
    v5:
    - Add check for the alignment of Translation against the BAR alignment
      [Ray]
    - Keep coding style of comments consistent with the context [Ray]
    - Comment change for Base in PCI_RES_NODE [Ray]
    - Add macros of TO_HOST_ADDRESS and TO_DEVICE_ADDRESS for address type
      conversion (After that we can also simply the comments about the
      calculation [Ray]
    - Add check for bus translation offset in CreateRootBridge(), making
      sure it is zero, and unify code logic for all types of resource
      after that [Ray]
    - Use GetTranslationByResourceType() to simplify the code in
      RootBridgeIoConfiguration() (also fix a bug in previous patch
      version of missing a break after case TypePMem64) [Ray]
    - Commit message refinement [Ray]
   =20
    v4:
    - Add ASSERT (FALSE) to default branch in GetTranslationByResourceType
      [Laszlo]
    - Fix bug when passing BaseAddress to gDS->AllocateIoSpace and
      gDS->AllocateMemorySpace [Laszlo]
    - Add comment for applying alignment to both device address and host
      address, and add NOTE for the alignment requirement of Translation,
      as well as in commit message [Laszlo][Ray]
    - Improve indention for the code in CreateRootBridge [Laszlo]
    - Improve comment for Translation in PCI_ROOT_BRIDGE_APERTURE
      definition [Laszlo]
    - Ignore translation of bus in CreateRootBridge
   =20
    v4:
    - Add ASSERT (FALSE) to default branch in GetTranslationByResourceType
      [Laszlo]
    - Fix bug when passing BaseAddress to gDS->AllocateIoSpace and
      gDS->AllocateMemorySpace [Laszlo]
    - Add comment for applying alignment to both device address and host
      address, and add NOTE for the alignment requirement of Translation,
      as well as in commit message [Laszlo][Ray]
    - Improve indention for the code in CreateRootBridge [Laszlo]
    - Improve comment for Translation in PCI_ROOT_BRIDGE_APERTURE
      definition [Laszlo]
    - Ignore translation of bus in CreateRootBridge

 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h   |  21 ++++
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h |   3 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c   | 129 ++++++++++++=
+++++---
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 118 ++++++++++++=
++++--
 4 files changed, 245 insertions(+), 26 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h b/MdeMod=
ulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h
index 9a8ca21f4819..c2791ea5c2a4 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h
@@ -38,6 +38,13 @@ typedef struct {
 #define PCI_HOST_BRIDGE_FROM_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResA=
lloc, PCI_HOST_BRIDGE_SIGNATURE)
=20
 //
+// Macros to translate device address to host address and vice versa. Acco=
rding
+// to UEFI 2.7, device address =3D host address + translation offset.
+//
+#define TO_HOST_ADDRESS(DeviceAddress,TranslationOffset) ((DeviceAddress) =
- (TranslationOffset))
+#define TO_DEVICE_ADDRESS(HostAddress,TranslationOffset) ((HostAddress) + =
(TranslationOffset))
+
+//
 // Driver Entry Point
 //
 /**
@@ -247,6 +254,20 @@ ResourceConflict (
   IN  PCI_HOST_BRIDGE_INSTANCE *HostBridge
   );
=20
+/**
+  This routine gets translation offset from a root bridge instance by reso=
urce type.
+
+  @param RootBridge The Root Bridge Instance for the resources.
+  @param ResourceType The Resource Type of the translation offset.
+
+  @retval The Translation Offset of the specified resource.
+**/
+UINT64
+GetTranslationByResourceType (
+  IN  PCI_ROOT_BRIDGE_INSTANCE     *RootBridge,
+  IN  PCI_RESOURCE_TYPE            ResourceType
+  );
+
 extern EFI_METRONOME_ARCH_PROTOCOL *mMetronome;
 extern EFI_CPU_IO2_PROTOCOL        *mCpuIo;
 #endif
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h b/MdeM=
odulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h
index 8612c0c3251b..a6c3739db368 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h
@@ -38,6 +38,9 @@ typedef enum {
=20
 typedef struct {
   PCI_RESOURCE_TYPE Type;
+  //
+  // Base is a host address
+  //
   UINT64            Base;
   UINT64            Length;
   UINT64            Alignment;
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeMod=
ulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
index 1494848c3e8c..42ded2855c71 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
@@ -33,6 +33,39 @@ EFI_EVENT                   mIoMmuEvent;
 VOID                        *mIoMmuRegistration;
=20
 /**
+  This routine gets translation offset from a root bridge instance by reso=
urce type.
+
+  @param RootBridge The Root Bridge Instance for the resources.
+  @param ResourceType The Resource Type of the translation offset.
+
+  @retval The Translation Offset of the specified resource.
+**/
+UINT64
+GetTranslationByResourceType (
+  IN  PCI_ROOT_BRIDGE_INSTANCE     *RootBridge,
+  IN  PCI_RESOURCE_TYPE            ResourceType
+  )
+{
+  switch (ResourceType) {
+    case TypeIo:
+      return RootBridge->Io.Translation;
+    case TypeMem32:
+      return RootBridge->Mem.Translation;
+    case TypePMem32:
+      return RootBridge->PMem.Translation;
+    case TypeMem64:
+      return RootBridge->MemAbove4G.Translation;
+    case TypePMem64:
+      return RootBridge->PMemAbove4G.Translation;
+    case TypeBus:
+      return RootBridge->Bus.Translation;
+    default:
+      ASSERT (FALSE);
+      return 0;
+  }
+}
+
+/**
   Ensure the compatibility of an IO space descriptor with the IO aperture.
=20
   The IO space descriptor can come from the GCD IO space map, or it can
@@ -366,6 +399,7 @@ InitializePciHostBridge (
   UINTN                       MemApertureIndex;
   BOOLEAN                     ResourceAssigned;
   LIST_ENTRY                  *Link;
+  UINT64                      HostAddress;
=20
   RootBridges =3D PciHostBridgeGetRootBridges (&RootBridgeCount);
   if ((RootBridges =3D=3D NULL) || (RootBridgeCount =3D=3D 0)) {
@@ -411,8 +445,15 @@ InitializePciHostBridge (
     }
=20
     if (RootBridges[Index].Io.Base <=3D RootBridges[Index].Io.Limit) {
+      //
+      // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
+      // For GCD resource manipulation, we need to use host address.
+      //
+      HostAddress =3D TO_HOST_ADDRESS (RootBridges[Index].Io.Base,
+        RootBridges[Index].Io.Translation);
+
       Status =3D AddIoSpace (
-                 RootBridges[Index].Io.Base,
+                 HostAddress,
                  RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base =
+ 1
                  );
       ASSERT_EFI_ERROR (Status);
@@ -422,7 +463,7 @@ InitializePciHostBridge (
                         EfiGcdIoTypeIo,
                         0,
                         RootBridges[Index].Io.Limit - RootBridges[Index].I=
o.Base + 1,
-                        &RootBridges[Index].Io.Base,
+                        &HostAddress,
                         gImageHandle,
                         NULL
                         );
@@ -443,14 +484,20 @@ InitializePciHostBridge (
=20
     for (MemApertureIndex =3D 0; MemApertureIndex < ARRAY_SIZE (MemApertur=
es); MemApertureIndex++) {
       if (MemApertures[MemApertureIndex]->Base <=3D MemApertures[MemApertu=
reIndex]->Limit) {
+        //
+        // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
+        // For GCD resource manipulation, we need to use host address.
+        //
+        HostAddress =3D TO_HOST_ADDRESS (MemApertures[MemApertureIndex]->B=
ase,
+          MemApertures[MemApertureIndex]->Translation);
         Status =3D AddMemoryMappedIoSpace (
-                   MemApertures[MemApertureIndex]->Base,
+                   HostAddress,
                    MemApertures[MemApertureIndex]->Limit - MemApertures[Me=
mApertureIndex]->Base + 1,
                    EFI_MEMORY_UC
                    );
         ASSERT_EFI_ERROR (Status);
         Status =3D gDS->SetMemorySpaceAttributes (
-                        MemApertures[MemApertureIndex]->Base,
+                        HostAddress,
                         MemApertures[MemApertureIndex]->Limit - MemApertur=
es[MemApertureIndex]->Base + 1,
                         EFI_MEMORY_UC
                         );
@@ -463,7 +510,7 @@ InitializePciHostBridge (
                           EfiGcdMemoryTypeMemoryMappedIo,
                           0,
                           MemApertures[MemApertureIndex]->Limit - MemApert=
ures[MemApertureIndex]->Base + 1,
-                          &MemApertures[MemApertureIndex]->Base,
+                          &HostAddress,
                           gImageHandle,
                           NULL
                           );
@@ -654,6 +701,11 @@ AllocateResource (
   if (BaseAddress < Limit) {
     //
     // Have to make sure Aligment is handled since we are doing direct add=
ress allocation
+    // Strictly speaking, alignment requirement should be applied to device
+    // address instead of host address which is used in GCD manipulation b=
elow,
+    // but as we restrict the alignment of Translation to be larger than a=
ny BAR
+    // alignment in the root bridge, we can simplify the situation and con=
sider
+    // the same alignment requirement is also applied to host address.
     //
     BaseAddress =3D ALIGN_VALUE (BaseAddress, LShiftU64 (1, BitsOfAlignmen=
t));
=20
@@ -721,6 +773,7 @@ NotifyPhase (
   PCI_RESOURCE_TYPE                     Index2;
   BOOLEAN                               ResNodeHandled[TypeMax];
   UINT64                                MaxAlignment;
+  UINT64                                Translation;
=20
   HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This);
=20
@@ -822,14 +875,43 @@ NotifyPhase (
           BitsOfAlignment =3D LowBitSet64 (Alignment + 1);
           BaseAddress =3D MAX_UINT64;
=20
+          //
+          // RESTRICTION: To simplify the situation, we require the alignm=
ent of
+          // Translation must be larger than any BAR alignment in the same=
 root
+          // bridge, so that resource allocation alignment can be applied =
to
+          // both device address and host address.
+          //
+          Translation =3D GetTranslationByResourceType (RootBridge, Index);
+          if ((Translation & Alignment) !=3D 0) {
+            DEBUG ((DEBUG_ERROR, "[%a:%d] Translation %lx is not aligned t=
o %lx!\n",
+              __FUNCTION__, __LINE__, Translation, Alignment
+              ));
+            ASSERT (FALSE);
+            //
+            // This may be caused by too large alignment or too small
+            // Translation; pick the 1st possibility and return out of res=
ource,
+            // which can also go thru the same process for out of resource
+            // outside the loop.
+            //
+            ReturnStatus =3D EFI_OUT_OF_RESOURCES;
+            continue;
+          }
+
           switch (Index) {
           case TypeIo:
+            //
+            // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device addre=
ss.
+            // For AllocateResource is manipulating GCD resource, we need =
to use
+            // host address here.
+            //
             BaseAddress =3D AllocateResource (
                             FALSE,
                             RootBridge->ResAllocNode[Index].Length,
                             MIN (15, BitsOfAlignment),
-                            ALIGN_VALUE (RootBridge->Io.Base, Alignment + =
1),
-                            RootBridge->Io.Limit
+                            TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Io.B=
ase, Alignment + 1),
+                              RootBridge->Io.Translation),
+                            TO_HOST_ADDRESS (RootBridge->Io.Limit,
+                              RootBridge->Io.Translation)
                             );
             break;
=20
@@ -838,8 +920,10 @@ NotifyPhase (
                             TRUE,
                             RootBridge->ResAllocNode[Index].Length,
                             MIN (63, BitsOfAlignment),
-                            ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alig=
nment + 1),
-                            RootBridge->MemAbove4G.Limit
+                            TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->MemA=
bove4G.Base, Alignment + 1),
+                              RootBridge->MemAbove4G.Translation),
+                            TO_HOST_ADDRESS (RootBridge->MemAbove4G.Limit,
+                              RootBridge->MemAbove4G.Translation)
                             );
             if (BaseAddress !=3D MAX_UINT64) {
               break;
@@ -853,8 +937,10 @@ NotifyPhase (
                             TRUE,
                             RootBridge->ResAllocNode[Index].Length,
                             MIN (31, BitsOfAlignment),
-                            ALIGN_VALUE (RootBridge->Mem.Base, Alignment +=
 1),
-                            RootBridge->Mem.Limit
+                            TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Mem.=
Base, Alignment + 1),
+                              RootBridge->Mem.Translation),
+                            TO_HOST_ADDRESS (RootBridge->Mem.Limit,
+                              RootBridge->Mem.Translation)
                             );
             break;
=20
@@ -863,8 +949,10 @@ NotifyPhase (
                             TRUE,
                             RootBridge->ResAllocNode[Index].Length,
                             MIN (63, BitsOfAlignment),
-                            ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Ali=
gnment + 1),
-                            RootBridge->PMemAbove4G.Limit
+                            TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMem=
Above4G.Base, Alignment + 1),
+                              RootBridge->PMemAbove4G.Translation),
+                            TO_HOST_ADDRESS (RootBridge->PMemAbove4G.Limit,
+                              RootBridge->PMemAbove4G.Translation)
                             );
             if (BaseAddress !=3D MAX_UINT64) {
               break;
@@ -877,8 +965,10 @@ NotifyPhase (
                             TRUE,
                             RootBridge->ResAllocNode[Index].Length,
                             MIN (31, BitsOfAlignment),
-                            ALIGN_VALUE (RootBridge->PMem.Base, Alignment =
+ 1),
-                            RootBridge->PMem.Limit
+                            TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMem=
.Base, Alignment + 1),
+                              RootBridge->PMem.Translation),
+                            TO_HOST_ADDRESS (RootBridge->PMem.Limit,
+                              RootBridge->PMem.Translation)
                             );
             break;
=20
@@ -1421,7 +1511,14 @@ GetProposedResources (
           Descriptor->Desc                  =3D ACPI_ADDRESS_SPACE_DESCRIP=
TOR;
           Descriptor->Len                   =3D sizeof (EFI_ACPI_ADDRESS_S=
PACE_DESCRIPTOR) - 3;;
           Descriptor->GenFlag               =3D 0;
-          Descriptor->AddrRangeMin          =3D RootBridge->ResAllocNode[I=
ndex].Base;
+          //
+          // AddrRangeMin in Resource Descriptor here should be device add=
ress
+          // instead of host address, or else PCI bus driver cannot set co=
rrect
+          // address into PCI BAR registers.
+          // Base in ResAllocNode is a host address, so conversion is need=
ed.
+          //
+          Descriptor->AddrRangeMin          =3D TO_DEVICE_ADDRESS (RootBri=
dge->ResAllocNode[Index].Base,
+            GetTranslationByResourceType (RootBridge, Index));
           Descriptor->AddrRangeMax          =3D 0;
           Descriptor->AddrTranslationOffset =3D (ResStatus =3D=3D ResAlloc=
ated) ? EFI_RESOURCE_SATISFIED : PCI_RESOURCE_LESS;
           Descriptor->AddrLen               =3D RootBridge->ResAllocNode[I=
ndex].Length;
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeM=
odulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index dc06c16dc038..5dd9d257d46d 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -86,12 +86,35 @@ CreateRootBridge (
           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_=
PMEM) !=3D 0 ? L"CombineMemPMem " : L"",
           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE=
) !=3D 0 ? L"Mem64Decode" : L""
           ));
+  //
+  // Translation for bus is not supported.
+  //
   DEBUG ((EFI_D_INFO, "           Bus: %lx - %lx\n", Bridge->Bus.Base, Bri=
dge->Bus.Limit));
-  DEBUG ((EFI_D_INFO, "            Io: %lx - %lx\n", Bridge->Io.Base, Brid=
ge->Io.Limit));
-  DEBUG ((EFI_D_INFO, "           Mem: %lx - %lx\n", Bridge->Mem.Base, Bri=
dge->Mem.Limit));
-  DEBUG ((EFI_D_INFO, "    MemAbove4G: %lx - %lx\n", Bridge->MemAbove4G.Ba=
se, Bridge->MemAbove4G.Limit));
-  DEBUG ((EFI_D_INFO, "          PMem: %lx - %lx\n", Bridge->PMem.Base, Br=
idge->PMem.Limit));
-  DEBUG ((EFI_D_INFO, "   PMemAbove4G: %lx - %lx\n", Bridge->PMemAbove4G.B=
ase, Bridge->PMemAbove4G.Limit));
+  ASSERT (Bridge->Bus.Translation =3D=3D 0);
+  if (Bridge->Bus.Translation !=3D 0) {
+    return NULL;
+  }
+
+  DEBUG ((
+    DEBUG_INFO, "            Io: %lx - %lx Translation=3D%lx\n",
+    Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation
+    ));
+  DEBUG ((
+    DEBUG_INFO, "           Mem: %lx - %lx Translation=3D%lx\n",
+    Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation
+    ));
+  DEBUG ((
+    DEBUG_INFO, "    MemAbove4G: %lx - %lx Translation=3D%lx\n",
+    Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAbove4G.=
Translation
+    ));
+  DEBUG ((
+    DEBUG_INFO, "          PMem: %lx - %lx Translation=3D%lx\n",
+    Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation
+    ));
+  DEBUG ((
+    DEBUG_INFO, "   PMemAbove4G: %lx - %lx Translation=3D%lx\n",
+    Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMemAbove=
4G.Translation
+    ));
=20
   //
   // Make sure Mem and MemAbove4G apertures are valid
@@ -206,7 +229,12 @@ CreateRootBridge (
     }
     RootBridge->ResAllocNode[Index].Type     =3D Index;
     if (Bridge->ResourceAssigned && (Aperture->Limit >=3D Aperture->Base))=
 {
-      RootBridge->ResAllocNode[Index].Base   =3D Aperture->Base;
+      //
+      // Base in ResAllocNode is a host address, while Base in Aperture is=
 a
+      // device address.
+      //
+      RootBridge->ResAllocNode[Index].Base   =3D TO_HOST_ADDRESS (Aperture=
->Base,
+        Aperture->Translation);
       RootBridge->ResAllocNode[Index].Length =3D Aperture->Limit - Apertur=
e->Base + 1;
       RootBridge->ResAllocNode[Index].Status =3D ResAllocated;
     } else {
@@ -403,6 +431,28 @@ RootBridgeIoCheckParameter (
   return EFI_SUCCESS;
 }
=20
+EFI_STATUS
+RootBridgeIoGetMemTranslationByAddress (
+  IN PCI_ROOT_BRIDGE_INSTANCE               *RootBridge,
+  IN UINT64                                 Address,
+  IN OUT UINT64                             *Translation
+  )
+{
+  if (Address >=3D RootBridge->Mem.Base && Address <=3D RootBridge->Mem.Li=
mit) {
+    *Translation =3D RootBridge->Mem.Translation;
+  } else if (Address >=3D RootBridge->PMem.Base && Address <=3D RootBridge=
->PMem.Limit) {
+    *Translation =3D RootBridge->PMem.Translation;
+  } else if (Address >=3D RootBridge->MemAbove4G.Base && Address <=3D Root=
Bridge->MemAbove4G.Limit) {
+    *Translation =3D RootBridge->MemAbove4G.Translation;
+  } else if (Address >=3D RootBridge->PMemAbove4G.Base && Address <=3D Roo=
tBridge->PMemAbove4G.Limit) {
+    *Translation =3D RootBridge->PMemAbove4G.Translation;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+}
+
 /**
   Polls an address in memory mapped I/O space until an exit condition is m=
et,
   or a timeout occurs.
@@ -658,13 +708,25 @@ RootBridgeIoMemRead (
   )
 {
   EFI_STATUS                             Status;
+  PCI_ROOT_BRIDGE_INSTANCE               *RootBridge;
+  UINT64                                 Translation;
=20
   Status =3D RootBridgeIoCheckParameter (This, MemOperation, Width, Addres=
s,
                                        Count, Buffer);
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addr=
ess, Count, Buffer);
+
+  RootBridge =3D ROOT_BRIDGE_FROM_THIS (This);
+  Status =3D RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, =
&Translation);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // Address passed to CpuIo->Mem.Read needs to be a host address instead =
of
+  // device address.
+  return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
+      TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
 }
=20
 /**
@@ -705,13 +767,25 @@ RootBridgeIoMemWrite (
   )
 {
   EFI_STATUS                             Status;
+  PCI_ROOT_BRIDGE_INSTANCE               *RootBridge;
+  UINT64                                 Translation;
=20
   Status =3D RootBridgeIoCheckParameter (This, MemOperation, Width, Addres=
s,
                                        Count, Buffer);
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Add=
ress, Count, Buffer);
+
+  RootBridge =3D ROOT_BRIDGE_FROM_THIS (This);
+  Status =3D RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, =
&Translation);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // Address passed to CpuIo->Mem.Write needs to be a host address instead=
 of
+  // device address.
+  return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
+      TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
 }
=20
 /**
@@ -746,6 +820,8 @@ RootBridgeIoIoRead (
   )
 {
   EFI_STATUS                                    Status;
+  PCI_ROOT_BRIDGE_INSTANCE                      *RootBridge;
+
   Status =3D RootBridgeIoCheckParameter (
              This, IoOperation, Width,
              Address, Count, Buffer
@@ -753,7 +829,13 @@ RootBridgeIoIoRead (
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addre=
ss, Count, Buffer);
+
+  RootBridge =3D ROOT_BRIDGE_FROM_THIS (This);
+
+  // Address passed to CpuIo->Io.Read needs to be a host address instead of
+  // device address.
+  return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
+      TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer=
);
 }
=20
 /**
@@ -788,6 +870,8 @@ RootBridgeIoIoWrite (
   )
 {
   EFI_STATUS                                    Status;
+  PCI_ROOT_BRIDGE_INSTANCE                      *RootBridge;
+
   Status =3D RootBridgeIoCheckParameter (
              This, IoOperation, Width,
              Address, Count, Buffer
@@ -795,7 +879,13 @@ RootBridgeIoIoWrite (
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addr=
ess, Count, Buffer);
+
+  RootBridge =3D ROOT_BRIDGE_FROM_THIS (This);
+
+  // Address passed to CpuIo->Io.Write needs to be a host address instead =
of
+  // device address.
+  return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
+      TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer=
);
 }
=20
 /**
@@ -1615,9 +1705,17 @@ RootBridgeIoConfiguration (
=20
     Descriptor->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR;
     Descriptor->Len  =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+    // According to UEFI 2.7, RootBridgeIo->Configuration should return ad=
dress
+    // range in CPU view (host address), and ResAllocNode->Base is already=
 a CPU
+    // view address (host address).
     Descriptor->AddrRangeMin  =3D ResAllocNode->Base;
     Descriptor->AddrRangeMax  =3D ResAllocNode->Base + ResAllocNode->Lengt=
h - 1;
     Descriptor->AddrLen       =3D ResAllocNode->Length;
+    Descriptor->AddrTranslationOffset =3D GetTranslationByResourceType (
+      RootBridge,
+      ResAllocNode->Type
+      );
+
     switch (ResAllocNode->Type) {
=20
     case TypeIo:
--=20
2.7.4

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From: Heyi Guo <heyi.guo@linaro.org>
To: edk2-devel@lists.01.org
Date: Thu,  1 Mar 2018 14:57:23 +0800
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Subject: [edk2] [PATCH v5 5/6] MdeModulePkg/PciBus: convert host address to
 device address
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Cc: Ruiyu Ni <ruiyu.ni@intel.com>, Eric Dong <eric.dong@intel.com>,
 Ard Biesheuvel <ard.biesheuvel@linaro.org>, Heyi Guo <heyi.guo@linaro.org>,
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According to UEFI spec 2.7, PciRootBridgeIo->Configuration() should
return host address (CPU view ddress) rather than device address
(PCI view address), so in function GetMmioAddressTranslationOffset we
need to convert the range to device address before comparing.

And device address =3D host address + translation offset.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/=
PciBusDxe/PciIo.c
index 190f4b0dc7ed..fef3eceb7f62 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -1812,10 +1812,14 @@ GetMmioAddressTranslationOffset (
     return (UINT64) -1;
   }
=20
+  // According to UEFI 2.7, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Configuration=
()
+  // returns host address instead of device address, while AddrTranslation=
Offset
+  // is not zero, and device address =3D host address + AddrTranslationOff=
set, so
+  // we convert host address to device address for range compare.
   while (Configuration->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) {
     if ((Configuration->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) &&
-        (Configuration->AddrRangeMin <=3D AddrRangeMin) &&
-        (Configuration->AddrRangeMin + Configuration->AddrLen >=3D AddrRan=
geMin + AddrLen)
+        (Configuration->AddrRangeMin + Configuration->AddrTranslationOffse=
t <=3D AddrRangeMin) &&
+        (Configuration->AddrRangeMin + Configuration->AddrLen + Configurat=
ion->AddrTranslationOffset >=3D AddrRangeMin + AddrLen)
         ) {
       return Configuration->AddrTranslationOffset;
     }
--=20
2.7.4

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From: Heyi Guo <heyi.guo@linaro.org>
To: edk2-devel@lists.01.org
Date: Thu,  1 Mar 2018 14:57:24 +0800
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Subject: [edk2] [PATCH v5 6/6] MdeModulePkg/PciBus: return CPU address for
 GetBarAttributes
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Cc: Ruiyu Ni <ruiyu.ni@intel.com>, Eric Dong <eric.dong@intel.com>,
 Ard Biesheuvel <ard.biesheuvel@linaro.org>, Heyi Guo <heyi.guo@linaro.org>,
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According to UEFI spec 2.7, PciIo->GetBarAttributes should return host
address (CPU view ddress) rather than device address (PCI view
address), and
device address =3D host address + address translation offset,
so we subtract translation from device address before returning.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/=
PciBusDxe/PciIo.c
index fef3eceb7f62..62179eb44bbd 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -1972,6 +1972,10 @@ PciIoGetBarAttributes (
         return EFI_UNSUPPORTED;
       }
     }
+
+    // According to UEFI spec 2.7, we need return host address for
+    // PciIo->GetBarAttributes, and host address =3D device address - tran=
slation.
+    Descriptor->AddrRangeMin -=3D Descriptor->AddrTranslationOffset;
   }
=20
   return EFI_SUCCESS;
--=20
2.7.4

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