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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:41 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=y0dClf/wZRq0Kd5fFTMNat+aU6qlw58nwjAuYXqWz94=; b=iZIp1IOzzdPhMGTRonpvPAZxif95P5/ZKBVy5Wzr9vPpcAHUIBffByQ8vQwmAv/Zz7 hxVUfKw/KNZ1U9KmtUaH6reNXl/5YeW7+BF4U1aOwlrWyBFMxVSOD5vOK50BuXIs4MZc 8AAYFwCx+A6j66q/+5gEm3ztJ70AhZzd+un+Csi+8r6xGVsz1eebksuP4WfH36TJAL43 qJYYUsk6+0E3i/7NRZKnFE/NkQTf1z2zzz9fhJZF82WaKLbdp0yEzSlmBTPfjnTyfanl pvMkW2uByn6ubGxQurLUpmDEaXM848ybF9y224q3bESgh/ov/Q0hL0rgIXa/CxlIlsrX mKmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=y0dClf/wZRq0Kd5fFTMNat+aU6qlw58nwjAuYXqWz94=; b=n7b46gJq32BUxBV4mGevU2QsIRkvU3qB32wadHEMQZw0fE3VnWkCX5nI2kt3K5T0OC XeEOM2b3qpaMtdPqcL3gbb0ZEH201nZ8y6xcap3GlkkfqUwYHJzsEhGhKRHQ1+OujBOe kEkk/unPu8bjlrkc+a2qgH0eIhHhVr0eP1O3MNqfPntodB2Ut2zfRjuIxvtdt6YEEtFR V4UxO1UuJ3s9y2J7YHgR0uQjQRbL2P/43wcaNFdOcVBf1PKKW3Klzs/vFaAXt5AQnmwD 6utIgJ5wGNLLpITPJAaKTyxPyNssh2A4ho+yVZESQzv+cGiPraWPrRiwHn+L9O99b1OC bZOA== X-Gm-Message-State: APt69E33UBUxveNZilAcjhDc5Yb0BWjOH2JATaySJfwD3Ay2Jl+uUXlT voZ+qF9ikJhTNyKxrqBfhaYA0qOjJpA= X-Google-Smtp-Source: ADUXVKKDNV7E52opXD46Any4+3YZUF5QJeCkBSoLXlZ3DhtUwvxFM2VTkUrvc5L6ss9+OfbEmhOVeA== X-Received: by 2002:a19:d245:: with SMTP id j66-v6mr4498600lfg.139.1528472082317; Fri, 08 Jun 2018 08:34:42 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:33:59 +0200 Message-Id: <1528472063-1660-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 01/25] Marvell/Library: Introduce ArmadaSoCDescLib class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua ArmadaSoCDescLib is a per SoC family library, which provides SoC description, like register base of some hardware module controller, COMPHY/I2C/NETWORK etc., which right now is hardcoded in MvHwDescLib.h. There will be a new protocol, which gets SoC description from this library, and provides board description based on enable/disable values of each hardware module controller in dsc file. As a first example implement obtaining UTMI controllers information. Remaining interfaces will be added in follow-up commits. This patch introduces new library callback (ArmadaSoCDescUtmiGet ()), which dynamically allocates and fills MV_SOC_UTMI_DESC structure, SoC description of UTMI PHYs. A new PCD is introduced (PcdMaxCpCount) which stores maximal amount of CP110 blocks in the SoC family. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: jinghua Signed-off-by: Marcin Wojtas Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 78 ++++++++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.inf | 37 ++++++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 33 +++++++++ Silicon/Marvell/Marvell.dec = | 4 + 4 files changed, 152 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c new file mode 100644 index 0000000..0ee943b --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -0,0 +1,78 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implemen= tation: +* AP - Application Processor hardware block (Armada 7k8k incorporates AP8= 06) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +**/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +// +// Common macros +// +#define MV_SOC_CP_BASE(Cp) (0xF2000000 + (Cp) * 0x2000000) + +// +// Platform description of UTMI PHY's +// +#define MV_SOC_UTMI_PER_CP_COUNT 2 +#define MV_SOC_UTMI_ID(Utmi) (Utmi) +#define MV_SOC_UTMI_BASE(Utmi) (0x580000 + (Utmi) * 0x1000) +#define MV_SOC_UTMI_CFG_BASE 0x440440 +#define MV_SOC_UTMI_USB_CFG_BASE 0x440420 + +EFI_STATUS +EFIAPI +ArmadaSoCDescUtmiGet ( + IN OUT MV_SOC_UTMI_DESC **UtmiDesc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_UTMI_DESC *Desc; + UINT8 CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + UINT8 Index, CpIndex, UtmiIndex =3D 0; + + Desc =3D AllocateZeroPool (CpCount * MV_SOC_UTMI_PER_CP_COUNT * + sizeof (MV_SOC_UTMI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_UTMI_PER_CP_COUNT; Index++) { + Desc[UtmiIndex].UtmiPhyId =3D MV_SOC_UTMI_ID (UtmiIndex); + Desc[UtmiIndex].UtmiBaseAddress =3D + MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_BASE (= Index); + Desc[UtmiIndex].UtmiConfigAddress =3D + MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_CF= G_BASE; + Desc[UtmiIndex].UsbConfigAddress =3D + MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_USB_CF= G_BASE; + UtmiIndex++; + } + } + + *UtmiDesc =3D Desc; + *DescCount =3D UtmiIndex; + + return EFI_SUCCESS; +} diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLi= b/Armada7k8kSoCDescLib.inf new file mode 100644 index 0000000..e993878 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.inf @@ -0,0 +1,37 @@ +## @file +# +# Copyright (C) 2018, Marvell International Ltd. and its affiliates
+# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D Armada7k8kDescLib + FILE_GUID =3D c64f0048-4ca3-4573-b0a6-c2e9e6457285 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmadaSoCDescLib + +[Sources] + Armada7k8kSoCDescLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib + PcdLib + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdMaxCpCount diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h new file mode 100644 index 0000000..22f5c17 --- /dev/null +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -0,0 +1,33 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ +#ifndef __ARMADA_SOC_DESC_LIB_H__ +#define __ARMADA_SOC_DESC_LIB_H__ + +// +// UTMI PHY devices SoC description +// +typedef struct { + UINT8 UtmiPhyId; + UINTN UtmiBaseAddress; + UINTN UtmiConfigAddress; + UINTN UsbConfigAddress; +} MV_SOC_UTMI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescUtmiGet ( + IN OUT MV_SOC_UTMI_DESC **UtmiDesc, + IN OUT UINT8 *DescCount + ); +#endif /* __ARMADA_SOC_DESC_LIB_H__ */ diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index be74b4e..2a92eff 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -60,6 +60,7 @@ gMarvellSpiFlashDxeGuid =3D { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, = 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } } =20 [LibraryClasses] + ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h SampleAtResetLib|Include/Library/SampleAtResetLib.h =20 [Protocols] @@ -68,6 +69,9 @@ gMarvellPlatformInitCompleteProtocolGuid =3D { 0x465b8cf7, 0x016f, 0x4ba= 6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } } =20 [PcdsFixedAtBuild.common] +#Board description + gMarvellTokenSpaceGuid.PcdMaxCpCount|0x2|UINT8|0x30000072 + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001 =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472092596836.9832359340551; Fri, 8 Jun 2018 08:34:52 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 57B0821109387; Fri, 8 Jun 2018 08:34:48 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3CC7021107442 for ; Fri, 8 Jun 2018 08:34:46 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id t134-v6so20710800lff.6 for ; Fri, 08 Jun 2018 08:34:46 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:43 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/u95Jn4GF/m3nEUy3FUBimD+9uilupA7zKjsdTWvrz4=; b=Mrzc2WaLeek52T0Deyz+OKIWVhAu6k6BWJnCexXR+FYBMBx1izbi/1FNxiCsEbeCGo Pg0McF73huK9fnUwBiG11buGuFkyDm2K8vgnfu6+iq6NPTk/lFRQY3mzUVgjAc4ApJMG sRqpwzPoBcX7GLjE9LEqU6hR/pqmdH290nvvQkPgy5mMOUyNQ6RzS/xkVNykPT4RdZC8 zN643vuUYe0slb6RuwugaPvsvJDveEbHLYymCbVrITtFQK2W+PtC8b7hhgNSHDbjert4 E3RKnh9hyDnbGN0w5RgzayrXDQG+hXVQluflL2dSWAG73Zjm6dJ+cztPd9DNZApVinBB jQiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/u95Jn4GF/m3nEUy3FUBimD+9uilupA7zKjsdTWvrz4=; b=opSsjFo3pODMQojs3KxiQGCR+3UT3gFqVIdEHYsXNdvRZU8cYfpopVBjRAqIZoMA9o 9IeYBqE/R6NeWmy+Ic+0dKokiMgd4kBTXRjwzbdb6TU/8w+nmpvDEABp281Tm75eWOlw 9kW7oZlQGGD6MYkjJSi2qWhL31ILrB7i5qVWD2ypkoPiqIZinVmGXQOeHW83v/97RcSm e3YobDJ49mHzlp6oBjSwXq50wFtz53PKG7FBj4rjqy1ZP6fOk1T/GYRLPMKuFm1hC0xf wkpWEbXZKcKUgo393hMRwTcM7LUWuxUCUAuZftIceG6XHSG8J1tCRK4nRhncmxsVYRxs hQ7A== X-Gm-Message-State: APt69E0ecFHqxeN3+9jFKnBJTcH81ZWIe86kKE3q8Mkq9q3CJI3clMi1 l7DdJQ4iwnh5CFXpOCZjuwibrJa7riw= X-Google-Smtp-Source: ADUXVKLazg/hI9mdEH1HV9OaokN0j/bEzHHbXUjdFmm2TtXmnAGhe1asbHNiHSvFaQHg/w6btcoFMA== X-Received: by 2002:a19:5c4b:: with SMTP id q72-v6mr4141393lfb.128.1528472083768; Fri, 08 Jun 2018 08:34:43 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:00 +0200 Message-Id: <1528472063-1660-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 02/25] Marvell/Library: Introduce ArmadaBoardDescLib class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch adds a new library class that will be helpful to describe a per-board information, which will be processed by BoardDesc protocol. Together with ArmadaSoCDescLib data it will be a flexible solution allowing to provide complete information to the drivers, replacing faulty MvHwDescLib.h. Initially ArmadaBoardDescLib defines per-board UTMI PHYs information structure. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 27 ++++++++++++++++= ++++ Silicon/Marvell/Marvell.dec | 1 + 2 files changed, 28 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h new file mode 100644 index 0000000..2d50067 --- /dev/null +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -0,0 +1,27 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ +#ifndef __ARMADA_BOARD_DESC_LIB_H__ +#define __ARMADA_BOARD_DESC_LIB_H__ + +#include + +// +// UTMI PHY devices per-board description +// +typedef struct { + MV_SOC_UTMI_DESC *SoC; + UINT8 UtmiDevCount; + UINT8 UtmiPortType; +} MV_BOARD_UTMI_DESC; +#endif /* __ARMADA_SOC_DESC_LIB_H__ */ diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 2a92eff..db49300 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -60,6 +60,7 @@ gMarvellSpiFlashDxeGuid =3D { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, = 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } } =20 [LibraryClasses] + ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h SampleAtResetLib|Include/Library/SampleAtResetLib.h =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472098181810.7224487798865; Fri, 8 Jun 2018 08:34:58 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9000F211093A1; Fri, 8 Jun 2018 08:34:48 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 105DE21107174 for ; Fri, 8 Jun 2018 08:34:47 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id t134-v6so20710890lff.6 for ; Fri, 08 Jun 2018 08:34:46 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:44 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8knC8Gx3f0N6uSsuR2yumGnOL/sMlCNLQBYkZVHzwWw=; b=Rg5LqSee7iM5nx86TcqfydOn9pBQhTP/ykBpAoz+cYyLC0607pvndkIWdOfYiXDmzx gHs5HzVOeq6aNpW5UiiHDbWYM+308a+BOeofCLnH/Ni6UyvOZNH8hOeAP8++JR6yy52J IaOjmEpd9IPyh3MdLsmKJUzhOaYCgd7W7RU3yI+m7iDFK0kt6a946v+TKnsEn1DGqCWZ 0nmaQwv/KCQ33vCNgWElTai6KBsfXkJEvXu1lapMdx9qiya6L8M9FqGtyc068kIAByF0 x0KootVo1983a9Dsd+Tuwv0VqYuTZJH5aveHCzQJBmgMW2LiwInQq56Lzxs+wDeITfgk 6z9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8knC8Gx3f0N6uSsuR2yumGnOL/sMlCNLQBYkZVHzwWw=; b=UNoZQcN4J+GeGoBl7XgirIcGbJ6r6YKyFBIlwIzC9PNfrcKQAf+KyR3xZ2BbhblSbl eEt/r9Pm3Yslm+kH+vpN4x2MazscFa8HhJnplBX1c2BvhSuwt/QCDAdhx2ywRzmWPQSn 3fi6tZLicNokJiJ57ptz3j2m3ovdXzpPN3rGlNJfXrOASSKF8ngcSxm0J91A7+qdNWs7 VOEnj8bqLK9Iz17MWu6oan1F2DKCuZ7yFkAoF+/8AtKeGMDZYUeCc+k5nK/quMalPvvD YJc14RGoOP+E9B5XvP9A89MP/D3KytzzWXL7xKQwOP4Fax41NUpcH1YtJMeYHCiwRiwJ wfvg== X-Gm-Message-State: APt69E2IS7udAUEg61UuOSzUB79qF8xPI8VC8wZ841QeDaTOjq7LHVpB gXSfTvC2Dny/8+cmLp45jLnk2g65QrI= X-Google-Smtp-Source: ADUXVKIHzLh12emcYJQVxas8XPgD0CgyQpwyiuKlJba44Y9FMM65XAcETxfrBqW2KprvroFX86h6mA== X-Received: by 2002:a19:6a0f:: with SMTP id u15-v6mr4455120lfu.81.1528472084933; Fri, 08 Jun 2018 08:34:44 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:01 +0200 Message-Id: <1528472063-1660-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 03/25] Marvell: Introduce MARVELL_BOARD_DESC_PROTOCOL X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua This patch introduces protocol that exposes generic API to get board description. It uses ArmadaSoCDescLib library, which is implemented per SoC family to get the SoC level description for hardware module controller. Together with the information obtained from ArmadaBoardDescLib the protocol allows the drivers to get per-board information about used hardware and settings. As a first usage a UTMI information obtaining is implemented. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: jinghua Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Include/Protocol/BoardDesc.h | 62 ++++++++++++++++++++ Silicon/Marvell/Marvell.dec | 1 + 2 files changed, 63 insertions(+) diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h new file mode 100644 index 0000000..f8a2902 --- /dev/null +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -0,0 +1,62 @@ +/*************************************************************************= ****** +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ +#ifndef __MARVELL_BOARD_DESC_PROTOCOL_H__ +#define __MARVELL_BOARD_DESC_PROTOCOL_H__ + +#include +#include + +extern EFI_GUID gMarvellBoardDescProtocolGuid; + +typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOARD_DESC_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_UTMI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_UTMI_DESC **UtmiDesc + ); + +typedef +VOID +(EFIAPI *MV_BOARD_DESC_FREE) ( + IN VOID *BoardDesc + ); + +struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; + MV_BOARD_DESC_FREE BoardDescFree; +}; + +#endif // __MARVELL_BOARD_DESC_PROTOCOL_H__ diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index db49300..6861cc4 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -212,6 +212,7 @@ gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0|UINT32|0x50000001 =20 [Protocols] + gMarvellBoardDescProtocolGuid =3D { 0xebed8738, 0xd4a6, 0x400= 1, { 0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }} gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} gMarvellPhyProtocolGuid =3D { 0x32f48a43, 0x37e3, 0x4ac= f, { 0x93, 0xc4, 0x3e, 0x57, 0xa7, 0xb0, 0xfb, 0xdc }} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 152847210200473.85148130664663; Fri, 8 Jun 2018 08:35:02 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B853D21107442; Fri, 8 Jun 2018 08:34:49 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 743432110938F for ; Fri, 8 Jun 2018 08:34:48 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id t134-v6so20711015lff.6 for ; Fri, 08 Jun 2018 08:34:48 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:45 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DO53Tfshzj2I6e7mGU9VrOBntbFqkllSigcHwOuaCZE=; b=HScsAmVfPsitXEECrUw+eqkhI/zcOcBSfzyUaj2XfnaegkVbqqBpYWYEAvZo9QyoSb /GPk6OUeGbM1yXjZe9SC7SkC7qGrcFJ7LRHftc29Q2kLR5pqJVStOr4VBEZea5A3lpqi /smJTm0/xDN5OA+/+B+2qNJjGLqE+TAbeIK1BtgZikjJkwh1/mGoIo6HjgsBtCYo74tu hcEEi5QgIuxiLCnJkz5mj+39vxKB5QNz32NdNnX1OEcwr9ClOFQ4TCuyOmiRvQ3NpyL4 NALNMA7QrLrBZ+VtILoxXYIWYCQlXs4SljURwn+fQfJTSBiHrIuB/EIyr8jARQdnu0Lm FZyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DO53Tfshzj2I6e7mGU9VrOBntbFqkllSigcHwOuaCZE=; b=OEmxGhu2NEnSGOt/ry98yC41LpFsMbiQ8PnNaTAbweLcBsZeumYAmDebRLqW1Kx8oz Oyz/Bk0nzTf67uXJPm3UdokuXvCd1xyQWsYimVvrCt+waFVU+ckWqC3FTQvrpOLQhpSB sI+P0Doo+gwIv72aT3xwhYwqq9vWJ2zQ7+QUgC4krjtHZdUDss1AX4tWhh2XYZISLVjs uQuv5z6b9AYAXUUpcyLz/9VU6qkodftMYHkqyQmkyBtk7LXpP3DFsh4rYDOjOKNZVzHT ZdDAWyWIxyIkjrnBWUJMV2trR2xsStxq3j5K/TZJiWx7t1N6uFa6gLrAXeyHOPeQVxwT 8/1g== X-Gm-Message-State: APt69E1Q0TjEjWtxAanvhVHAaw8Zi0nzOqJUog65V6fsn+eTEV7sUe4g ULwZNcpfUmF/SY7JSZxLUUWKoalRxb4= X-Google-Smtp-Source: ADUXVKJ19i/kBH9xwaRO1e+LhO9s5vI2F1+7c47lV17zz7XOo+847tjboIXe3BdePWR6AOlLLIJSjw== X-Received: by 2002:a19:2813:: with SMTP id o19-v6mr1942514lfo.108.1528472086192; Fri, 08 Jun 2018 08:34:46 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:02 +0200 Message-Id: <1528472063-1660-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 04/25] Marvell/Drivers: MvBoardDescDxe: Introduce board description driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua This patch introduces a producer of MARVELL_BOARD_DESC_PROTOCOL, which gets SoC description from ArmadaSoCDescLib, then based on dsc file, provide only enabled hardware module controllers for the consumers, which are typically controllers' drivers. Thanks to that there is a separation between obtaining the platform description and the drivers. A first example of the board description callback is information about UTMI controllers and type. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: jinghua Signed-off-by: Marcin Wojtas Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 174 +++++++++++++++= +++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h | 59 +++++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 65 ++++++++ 3 files changed, 298 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c new file mode 100644 index 0000000..c220e58 --- /dev/null +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -0,0 +1,174 @@ +/*************************************************************************= ****** +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ +#include "MvBoardDescDxe.h" + +MV_BOARD_DESC *mBoardDescInstance; + +STATIC +EFI_STATUS +MvBoardDescUtmiGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_UTMI_DESC **UtmiDesc + ) +{ + UINT8 *UtmiDeviceTable, *XhciDeviceTable, *UtmiPortType, UtmiCount; + UINTN UtmiDeviceTableSize, UtmiIndex, Index; + MV_BOARD_UTMI_DESC *BoardDesc; + MV_SOC_UTMI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available UTMI controllers */ + Status =3D ArmadaSoCDescUtmiGet (&SoCDesc, &UtmiCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled Utmi PHY's */ + UtmiDeviceTable =3D (UINT8 *)PcdGetPtr (PcdUtmiControllersEnabled); + if (UtmiDeviceTable =3D=3D NULL) { + /* No UTMI PHY on platform */ + return EFI_SUCCESS; + } + + /* Make sure XHCI controllers table is present */ + XhciDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciEXhci); + if (XhciDeviceTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Missing PcdPciEXhci\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + UtmiDeviceTableSize =3D PcdGetSize (PcdUtmiControllersEnabled); + + /* Check if PCD with UTMI PHYs is correctly defined */ + if (UtmiDeviceTableSize > UtmiCount || + UtmiDeviceTableSize > PcdGetSize (PcdPciEXhci)) { + DEBUG ((DEBUG_ERROR, + "%a: Wrong PcdUtmiControllersEnabled format\n", + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Obtain port type table */ + UtmiPortType =3D (UINT8 *)PcdGetPtr (PcdUtmiPortType); + if (UtmiPortType =3D=3D NULL || + PcdGetSize (PcdUtmiPortType) !=3D UtmiDeviceTableSize) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdUtmiPortType format\n", __FUNCTION_= _)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (UtmiDeviceTableSize * sizeof (MV_BOARD_U= TMI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + UtmiIndex =3D 0; + for (Index =3D 0; Index < UtmiDeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (Utmi, Index)) { + continue; + } + + /* UTMI PHY without enabled XHCI controller is useless */ + if (!MVHW_DEV_ENABLED (Xhci, Index)) { + DEBUG ((DEBUG_ERROR, + "%a: Disabled Xhci controller %d\n", + Index, + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + BoardDesc[UtmiIndex].SoC =3D &SoCDesc[Index]; + BoardDesc[UtmiIndex].UtmiPortType =3D UtmiPortType[Index]; + UtmiIndex++; + } + + BoardDesc->UtmiDevCount =3D UtmiIndex; + + *UtmiDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +VOID +MvBoardDescFree ( + IN VOID *BoardDesc + ) +{ + if (BoardDesc !=3D NULL) { + FreePool (BoardDesc); + } +} + +STATIC +EFI_STATUS +MvBoardDescInitProtocol ( + IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol + ) +{ + BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; + BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvBoardDescEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mBoardDescInstance =3D AllocateZeroPool (sizeof (MV_BOARD_DESC)); + if (mBoardDescInstance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + MvBoardDescInitProtocol (&mBoardDescInstance->BoardDescProtocol); + + mBoardDescInstance->Signature =3D BOARD_DESC_SIGNATURE; + + Status =3D gBS->InstallMultipleProtocolInterfaces (&(mBoardDescInstance-= >Handle), + &gMarvellBoardDescProtocolGuid, + &(mBoardDescInstance->BoardDescProtocol)); + if (EFI_ERROR (Status)) { + FreePool (mBoardDescInstance); + return Status; + } + + return EFI_SUCCESS; +} diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.h new file mode 100644 index 0000000..47d9a72 --- /dev/null +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h @@ -0,0 +1,59 @@ +/*************************************************************************= ****** +Copyright (C) 2018 Marvell International Ltd. +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ +#ifndef __MV_BOARD_DESC_H__ +#define __MV_BOARD_DESC_H__ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define BOARD_DESC_SIGNATURE SIGNATURE_64 ('B', 'O', 'A'= , 'R', 'D', 'D', 'S', 'C') + +typedef struct { + MARVELL_BOARD_DESC_PROTOCOL BoardDescProtocol; + UINTN Signature; + EFI_HANDLE Handle; + EFI_LOCK Lock; +} MV_BOARD_DESC; + +#define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index]) + +#endif // __MV_BOARD_DESC_H__ diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf new file mode 100644 index 0000000..9367833 --- /dev/null +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -0,0 +1,65 @@ +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute +# and/or modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are m= et: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS = IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPO= SE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIA= BLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTI= AL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS = OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEV= ER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABI= LITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF TH= E USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D BoardDescDxe + FILE_GUID =3D 4ed385f9-5d2c-4774-95c5-d5d9d70b3c37 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D MvBoardDescEntryPoint + +[Sources] + MvBoardDescDxe.c + MvBoardDescDxe.h + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + ArmadaSoCDescLib + DebugLib + MemoryAllocationLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gMarvellBoardDescProtocolGuid + +[Pcd] + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled + gMarvellTokenSpaceGuid.PcdUtmiPortType + gMarvellTokenSpaceGuid.PcdPciEXhci + +[Depex] + TRUE --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472106009463.9582133785781; Fri, 8 Jun 2018 08:35:06 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E6B812110747D; Fri, 8 Jun 2018 08:34:50 -0700 (PDT) Received: from mail-lf0-x233.google.com (mail-lf0-x233.google.com [IPv6:2a00:1450:4010:c07::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D6F8F211093B0 for ; Fri, 8 Jun 2018 08:34:49 -0700 (PDT) Received: by mail-lf0-x233.google.com with SMTP id n15-v6so20684187lfn.10 for ; Fri, 08 Jun 2018 08:34:49 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:46 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::233; helo=mail-lf0-x233.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F4U2QQ8DYGHCwSfwK639K/hbrOAhoesP13gD4gcYN1E=; b=hK6e82+yyXOtth9AGXVzqFiM1CZaJbGI0MeFQMazRTVsDhm4UHpPGjpfFS/8FUIc4C +cq+OMvH4iK44jpLWnfsXs1N+oh+BmtGeJ1xDMAuGQWa5WkpV3K6jZmeiawmcZRomr5A ywk59jP/iGx1h91HCQ5YYa82R2AEFfCIpl13mclf7tPq9Q2TRcgwUIL3FLXDWt8Sj5ty qvCH4oWH5OyfyT+NoSQZPB0CPfa+Zia3lsL49sR2SBYESbD0g/Ed3WQXoF1j8KE6LIsy a+PQUU3M6fTLK57O1282SyuDwJnK9ZAuyDtrR5zHiXbBTrO57T8IWPcw4AGlpt9LFFUT x9Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F4U2QQ8DYGHCwSfwK639K/hbrOAhoesP13gD4gcYN1E=; b=YWgqtAp3SlSRY1QEX9bP0QOSExFJ+D6WFr4/Y5TLjW6aXYl5zHB4nB1hzyRx8e5QHM e8WCuIjVzYp6a41Ib6HOXcIKg/5J2Xk0lqxSosNRWblP/uK8i5eubnyuAzjFxFuHGTFx du77gAqoWu5eL2NcdeUWkmwvz34guo5AT3CrGxezP9Zs9YlU2hHRgxC/Ev78N4dlmj5g +RAq80A1ECfdeacOYc0Udc47rbLvnMM/Rb2u+1yxopX+Adj01xEnb51vCf1MH157WDw/ JR64RlX06R7vNNpo3D3T4suije/hZkIHENtDVZXysX+nBCB2nxXTooykG/xiHKwVMBD8 6YFg== X-Gm-Message-State: APt69E0lJpu8OwjfTUBlKI2SYGMnPTo36NwcE3HYevyLr4zeuSmUzLTu 7FhOnfIH3CQ6G5trBU/NVK1rVDiQlSU= X-Google-Smtp-Source: ADUXVKKpg3S/NHnVD6Jhu4Tg8hRYWcC1fEpU+wTxwJS2kaGM/JmD18R9pRU2mGpn2FcGKhDl6v1p7w== X-Received: by 2002:a19:4e86:: with SMTP id u6-v6mr4439874lfk.105.1528472087687; Fri, 08 Jun 2018 08:34:47 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:03 +0200 Message-Id: <1528472063-1660-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 05/25] Marvell/Armada7k8k: Enable board description driver compilation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua This patch enables compilation of MvBoardDescDxe driver for Armada70x0-DB, Armada80x0-DB and Armada80x0McBin. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: jinghua Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf | 1 + Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 2 ++ 2 files changed, 3 insertions(+) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.fdf index e5e5443..15c2778 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf @@ -106,6 +106,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c # # Platform Initialization # + INF Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf INF Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf =20 # PI DXE Drivers producing Architectural Protocols (EFI Services) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index 75fa3d4..a9d67a2 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -32,6 +32,7 @@ #SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # [LibraryClasses.common] + ArmadaSoCDescLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.inf ArmPlatformLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k= 8kLib.inf ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf MppLib|Silicon/Marvell/Library/MppLib/MppLib.inf @@ -449,6 +450,7 @@ ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf =20 # Platform Initialization + Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf =20 # Platform drivers --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472110108826.834055276695; Fri, 8 Jun 2018 08:35:10 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 19463211093B4; Fri, 8 Jun 2018 08:34:53 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EA8AB211093B4 for ; Fri, 8 Jun 2018 08:34:50 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id i15-v6so10403070lfc.2 for ; Fri, 08 Jun 2018 08:34:50 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:48 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KaeNmCgUwzKo0rFUE89PEg82du/3WfZ/J5gU+rBCCBU=; b=krLkpaPw0ppzeaOTD8s0RYRgKJfDgCSFwS6sv+CnW5AbUrC5OfQPj/ifgZ5azZELm7 J/7vcxVCNGwMy1uUqgd/jH2BPJo9YVtVDATvkS2GXShMAr5it2v6vWwu+auHcjtVI5// gB1OdBtOX+5IqTHmkpycPqZiG538my2WO4cQwoPX3McLUtcb8nLJ0Dwti5fdKXckKIuw S2X5H2teWqe9LgkCsTJxIQs1KGdLvy7fFMK3i37iqa1b/EybUOap6WNtzQLVD90QMf5p BeNAgXLc7Gsd+nNDoS8qkueQBrYgcmRfRDzOCFzGxpLFZNjIfCCYqQrergT+BUsPDjzY LFSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KaeNmCgUwzKo0rFUE89PEg82du/3WfZ/J5gU+rBCCBU=; b=kyTOhqNzljCSB+xinOP6lE4Gu3pei3voIqU7JALHgNbp4rj6zS20MrH5nRta838yWt N7IV5LhFIAEtLXGPrkRUhEC7k82NArvcL0yWwZDGG5063vXluHwQM5ljzRkdfQJ958qi InRl+zGnvjGZrk41s+y7UXDp1Eah7+HZfuITpERsL/tPKiNbbnlkc7anld8RU3vKItoD IWTfj4xOB5/ra5aR54uKrqUgtiBIEBAFzkXp8gIAWL5sMoUg89cGl8hhEwoLYsQWiBsM LJH/q1dWF3U0gT0gwwrIVzu78wWxdMmilCX/YUX7BgYdT9KhzEBgi8QCyKDYS9iXI/J3 DdWA== X-Gm-Message-State: APt69E3n85k49PvpuvZi1+civLy8Td6+88XVAJF3xrIenQKtHPZkLiWK lRv4BHUvrSfWtZSJR5BR15BA1eE8Q00= X-Google-Smtp-Source: ADUXVKKYpBQckrMUZ9CqfY5KGUaI9ZzHAJMb2MYUBbEvFGOdOfzeBTQajvTMxX8NrCmb1YvKI1gzpw== X-Received: by 2002:a19:f71a:: with SMTP id z26-v6mr4163366lfe.137.1528472088952; Fri, 08 Jun 2018 08:34:48 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:04 +0200 Message-Id: <1528472063-1660-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 06/25] Marvell/Library: UtmiPhyLib: Switch to use MARVELL_BOARD_DESC protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" UTMI driver used to get Armada7k8k UTMI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get UTMI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Use the protocol and pass information to further to the library init routine. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 - Silicon/Marvell/Include/Library/MvHwDescLib.h | 47 --= ------------ Silicon/Marvell/Include/Library/UtmiPhyLib.h | 2 + Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 65 ++= +++++------------- Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 5 ++ Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 9 ++- 6 files changed, 32 insertions(+), 97 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index d38b467..f2c173c 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -51,7 +51,6 @@ DebugLib MemoryAllocationLib MppLib - UtmiPhyLib =20 [Sources.common] Armada7k8kLib.c diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 9ae03d0..e13814a 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -127,19 +127,6 @@ typedef struct { } MVHW_RTC_DESC; =20 // -// UTMI PHY's description template definition -// - -typedef struct { - UINT8 UtmiDevCount; - UINT32 UtmiPhyId[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiBaseAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiConfigAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiUsbConfigAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiMuxBitCount[MVHW_MAX_XHCI_DEVS]; -} MVHW_UTMI_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -253,38 +240,4 @@ MVHW_RTC_DESC mA7k8kRtcDescTemplate =3D {\ { SIZE_4KB, SIZE_4KB }\ } =20 -// -// Platform description of UTMI PHY's -// -#define MVHW_CP0_UTMI0_BASE 0xF2580000 -#define MVHW_CP0_UTMI0_CFG_BASE 0xF2440440 -#define MVHW_CP0_UTMI0_USB_CFG_BASE 0xF2440420 -#define MVHW_CP0_UTMI0_ID 0x0 -#define MVHW_CP0_UTMI1_BASE 0xF2581000 -#define MVHW_CP0_UTMI1_CFG_BASE 0xF2440444 -#define MVHW_CP0_UTMI1_USB_CFG_BASE 0xF2440420 -#define MVHW_CP0_UTMI1_ID 0x1 -#define MVHW_CP1_UTMI0_BASE 0xF4580000 -#define MVHW_CP1_UTMI0_CFG_BASE 0xF4440440 -#define MVHW_CP1_UTMI0_USB_CFG_BASE 0xF4440420 -#define MVHW_CP1_UTMI0_ID 0x0 -#define MVHW_CP1_UTMI1_BASE 0xF4581000 -#define MVHW_CP1_UTMI1_CFG_BASE 0xF4440444 -#define MVHW_CP1_UTMI1_USB_CFG_BASE 0xF4440420 -#define MVHW_CP1_UTMI1_ID 0x1 - -#define DECLARE_A7K8K_UTMI_TEMPLATE \ -STATIC \ -MVHW_UTMI_DESC mA7k8kUtmiDescTemplate =3D {\ - 4,\ - { MVHW_CP0_UTMI0_ID, MVHW_CP0_UTMI1_ID,\ - MVHW_CP1_UTMI0_ID, MVHW_CP1_UTMI1_ID },\ - { MVHW_CP0_UTMI0_BASE, MVHW_CP0_UTMI1_BASE,\ - MVHW_CP1_UTMI0_BASE, MVHW_CP1_UTMI1_BASE },\ - { MVHW_CP0_UTMI0_CFG_BASE, MVHW_CP0_UTMI1_CFG_BASE,\ - MVHW_CP1_UTMI0_CFG_BASE, MVHW_CP1_UTMI1_CFG_BASE },\ - { MVHW_CP0_UTMI0_USB_CFG_BASE, MVHW_CP0_UTMI1_USB_CFG_BASE,\ - MVHW_CP1_UTMI0_USB_CFG_BASE, MVHW_CP1_UTMI1_USB_CFG_BASE }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Include/Library/UtmiPhyLib.h b/Silicon/Marvell= /Include/Library/UtmiPhyLib.h index 7c62cba..6f4e355 100644 --- a/Silicon/Marvell/Include/Library/UtmiPhyLib.h +++ b/Silicon/Marvell/Include/Library/UtmiPhyLib.h @@ -35,6 +35,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __UTMIPHYLIB_H__ #define __UTMIPHYLIB_H__ =20 +#include + EFI_STATUS UtmiPhyInit ( VOID diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marv= ell/Library/UtmiPhyLib/UtmiPhyLib.c index 2cd9cfa..cef1279 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c @@ -33,9 +33,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. **************************************************************************= *****/ =20 #include "UtmiPhyLib.h" -#include - -DECLARE_A7K8K_UTMI_TEMPLATE; =20 typedef struct { EFI_PHYSICAL_ADDRESS UtmiBaseAddr; @@ -288,67 +285,47 @@ UtmiPhyInit ( VOID ) { + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_UTMI_DESC *BoardDesc; UTMI_PHY_DATA UtmiData; - UINT8 *UtmiDeviceTable, *XhciDeviceTable, *UtmiPortType, Index; - MVHW_UTMI_DESC *Desc =3D &mA7k8kUtmiDescTemplate; - - /* Obtain table with enabled Utmi PHY's*/ - UtmiDeviceTable =3D (UINT8 *)PcdGetPtr (PcdUtmiControllersEnabled); - if (UtmiDeviceTable =3D=3D NULL) { - /* No UTMI PHY on platform */ - return EFI_SUCCESS; - } - - if (PcdGetSize (PcdUtmiControllersEnabled) > MVHW_MAX_XHCI_DEVS) { - DEBUG ((DEBUG_ERROR, "UTMI: Wrong PcdUtmiControllersEnabled format\n")= ); - return EFI_INVALID_PARAMETER; - } + EFI_STATUS Status; + UINTN Index; =20 - /* Make sure XHCI controllers table is present */ - XhciDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciEXhci); - if (XhciDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "UTMI: Missing PcdPciEXhci\n")); - return EFI_INVALID_PARAMETER; + /* Obtain board description */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } =20 - /* Obtain port type table */ - UtmiPortType =3D (UINT8 *)PcdGetPtr (PcdUtmiPortType); - if (UtmiPortType =3D=3D NULL || - PcdGetSize (PcdUtmiPortType) !=3D PcdGetSize (PcdUtmiControllersEnab= led)) { - DEBUG ((DEBUG_ERROR, "UTMI: Wrong PcdUtmiPortType format\n")); - return EFI_INVALID_PARAMETER; + Status =3D BoardDescProtocol->BoardDescUtmiGet (BoardDescProtocol, &Boar= dDesc); + if (EFI_ERROR (Status)) { + return Status; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdUtmiControllersEnabled); Index+= +) { - if (!MVHW_DEV_ENABLED (Utmi, Index)) { - continue; - } - - /* UTMI PHY without enabled XHCI controller is useless */ - if (!MVHW_DEV_ENABLED (Xhci, Index)) { - DEBUG ((DEBUG_ERROR, "UTMI: Disabled Xhci controller %d\n", Index)); - return EFI_INVALID_PARAMETER; - } - + for (Index =3D 0; Index < BoardDesc->UtmiDevCount; Index++) { /* Get base address of UTMI phy */ - UtmiData.UtmiBaseAddr =3D Desc->UtmiBaseAddresses[Index]; + UtmiData.UtmiBaseAddr =3D BoardDesc[Index].SoC->UtmiBaseAddress; =20 /* Get usb config address */ - UtmiData.UsbCfgAddr =3D Desc->UtmiUsbConfigAddresses[Index]; + UtmiData.UsbCfgAddr =3D BoardDesc[Index].SoC->UsbConfigAddress; =20 /* Get UTMI config address */ - UtmiData.UtmiCfgAddr =3D Desc->UtmiConfigAddresses[Index]; + UtmiData.UtmiCfgAddr =3D BoardDesc[Index].SoC->UtmiConfigAddress; =20 /* Get UTMI PHY ID */ - UtmiData.PhyId =3D Desc->UtmiPhyId[Index]; + UtmiData.PhyId =3D BoardDesc[Index].SoC->UtmiPhyId; =20 /* Get the usb port type */ - UtmiData.UtmiPhyPort =3D UtmiPortType[Index]; + UtmiData.UtmiPhyPort =3D BoardDesc[Index].UtmiPortType; =20 /* Currently only Cp110 is supported */ Cp110UtmiPhyInit (&UtmiData); } =20 + BoardDescProtocol->BoardDescFree (BoardDesc); + return EFI_SUCCESS; } diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/Marv= ell/Library/UtmiPhyLib/UtmiPhyLib.h index 0d7d72e..7e56f1a 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h @@ -35,6 +35,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __UTMIPHY_H__ #define __UTMIPHY_H__ =20 +#include + #include #include #include @@ -42,6 +44,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include + +#include =20 #define UTMI_USB_CFG_DEVICE_EN_OFFSET 0 #define UTMI_USB_CFG_DEVICE_EN_MASK (0x1 << UTMI_USB_CFG_DEV= ICE_EN_OFFSET) diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf b/Silicon/Ma= rvell/Library/UtmiPhyLib/UtmiPhyLib.inf index 0876879..e2381f4 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf @@ -51,11 +51,10 @@ IoLib MemoryAllocationLib PcdLib + UefiBootServicesTableLib + +[Protocols] + gMarvellBoardDescProtocolGuid ## CONSUMES =20 [Sources.common] UtmiPhyLib.c - -[Pcd] - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled - gMarvellTokenSpaceGuid.PcdUtmiPortType - gMarvellTokenSpaceGuid.PcdPciEXhci --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:49 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fD6IE7kjfrgHwtjMQb1JvtYoNiughwUxynn7ieL8sNg=; b=1iCI2K5NhAbM5PAKySktLuJrj9GoUuM7K8xPwPXtzQ1bIQvN0aMNuU43whjVXHkUVf va9AHo8xMhbYFMwJPwRBKUVwC/THBweW6JPMrLAOGS9x1ZnD0GMHKgjO1LIQbIMnRGQ1 U8qqsGh//h0PKbyza0AO437ppC8H4yiYHHc84zb4YXkNRkUhDDBjFK4hFM6ELj2xPdaN 8ScEnVVho2Enws2C+sGw/QFLhnJp29yYtcVL0lnxhRNsJW01zXEsizYKXm8FwSySlHGZ tUPBqYeTdtDNkozixuP8t3pTeq3nBj/uYeLNF98X6hhwbO2ebj3f2GFfCL9f7JjnWPaM qt1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fD6IE7kjfrgHwtjMQb1JvtYoNiughwUxynn7ieL8sNg=; b=IEtB5hdaDxIZAQorNrGW6Xk0Z110TmNQcADrk7nQhgCDUDmy6uZTalIt2Yvy3MyQU1 R2hp/O1lClTavY2QJSfW2d1FAW0dFi2ImGOQ2VQOmEWsMUm501pEu4ddLZkU90Lplx6J mAJ+d3gpufIMYX5MyEnE06RxQot/aKoA3DnOqti+ZbizLzv0C//6avhSFSB920r/Krdd i/G1LS59U8v16E/Gff5Q+wLF9LYGTzUmTirFLB+HRJJWespjs2k1lqz2k5JXpTd9ACqQ hX5vFTnh522EUae7o/CqgvBS/Z0LR4wDU6AlcDYyDkx6hhLrNYaDbRSg+yJyL4sRb8SC 1XHw== X-Gm-Message-State: APt69E10A5kS1vx6r74i68Yxf6rM/GoTaSOk+psS0UM7vKmpwpr8CqWq qCG4ChryEEWrzSxKwavm7qF6TWWKI+M= X-Google-Smtp-Source: ADUXVKI/9VuE2V8gMDTgyHFr7d4n5+wz1w6wBZiC0R2vdLke7yekFSDq28fmHMMRZMGNHHD9R0LreA== X-Received: by 2002:a19:5113:: with SMTP id f19-v6mr4405030lfb.13.1528472090224; Fri, 08 Jun 2018 08:34:50 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:05 +0200 Message-Id: <1528472063-1660-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 07/25] Marvell/Library: RealTimeClockLib: Simplify obtaining base address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Hitherto mechanism of obtaining RTC base address proved to be not flexible enough to support more than one SoC family. Because there can be a single controller in use anyway, this patch drops utilization of MvHwDescLib header with hardcoded structure and replace it with simple UINT64 PCD. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc |= 2 +- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c |= 29 ++++---------------- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.inf |= 2 +- Silicon/Marvell/Include/Library/MvHwDescLib.h |= 25 ----------------- Silicon/Marvell/Marvell.dec |= 2 +- 5 files changed, 9 insertions(+), 51 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 46a1ea9..b51b6fb 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -134,4 +134,4 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x1 } + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.c b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCloc= kLib.c index d671b6a..087bd9a 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -34,7 +33,6 @@ #include #include "RealTimeClockLib.h" =20 -DECLARE_A7K8K_RTC_TEMPLATE; STATIC EFI_EVENT mRtcVirtualAddrChangeEvent; STATIC UINTN mArmadaRtcBase; =20 @@ -216,28 +214,13 @@ LibRtcInitialize ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_RTC_DESC *Desc =3D &mA7k8kRtcDescTemplate; - UINT8 *RtcDeviceTable, Index; EFI_HANDLE Handle; EFI_STATUS Status; =20 - // Pick RTC device and initialize its data - RtcDeviceTable =3D (UINT8 *) PcdGetPtr (PcdRtcEnabled); - if (RtcDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "RTC: Missing PcdRtcEnabled\n")); - return EFI_INVALID_PARAMETER; - } - - // Initialize only first of enabled controllers - for (Index =3D 0; Index < PcdGetSize (PcdRtcEnabled); Index++) { - if (MVHW_DEV_ENABLED (Rtc, Index)) { - DEBUG ((DEBUG_ERROR, "RTC: Initialize controller %d\n", Index)); - mArmadaRtcBase =3D Desc->RtcBaseAddresses[Index]; - break; - } - } + // Obtain RTC device base address + mArmadaRtcBase =3D PcdGet64 (PcdRtcBaseAddress); =20 - // Check if any of the controllers can be initialized + // Check if the controller can be initialized if (mArmadaRtcBase =3D=3D 0) { DEBUG ((DEBUG_ERROR, "RTC: None of controllers enabled\n")); return EFI_INVALID_PARAMETER; @@ -247,7 +230,7 @@ LibRtcInitialize ( Status =3D gDS->AddMemorySpace ( EfiGcdMemoryTypeMemoryMappedIo, mArmadaRtcBase, - Desc->RtcMemSize[Index], + SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ); if (EFI_ERROR (Status)) { @@ -257,7 +240,7 @@ LibRtcInitialize ( =20 Status =3D gDS->SetMemorySpaceAttributes ( mArmadaRtcBase, - Desc->RtcMemSize[Index], + SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ); if (EFI_ERROR (Status)) { @@ -304,7 +287,7 @@ LibRtcInitialize ( ErrEvent: gBS->UninstallProtocolInterface (Handle, &gEfiRealTimeClockArchProtocolG= uid, NULL); ErrSetMem: - gDS->RemoveMemorySpace (mArmadaRtcBase, Desc->RtcMemSize[Index]); + gDS->RemoveMemorySpace (mArmadaRtcBase, SIZE_4KB); =20 return Status; } diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.inf b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.inf index 59c71c4..1ecd444 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.= inf +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.= inf @@ -49,7 +49,7 @@ gEfiEventVirtualAddressChangeGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdRtcEnabled + gMarvellTokenSpaceGuid.PcdRtcBaseAddress =20 [Depex.common.DXE_RUNTIME_DRIVER] gEfiCpuArchProtocolGuid diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index e13814a..34d03d4 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -116,17 +116,6 @@ typedef struct { } MVHW_PP2_DESC; =20 // -// RealTimeClock devices description template definition -// -#define MVHW_MAX_RTC_DEVS 2 - -typedef struct { - UINT8 RtcDevCount; - UINTN RtcBaseAddresses[MVHW_MAX_RTC_DEVS]; - UINTN RtcMemSize[MVHW_MAX_RTC_DEVS]; -} MVHW_RTC_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -226,18 +215,4 @@ MVHW_PP2_DESC mA7k8kPp2DescTemplate =3D {\ { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \ } =20 -// -// Platform description of RealTimeClock devices -// -#define MVHW_CP0_RTC0_BASE 0xF2284000 -#define MVHW_CP1_RTC0_BASE 0xF4284000 - -#define DECLARE_A7K8K_RTC_TEMPLATE \ -STATIC \ -MVHW_RTC_DESC mA7k8kRtcDescTemplate =3D {\ - 2,\ - { MVHW_CP0_RTC0_BASE, MVHW_CP1_RTC0_BASE },\ - { SIZE_4KB, SIZE_4KB }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 6861cc4..4def897 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -195,7 +195,7 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT64|0x40000052 =20 #TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:50 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Qf1oEKKTk5TAv2bdKUSnLb+A7+QbpWVWnwdNA7X/NDs=; b=tHS71t4i5ZMcN4gOtpZJQtxvUvP8p2g1zCW7lZDSOUgR0tnKZtLHRsyonhwGJ7JkXM TXKpGgON1smf63ZzRglM5Do1dkQWcoqPdwT+ecL2/fvzYFknzPgE+9eoo/g3u9ubB72U O94DJi7Op6oJrnP35ctidcCtugVItRibbrKGQPM45yCFYGeJ0GDiJwALFcmHy51xF1f3 xqC4t5Yz2QMiLs2jJ+NOjRfQUmxAGJyO87laPypTG9F+vmeJk1p78UX9HxoGpkWqjstC UVcAz30/2hozVBfuFbGYL/sgzgm0yI9rwGW3BGmGIE2APc4ZV8qd9cXqN0tcSu2/4dLH V66Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Qf1oEKKTk5TAv2bdKUSnLb+A7+QbpWVWnwdNA7X/NDs=; b=qGMmRiAFKC54X6EUKWd0ZAoAvINm7Y2aX7NmDCCWDv2uRPNgMYPO0zcBGQNlcAUWfZ lrKI05zFNPQNVo8ya6Q0NdCwIvdZhVWhUd4GquqdfWaQQetkCbTXFS3fyRwi8nRiYZ8W XII3as38kuNZkrNvgI88Gg7vLoZrXk9+H26SbjGhUhguCx9gd/UcPdQUc1m7ZAy+f2Sj Lv8+gPRpc3Tn3BrdxPzp4EU0/6POtXTTLvTdZTGwLLwY8RVNoiapDPLEkD2I9COq00aK jIiE4WFDloQnt0kX3gMbDJ8qb1TmfYIFtfXU1TboAIzl06/bRqM7HGKShqdFh5Z38gaT QH3w== X-Gm-Message-State: APt69E0UBgt/z8wZWql5KUitwVljqG7d/1hMr3cQH6RBQlNSTVo2c3rx +uoSW4pzK6WTUKb/ONWLk8Vx0mmv3hg= X-Google-Smtp-Source: ADUXVKKDR7MOw57gKXQ9oOC1whpHYRWyWo/4/qXbrBlRVsBJH/G0RsowB9bGIntuqxxxLZ13EKQdrQ== X-Received: by 2002:a19:6d0a:: with SMTP id i10-v6mr4137815lfc.103.1528472091442; Fri, 08 Jun 2018 08:34:51 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:06 +0200 Message-Id: <1528472063-1660-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 08/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with PP2 information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescPp2Get ()), which dynamically allocates and fills MV_SOC_PP2_DESC structure with the SoC description of PP2 NICs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 34 ++++++++++++++++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 15 +++++++++ 2 files changed, 49 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 0ee943b..36b445e 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -32,6 +32,40 @@ #define MV_SOC_CP_BASE(Cp) (0xF2000000 + (Cp) * 0x2000000) =20 // +// Platform description of PP2 NIC +// +#define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE ((Cp)) +#define MV_SOC_PP2_CLK_FREQ 333333333 + +EFI_STATUS +EFIAPI +ArmadaSoCDescPp2Get ( + IN OUT MV_SOC_PP2_DESC **Pp2Desc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_PP2_DESC *Desc; + UINT8 CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + UINT8 CpIndex; + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_PP2_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].Pp2BaseAddress =3D MV_SOC_PP2_BASE (CpIndex); + Desc[CpIndex].Pp2ClockFrequency =3D MV_SOC_PP2_CLK_FREQ; + } + + *Pp2Desc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +// // Platform description of UTMI PHY's // #define MV_SOC_UTMI_PER_CP_COUNT 2 diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 22f5c17..559642b 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -15,6 +15,21 @@ #define __ARMADA_SOC_DESC_LIB_H__ =20 // +// PP2 NIC devices SoC description +// +typedef struct { + UINTN Pp2BaseAddress; + UINTN Pp2ClockFrequency; +} MV_SOC_PP2_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescPp2Get ( + IN OUT MV_SOC_PP2_DESC **Pp2Desc, + IN OUT UINT8 *DescCount + ); + +// // UTMI PHY devices SoC description // typedef struct { --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472122670580.7764093757097; Fri, 8 Jun 2018 08:35:22 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 93D0E2110BD5A; Fri, 8 Jun 2018 08:34:57 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9B2262110A00B for ; Fri, 8 Jun 2018 08:34:54 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id v135-v6so20696415lfa.9 for ; Fri, 08 Jun 2018 08:34:54 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pFQv1w13VJS23PJefQW2pbLcsAj1Tn7m89uIvZrCJ6A=; b=KSiTUSFOHsVFhQdyrWz8hBEM1Uc6xf3SUzhCS+RTGdk5413Tu0+lT77tyYZMeQbqJf ksITu58KSGm5oEoTwg7E+DQNDmPrViHtRNzJtwRwwd/IW1d/J9mH8/UASDuuQ/v9pTpQ J8J9Fixu9uYQHuP5RME7bW7H/sSHGtn+kSLtPioT47Hope3VpjspakotoG4c5JvO7V+A M8gLxfSfUq3+rzMB/xDUuu/nrrqOy/hnCFY+c6q84IIM0y0AtyJP3GZbZLVN4oDRG8Cf f3JNhYqwKV+jFAVfCKzfhzCH1R46Dcs4JMAtAQT+aUZKaYypJtRViUVMx1Ogbs6snMar v4WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pFQv1w13VJS23PJefQW2pbLcsAj1Tn7m89uIvZrCJ6A=; b=pxmqaZTtz8K0jCevGGmwixqh4DWn53/zME57Wpr6MW1hwmx6ywzGH2sWB8xK9lPi6P xjY/nGyk2O1u7MTmEDSWtm29SjLhiwFkhQNKURUEyb/gmRKdV4LRlwcpoddhTtX6ZLpC fB2uRwk86J9uVpXOrBVAyRfirs4WmMeZhdYqTBm4jyKAxXjI9WLI6WkvBj5EQ2nSAULK A6hznOnG7U256KtWd0lHFkliwcEm8aewkIBazM5SzqKCprDPzSzcbPEGWfH3fVAQ+6ce 2wRICA1YveWwdx1xRx4MqFpo6A4SyGJixf3wwPZHKq0wfouELob0hrAZDzq53mLopb4q QzUg== X-Gm-Message-State: APt69E2i6SSmpl6iXknelfRH/zAg+KNus5AaybIplHL3QEfFavfefb6j rMO7pJ4BUi/Vhi4jMB7F7h15NqB9ObY= X-Google-Smtp-Source: ADUXVKI/8yEjzSf/1vNeNp4w+aMvwALwspTTPOTmcwx+ARjesbKq10CtNiIwYgHb16I9xEQh/VSIfw== X-Received: by 2002:a19:c004:: with SMTP id q4-v6mr4182922lff.16.1528472092599; Fri, 08 Jun 2018 08:34:52 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:07 +0200 Message-Id: <1528472063-1660-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 09/25] Marvell/Drivers: MvBoardDesc: Extend protocol with PP2 support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about PP2 NICs to the Pp2Dxe driver. Extend ArmadaBoardDescLib with new structure MV_BOARD_PP2_DESC, for holding board specific data. In further steps it should be extended and replace PCD port's representation with the appropriate structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 60 ++++++++++++++++= ++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 11 ++++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++ 4 files changed, 80 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index c220e58..86bddad 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,65 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescPp2Get ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PP2_DESC **Pp2Desc + ) +{ + UINT8 *Pp2DeviceTable, Pp2Count; + UINTN Pp2DeviceTableSize, Pp2Index, Index; + MV_BOARD_PP2_DESC *BoardDesc; + MV_SOC_PP2_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available PP2 controllers */ + Status =3D ArmadaSoCDescPp2Get (&SoCDesc, &Pp2Count); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled PP2 NICs */ + Pp2DeviceTable =3D (UINT8 *)PcdGetPtr (PcdPp2Controllers); + if (Pp2DeviceTable =3D=3D NULL) { + /* No PP2 NIC on platform */ + return EFI_SUCCESS; + } + + Pp2DeviceTableSize =3D PcdGetSize (PcdPp2Controllers); + + /* Check if PCD with PP2 NICs is correctly defined */ + if (Pp2DeviceTableSize > Pp2Count) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPp2Controllers format\n", __FUNCTIO= N__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (Pp2DeviceTableSize * sizeof (MV_BOARD_PP= 2_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + Pp2Index =3D 0; + for (Index =3D 0; Index < Pp2DeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (Pp2, Index)) { + DEBUG ((DEBUG_ERROR, "%a: Skip Pp2 controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[Pp2Index].SoC =3D &SoCDesc[Index]; + Pp2Index++; + } + + BoardDesc->Pp2DevCount =3D Pp2Index; + + *Pp2Desc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescUtmiGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_UTMI_DESC **UtmiDesc @@ -138,6 +197,7 @@ MvBoardDescInitProtocol ( IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol ) { + BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; =20 diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index 9367833..c7d5fe2 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -57,6 +57,7 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] + gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled gMarvellTokenSpaceGuid.PcdUtmiPortType gMarvellTokenSpaceGuid.PcdPciEXhci diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 2d50067..78cf698 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,17 @@ #include =20 // +// PP2 NIC devices per-board description +// +// TODO - Extend structure with entire +// ports description instead of PCDs. +// +typedef struct { + MV_SOC_PP2_DESC *SoC; + UINT8 Pp2DevCount; +} MV_BOARD_PP2_DESC; + +// // UTMI PHY devices per-board description // typedef struct { diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index f8a2902..114a0ec 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,13 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_PP2_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PP2_DESC **Pp2Desc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_UTMI_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_UTMI_DESC **UtmiDesc @@ -55,6 +62,7 @@ VOID ); =20 struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; MV_BOARD_DESC_FREE BoardDescFree; }; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:53 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YdziK7aCOLc2ln4+VgrsMGFTh0l7gwQla7uHtsfJ9vQ=; b=14XxDsJ/TgRKUXQrr/STmcVQnJtHXkQrc/CqQsldOQV3/Rut0CoUw7yc2xmW7N/3fk 5KJFj1AJU5NlpNaPpYGAkK0gcRtNZAaUCoZhx8p5rC4vnUO2vsHmA1bG4kpkQi6K+boe cZ3X+EyGZITpmI6/PCjXKAY9DPDofpdcFGOTmM4Kc2VDKKau33B4ZPg5wr+BsFp+ljyD F3oUhXHgxBD68OxjmMqmmeyV1eaXc2G5IhqMjottu4Oaddd0y6zcmNgg+tJWkTY1IANz //LG/h2REzErRS5QYPfRBijFP9G45cUhr+d2lywrYqcYlcHZFkOMsyPxoa1HaeQ4x16S giUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YdziK7aCOLc2ln4+VgrsMGFTh0l7gwQla7uHtsfJ9vQ=; b=dsydAakbzLiK/O1w6vuwNEAaD8Sk5Bmhny1pNJKtrJSzL/Ot3NFuM/02oV+pYyrjRp W7vS6wXyeY/9gXmk/fWDBuucR9knkyZq1Ei44OCI9OvvI3pSqGdTS1iF+X7ZZgwJO73Y Mdk//oAqhX2JlyCavPUaFEGoHr+kWpG1dI0LAlOHyNVJ6xlVpI09Fj8iuug32MdZizhO OvkkrqvegvUNxyDiAqpsX+KhFi7GuvdEmQuQ7VJib354C5owIwpgEGZTsqEBKRHV1Vdk LBcq+spwWovmIYj+/q19V2iQM5uW6LBMtjrjIBIvVuhJ+jh61DqOKGpI9nSvcibYp/bY qJVw== X-Gm-Message-State: APt69E3MLkT7F1Jod9NWeQfS23k+WgE8bC+GyTH+6+RK9QH8H9BjYUfo e9UiQj8stCQhcdgRyPF4qNCOHfPtWAY= X-Google-Smtp-Source: ADUXVKIibeDVGiRjksKUeZcNS7PUUYXU+nSomi4ZfX/iUMOZsCmBFn6pmMGqzQ0v1+/CtfcFCEXr4Q== X-Received: by 2002:a2e:1092:: with SMTP id 18-v6mr5111184ljq.115.1528472093998; Fri, 08 Jun 2018 08:34:53 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:08 +0200 Message-Id: <1528472063-1660-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 10/25] Marvell/Drivers: Pp2Dxe: Switch to use MARVELL_BOARD_DESC protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Pp2Dxe driver used to get Armada7k8k PP2 controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get PP2 controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 43 ++++++++------------ Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 2 +- Silicon/Marvell/Include/Library/MvHwDescLib.h | 26 ------------ 3 files changed, 19 insertions(+), 52 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Silicon/Marvell/= Drivers/Net/Pp2Dxe/Pp2Dxe.c index 3ed10f6..4ddce22 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 **************************************************************************= *****/ =20 +#include #include #include #include @@ -42,7 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include #include #include #include @@ -54,8 +54,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #define ReturnUnlock(tpl, status) do { gBS->RestoreTPL (tpl); return (stat= us); } while(0) =20 -DECLARE_A7K8K_PP2_TEMPLATE; - STATIC PP2_DEVICE_PATH Pp2DevicePathTemplate =3D { { { @@ -1343,35 +1341,28 @@ Pp2DxeInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_PP2_DESC *Desc =3D &mA7k8kPp2DescTemplate; - UINT8 *Pp2DeviceTable, Index; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_PP2_DESC *Pp2BoardDesc; MVPP2_SHARED *Mvpp2Shared; EFI_STATUS Status; + UINT8 Index; =20 /* Obtain table with enabled Pp2 devices */ - Pp2DeviceTable =3D (UINT8 *)PcdGetPtr (PcdPp2Controllers); - if (Pp2DeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdPp2Controllers\n")); - return EFI_INVALID_PARAMETER; - } - - if (PcdGetSize (PcdPp2Controllers) > MVHW_MAX_PP2_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdPp2Controllers format\n")); - return EFI_INVALID_PARAMETER; + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } =20 - /* Check amount of declared ports */ - if (PcdGetSize (PcdPp2Port2Controller) > Desc->Pp2DevCount * MVPP2_MAX_P= ORT) { - DEBUG ((DEBUG_ERROR, "Pp2Dxe: Wrong too many ports declared\n")); - return EFI_INVALID_PARAMETER; + Status =3D BoardDescProtocol->BoardDescPp2Get (BoardDescProtocol, + &Pp2BoardDesc); + if (EFI_ERROR (Status)) { + return Status; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdPp2Controllers); Index++) { - if (!MVHW_DEV_ENABLED (Pp2, Index)) { - DEBUG ((DEBUG_ERROR, "Skip Pp2 controller %d\n", Index)); - continue; - } + for (Index =3D 0; Index < Pp2BoardDesc->Pp2DevCount; Index++) { =20 /* Initialize private data */ Mvpp2Shared =3D AllocateZeroPool (sizeof (MVPP2_SHARED)); @@ -1383,8 +1374,8 @@ Pp2DxeInitialise ( Status =3D Pp2DxeInitialiseController ( Index, Mvpp2Shared, - Desc->Pp2BaseAddresses[Index], - Desc->Pp2ClockFrequency[Index] + Pp2BoardDesc[Index].SoC->Pp2BaseAddress, + Pp2BoardDesc[Index].SoC->Pp2ClockFrequency ); if (EFI_ERROR(Status)) { FreePool (Mvpp2Shared); @@ -1393,5 +1384,7 @@ Pp2DxeInitialise ( } } =20 + BoardDescProtocol->BoardDescFree (Pp2BoardDesc); + return EFI_SUCCESS; } diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Silicon/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index fcd0611..be536ab 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -67,11 +67,11 @@ gEfiSimpleNetworkProtocolGuid gEfiDevicePathProtocolGuid gEfiCpuArchProtocolGuid + gMarvellBoardDescProtocolGuid gMarvellMdioProtocolGuid gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 34d03d4..5fd514c 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -105,17 +105,6 @@ typedef struct { } MVHW_NONDISCOVERABLE_DESC; =20 // -// PP2 NIC devices description template definition -// -#define MVHW_MAX_PP2_DEVS 4 - -typedef struct { - UINT8 Pp2DevCount; - UINTN Pp2BaseAddresses[MVHW_MAX_PP2_DEVS]; - UINTN Pp2ClockFrequency[MVHW_MAX_PP2_DEVS]; -} MVHW_PP2_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -200,19 +189,4 @@ MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTem= plate =3D {\ { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent }\ } =20 -// -// Platform description of Pp2 NIC devices -// -#define MVHW_CP0_PP2_BASE 0xF2000000 -#define MVHW_CP1_PP2_BASE 0xF4000000 -#define MVHW_PP2_CLK_FREQ 333333333 - -#define DECLARE_A7K8K_PP2_TEMPLATE \ -STATIC \ -MVHW_PP2_DESC mA7k8kPp2DescTemplate =3D {\ - 2,\ - { MVHW_CP0_PP2_BASE, MVHW_CP1_PP2_BASE },\ - { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \ -} - #endif /* __MVHWDESCLIB_H__ */ --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:54 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22f; helo=mail-lf0-x22f.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lil8E2mhO+3juyZ8qbqziJG5F4bapwLgmC6oEEw02M8=; b=0K0fSCmtRtPwSbiNvYyUYOE3J+kiWDPttMcVG1UfflwIQ/yfbuJ1qJORR0HkBUcFHy 056aRIyVgCOGyoomxoPZDLOLIJwe+G++Ow0+mYAUi1qOko/aRwt9Ujqz3v4ev7yiipnb dMdrebE0qUKVzgltBDwvkn4KH+tMkpeahSfrYGj043Msk7Ty8w9n5QHE6DQReDrCPVK+ sSt9unWexWLy+EsLrbVaBYWzyZPgPtd3P6E4xflSRNquN8Ha3CAWT/EBszZU/opfhwoM R/fej6WJSLTNxB3jL7JelR3lswK6wcKR75ZsSp1YEjOfK1EigSkEZe9ymQ7jxt7PLcTJ HCUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lil8E2mhO+3juyZ8qbqziJG5F4bapwLgmC6oEEw02M8=; b=R5RadH1OI8vqBk452vhLVFlDVHjTCU1QRjFJj84wm5I9/y50W/ZaRNIf3wKmzUFCOJ qLmlL+L/Zqmw1p0I+IL1OAX/PpUBvp8U1pVc83eo1vk04JGavyGM5Xy22142kXcUSt7R bsiO0czWAJySvASB+VDIGjMMG2lwXkCw2yPAGFhNtv5kR6vugC9waaUIjaVZHO1GNK15 7vp7SF91qU684KD10vEoBCz8dZjQ4IUFOQXqy3W309M85Eh49O9mYBWLHgy9AeJBHFpE ruxiTqkE3xmSyfhPZ3rItwqtD3B0Qa+4c2vC6Qqtx6BB9PLvthlpT2cMan39Wm1KXcnf s2Sg== X-Gm-Message-State: APt69E0xQtNssZEad/CdVQLPSsIr5R0ctrTLiPbmin5D4XDEfcgpQ6cr y0mOHsYuV0VqvRAI2YuNaNRbztseing= X-Google-Smtp-Source: ADUXVKJPM39DB/7F63mAxXaW2/DkW93YM/Y/0iq+DfF5XPXwJcFe0iC1bhdbEOUZNM8UtbiLBleA7A== X-Received: by 2002:a2e:6f02:: with SMTP id k2-v6mr4952743ljc.72.1528472095173; Fri, 08 Jun 2018 08:34:55 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:09 +0200 Message-Id: <1528472063-1660-12-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 11/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callbacks for NonDiscoverable devices i.e. AHCI/XHCI/SDMMC. They dynamically allocate and fill according structures with the SoC description of the devices. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 114 ++++++++++++++++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 48 +++++++++ 2 files changed, 162 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 36b445e..de57b47 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -32,6 +32,120 @@ #define MV_SOC_CP_BASE(Cp) (0xF2000000 + (Cp) * 0x2000000) =20 // +// Platform description of NonDiscoverableDevices +// + +// +// Platform description of AHCI controllers +// +#define MV_SOC_AHCI_BASE(Cp) MV_SOC_CP_BASE ((Cp)) + 0x540000 +#define MV_SOC_AHCI_ID(Cp) ((Cp) % 2) + +EFI_STATUS +EFIAPI +ArmadaSoCDescAhciGet ( + IN OUT MV_SOC_AHCI_DESC **AhciDesc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_AHCI_DESC *Desc; + UINT8 CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + UINT8 CpIndex; + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_AHCI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].AhciId =3D MV_SOC_AHCI_ID (CpIndex); + Desc[CpIndex].AhciBaseAddress =3D MV_SOC_AHCI_BASE (CpIndex); + Desc[CpIndex].AhciMemSize =3D SIZE_8KB; + Desc[CpIndex].AhciDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + } + + *AhciDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +// +// Platform description of SDMMC controllers +// +#define MV_SOC_MAX_SDMMC_COUNT 2 +#define MV_SOC_SDMMC_BASE(Index) ((Index) =3D=3D 0 ? 0xF06E0000 : 0xF278= 0000) + +EFI_STATUS +EFIAPI +ArmadaSoCDescSdMmcGet ( + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_SDMMC_DESC *Desc; + UINT8 Index; + + Desc =3D AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC= _DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) { + Desc[Index].SdMmcBaseAddress =3D MV_SOC_SDMMC_BASE (Index); + Desc[Index].SdMmcMemSize =3D SIZE_1KB; + Desc[Index].SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + } + + *SdMmcDesc =3D Desc; + *DescCount =3D MV_SOC_MAX_SDMMC_COUNT; + + return EFI_SUCCESS; +} + +// +// Platform description of XHCI controllers +// +#define MV_SOC_XHCI_PER_CP_COUNT 2 +#define MV_SOC_XHCI_BASE(Xhci) (0x500000 + (Xhci) * 0x10000) + +EFI_STATUS +EFIAPI +ArmadaSoCDescXhciGet ( + IN OUT MV_SOC_XHCI_DESC **XhciDesc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_XHCI_DESC *Desc; + UINT8 CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + UINT8 Index, CpIndex, XhciIndex =3D 0; + + Desc =3D AllocateZeroPool (CpCount * MV_SOC_XHCI_PER_CP_COUNT * + sizeof (MV_SOC_XHCI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_XHCI_PER_CP_COUNT; Index++) { + Desc[XhciIndex].XhciBaseAddress =3D + MV_SOC_CP_BASE (CpIndex) + MV_SOC_XHCI_BASE (Inde= x); + Desc[XhciIndex].XhciMemSize =3D SIZE_16KB; + Desc[XhciIndex].XhciDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + XhciIndex++; + } + } + + *XhciDesc =3D Desc; + *DescCount =3D XhciIndex; + + return EFI_SUCCESS; +} + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE ((Cp)) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 559642b..438f838 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -14,6 +14,54 @@ #ifndef __ARMADA_SOC_DESC_LIB_H__ #define __ARMADA_SOC_DESC_LIB_H__ =20 +#include + +// +// NonDiscoverable devices SoC description +// +// AHCI +typedef struct { + UINT8 AhciId; + UINTN AhciBaseAddress; + UINTN AhciMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType; +} MV_SOC_AHCI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescAhciGet ( + IN OUT MV_SOC_AHCI_DESC **AhciDesc, + IN OUT UINT8 *DescCount + ); + +// SDMMC +typedef struct { + UINTN SdMmcBaseAddress; + UINTN SdMmcMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE SdMmcDmaType; +} MV_SOC_SDMMC_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescSdMmcGet ( + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, + IN OUT UINT8 *DescCount + ); + +// XHCI +typedef struct { + UINTN XhciBaseAddress; + UINTN XhciMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType; +} MV_SOC_XHCI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescXhciGet ( + IN OUT MV_SOC_XHCI_DESC **XhciDesc, + IN OUT UINT8 *DescCount + ); + // // PP2 NIC devices SoC description // --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472137295129.37757201110242; Fri, 8 Jun 2018 08:35:37 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2BC0D2111002D; Fri, 8 Jun 2018 08:35:00 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 603132110A00B for ; Fri, 8 Jun 2018 08:34:58 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id 36-v6so20678298lfr.11 for ; Fri, 08 Jun 2018 08:34:58 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:55 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QWeNHRFTjDIlZ+55j7RSixIGSaaGhtSUtsP5IFNT+PU=; b=SJTU3lwEQlMdhqtJpLgnom4jERNJ7EAufhONMxcRX48UwzNrbCONvp6chp3CzDvJMJ eVLUvBlpqmaJV0+DUh3jD46z5QuFVI3QtjArbB15X+MTdvj9jQgpVHZsiJkLTJp/K1Ya bnHLCrLMPbpbGkKA72IeSjTcakA3ToZ9zpgD2Ow/FVp1ZeMKSuM+DJxBec3n1l72nEGV bsiZBjePmc7iPfrwwcmSbbxfLJNvt2zDyhZ2GDydjR77UOyOiJeQm8eggR+cTumK0O3c NqM49iALzGUVVRPO1xWJ8pYdJqQDDlRi9pIfwesjjQQDDBx04v9gFPHb5b/NynShoWiY vTSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QWeNHRFTjDIlZ+55j7RSixIGSaaGhtSUtsP5IFNT+PU=; b=eY/iH+blaFbRZumknkiBDN+cVEyygpIyd/ltgf/HRRboy7r/fTFZWBIGCd1p+AlJVA nCXrsospBp0x58KlwFAW+l1rP6reDb785EUtUIPua9Nu1ztedjfglfW0jye2N3jOv+mL rsd9NXo0ExYiy3PGXjVaCuXJ9ZBLC208WjMeNcC3rRYNvXnr70IRLWGx31eRzL3XGAA9 I5PWZLPxDssmHONJcVZVIhgqLeYvkP6S/EBG3LUdW1CUNF+YYIRCTuYyix1evVEWq/Pj AU/NUp26jOvbrmQMDnMrobDwdIQGLe/RVYVEAktGpf6gfybGKDDTcFPm7TYoHZnyZJSn bP4A== X-Gm-Message-State: APt69E3rFWxOJ4byF6vrbH/at1CHdMY3yJqlJHEc0st+6jZ2w9TFnWNe lPjQirbczDKNQXyaT3gFOt3AOQy6zxs= X-Google-Smtp-Source: ADUXVKIU2x/dpWJ84CwucQQiQUcyrcVGYQnmPOL1XNEcU8xM6xEJyujNWJJnrWK/FcGK1pKM8lYgSw== X-Received: by 2002:a2e:28b:: with SMTP id y11-v6mr4810065lje.27.1528472096389; Fri, 08 Jun 2018 08:34:56 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:10 +0200 Message-Id: <1528472063-1660-13-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 12/25] Marvell/Drivers: MvBoardDesc: Extend protocol with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about NonDiscoverableDevices to the relevant drivers and libraries. Extend ArmadaBoardDescLib with new structures (MV_BOARD_AHCI_DESC/ MV_BOARD_SDMMC_DESC/MV_BOARD_XHCI_DESC) for holding board specific data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 180 +++++++++++++++= +++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 2 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 31 ++++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 24 +++ 4 files changed, 237 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 86bddad..44d159e 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,183 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescAhciGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_AHCI_DESC **AhciDesc + ) +{ + UINT8 *AhciDeviceTable, AhciCount; + UINTN AhciDeviceTableSize, AhciIndex, Index; + MV_BOARD_AHCI_DESC *BoardDesc; + MV_SOC_AHCI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available AHCI controllers */ + Status =3D ArmadaSoCDescAhciGet (&SoCDesc, &AhciCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled AHCI controllers */ + AhciDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciEAhci); + if (AhciDeviceTable =3D=3D NULL) { + /* No AHCI on platform */ + return EFI_SUCCESS; + } + + AhciDeviceTableSize =3D PcdGetSize (PcdPciEAhci); + + /* Check if PCD with AHCI controllers is correctly defined */ + if (AhciDeviceTableSize > AhciCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEAhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (AhciDeviceTableSize * sizeof (MV_BOARD_A= HCI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + AhciIndex =3D 0; + for (Index =3D 0; Index < AhciDeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (Ahci, Index)) { + DEBUG ((DEBUG_INFO, "%a: Skip Ahci controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[AhciIndex].SoC =3D &SoCDesc[Index]; + AhciIndex++; + } + + BoardDesc->AhciDevCount =3D AhciIndex; + + *AhciDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvBoardDescSdMmcGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + UINT8 *SdMmcDeviceTable, SdMmcCount; + UINTN SdMmcDeviceTableSize, SdMmcIndex, Index; + MV_BOARD_SDMMC_DESC *BoardDesc; + MV_SOC_SDMMC_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available SDMMC controllers */ + Status =3D ArmadaSoCDescSdMmcGet (&SoCDesc, &SdMmcCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled SDMMC controllers */ + SdMmcDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciESdhci); + if (SdMmcDeviceTable =3D=3D NULL) { + /* No SDMMC on platform */ + return EFI_SUCCESS; + } + + SdMmcDeviceTableSize =3D PcdGetSize (PcdPciESdhci); + + /* Check if PCD with SDMMC controllers is correctly defined */ + if (SdMmcDeviceTableSize > SdMmcCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciESdhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (SdMmcDeviceTableSize * sizeof (MV_BOARD_= SDMMC_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + SdMmcIndex =3D 0; + for (Index =3D 0; Index < SdMmcDeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (SdMmc, Index)) { + DEBUG ((DEBUG_INFO, "%a: Skip SdMmc controller %d\n", __FUNCTION__, = Index)); + continue; + } + + BoardDesc[SdMmcIndex].SoC =3D &SoCDesc[Index]; + SdMmcIndex++; + } + + BoardDesc->SdMmcDevCount =3D SdMmcIndex; + + *SdMmcDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvBoardDescXhciGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_XHCI_DESC **XhciDesc + ) +{ + UINT8 *XhciDeviceTable, XhciCount; + UINTN XhciDeviceTableSize, XhciIndex, Index; + MV_BOARD_XHCI_DESC *BoardDesc; + MV_SOC_XHCI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available XHCI controllers */ + Status =3D ArmadaSoCDescXhciGet (&SoCDesc, &XhciCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled XHCI controllers */ + XhciDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciEXhci); + if (XhciDeviceTable =3D=3D NULL) { + /* No XHCI on platform */ + return EFI_SUCCESS; + } + + XhciDeviceTableSize =3D PcdGetSize (PcdPciEXhci); + + /* Check if PCD with XHCI controllers is correctly defined */ + if (XhciDeviceTableSize > XhciCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEXhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (XhciDeviceTableSize * sizeof (MV_BOARD_X= HCI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + XhciIndex =3D 0; + for (Index =3D 0; Index < XhciDeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (Xhci, Index)) { + DEBUG ((DEBUG_INFO, "%a: Skip Xhci controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[XhciIndex].SoC =3D &SoCDesc[Index]; + XhciIndex++; + } + + BoardDesc->XhciDevCount =3D XhciIndex; + + *XhciDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescPp2Get ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_PP2_DESC **Pp2Desc @@ -197,6 +374,9 @@ MvBoardDescInitProtocol ( IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol ) { + BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; + BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; + BoardDescProtocol->BoardDescXhciGet =3D MvBoardDescXhciGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index c7d5fe2..fe819ac 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -60,6 +60,8 @@ gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled gMarvellTokenSpaceGuid.PcdUtmiPortType + gMarvellTokenSpaceGuid.PcdPciEAhci + gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdPciEXhci =20 [Depex] diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 78cf698..938d283 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,37 @@ #include =20 // +// NonDiscoverableDevices per-board description +// + +// +// AHCI devices per-board description +// +typedef struct { + MV_SOC_AHCI_DESC *SoC; + UINT8 AhciDevCount; +} MV_BOARD_AHCI_DESC; + +// +// SDMMC devices per-board description +// +// TODO - Extend structure with entire +// ports description instead of PCDs. +// +typedef struct { + MV_SOC_SDMMC_DESC *SoC; + UINT8 SdMmcDevCount; +} MV_BOARD_SDMMC_DESC; + +// +// XHCI devices per-board description +// +typedef struct { + MV_SOC_XHCI_DESC *SoC; + UINT8 XhciDevCount; +} MV_BOARD_XHCI_DESC; + +// // PP2 NIC devices per-board description // // TODO - Extend structure with entire diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index 114a0ec..a59ade5 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,27 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_AHCI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_AHCI_DESC **AhciDesc + ); + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_SDMMC_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ); + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_XHCI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_XHCI_DESC **XhciDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_PP2_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_PP2_DESC **Pp2Desc @@ -62,6 +83,9 @@ VOID ); =20 struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; + MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; + MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; MV_BOARD_DESC_FREE BoardDescFree; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472142305656.3829137895709; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:56 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GQXzZGMR7kkbEMn0LDrc47fFNhNytUzL7COLwHMdMHk=; b=dyh0C14yegxz7QAUHaeJtRnkVlohh6shnRF3OZS7nj8V+GmanWKHKx/sCVqvqY4el4 qM3GLlWfZEWxg/hN4XRoU54d1GB1koLvuRL54Pbh1J8Fnni8FbgNe0KVN7ZVhzZlNQzx BeJbN+NjXbhkVba+A7MJK+2NhPNhp3FwFKq18A6EStXA9lFtIE8fET/C0UOuFHsIU6aZ KvbbaA7SAPt9dg8xlPC/NbEqU4Pc/O+QCDJQ8x0H1F6gfO8yu11XYgz2ZoGrpKl8e/s5 m+8sl+dKmeYkWUMkdXLV0HbUkdWQgM8/n1XTmNENzivlprKvOXVsD7jfN7PA3uRCoShp j84g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GQXzZGMR7kkbEMn0LDrc47fFNhNytUzL7COLwHMdMHk=; b=a/5sTlHG+ZjEuH8YPA8qrWVwoK66R3GVYZuaPrr2a9QkX7u2SaMIXX6jfGTpQydY+z uUJir3wKb3QDQP+u3PVJrAxNCEN0KdyfDJVasXvQQBG2MgdRMvwVLzqAw1fFg1WPp0tP ZOs59mb2jdggsc39EfJT1HN4TH3vOrTiofHWwUaQu7YY2ljdkg4Uib5csJNYyh7+tBwe HNHqWI7gQVRHyXO5WeV2FTFFELTyx2tdBFjZEGgbngkH8c0WAarxNOCzHjn+mPIio717 vJaeLp+T8ybjmFxgpkQyfMl987vuPAKHqscYFLqVTefy0CvQE0oBi+MaZE3KSXJIUNQ/ 2XXw== X-Gm-Message-State: APt69E2bIK6e72aHuGC/Scm6OYhiKfdC7yNWDTyUXSDxzgFt4pv8Migb vtmTVVbdleLo/GMS4r27WFFcODAM1NU= X-Google-Smtp-Source: ADUXVKIeWC2cfS1ZKm7ad+QV1SX7nEVJbpumVUTR09J/EcOjJf+B4ACRitneS/3DHTsMEFx3NxeEXw== X-Received: by 2002:a2e:2b1b:: with SMTP id q27-v6mr4800490lje.145.1528472097789; Fri, 08 Jun 2018 08:34:57 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:11 +0200 Message-Id: <1528472063-1660-14-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 13/25] Marvell/Drivers: NonDiscoverable: Switch to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" NonDiscoverableDevices driver used to get Armada7k8k AHCI/SDMMC/XHCI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get AHCI/SDMMC/XHCI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c | 100 ++= ++++++++---------- Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf | 6 +- 2 files changed, 52 insertions(+), 54 deletions(-) diff --git a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.= c b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c index 6ff90a5..c5cf904 100644 --- a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c +++ b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c @@ -35,50 +35,33 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include =20 #include -#include #include #include =20 +#include #include =20 -DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; - -// -// Tables with used devices -// -STATIC UINT8 * CONST XhciDeviceTable =3D FixedPcdGetPtr (PcdPciEXhci); -STATIC UINT8 * CONST AhciDeviceTable =3D FixedPcdGetPtr (PcdPciEAhci); -STATIC UINT8 * CONST SdhciDeviceTable =3D FixedPcdGetPtr (PcdPciESdhci); - // // NonDiscoverable devices registration // STATIC EFI_STATUS NonDiscoverableInitXhci ( + IN MV_BOARD_XHCI_DESC *Desc ) { - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_STATUS Status; UINT8 i; =20 - if (PcdGetSize (PcdPciEXhci) < Desc->XhciDevCount) { - DEBUG((DEBUG_ERROR, "NonDiscoverable: Wrong PcdPciEXhci format\n")); - return EFI_INVALID_PARAMETER; - } - for (i =3D 0; i < Desc->XhciDevCount; i++) { - if (!MVHW_DEV_ENABLED (Xhci, i)) { - continue; - } - Status =3D RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeXhci, - Desc->XhciDmaType[i], + Desc[i].SoC->XhciDmaType, NULL, NULL, 1, - Desc->XhciBaseAddresses[i], Desc->XhciMemSize[i] + Desc[i].SoC->XhciBaseAddress, + Desc[i].SoC->XhciMemSize ); =20 if (EFI_ERROR(Status)) { @@ -93,29 +76,21 @@ NonDiscoverableInitXhci ( STATIC EFI_STATUS NonDiscoverableInitAhci ( + IN MV_BOARD_AHCI_DESC *Desc ) { - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_STATUS Status; UINT8 i; =20 - if (PcdGetSize (PcdPciEAhci) < Desc->AhciDevCount) { - DEBUG((DEBUG_ERROR, "NonDiscoverable: Wrong PcdPciEAhci format\n")); - return EFI_INVALID_PARAMETER; - } - for (i =3D 0; i < Desc->AhciDevCount; i++) { - if (!MVHW_DEV_ENABLED (Ahci, i)) { - continue; - } - Status =3D RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeAhci, - Desc->AhciDmaType[i], + Desc[i].SoC->AhciDmaType, NULL, NULL, 1, - Desc->AhciBaseAddresses[i], Desc->AhciMemSize[i] + Desc[i].SoC->AhciBaseAddress, + Desc[i].SoC->AhciMemSize ); =20 if (EFI_ERROR(Status)) { @@ -130,29 +105,21 @@ NonDiscoverableInitAhci ( STATIC EFI_STATUS NonDiscoverableInitSdhci ( + IN MV_BOARD_SDMMC_DESC *Desc ) { - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_STATUS Status; UINT8 i; =20 - if (PcdGetSize (PcdPciESdhci) < Desc->SdhciDevCount) { - DEBUG((DEBUG_ERROR, "NonDiscoverable: Wrong PcdPciESdhci format\n")); - return EFI_INVALID_PARAMETER; - } - - for (i =3D 0; i < Desc->SdhciDevCount; i++) { - if (!MVHW_DEV_ENABLED (Sdhci, i)) { - continue; - } - + for (i =3D 0; i < Desc->SdMmcDevCount; i++) { Status =3D RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeSdhci, - Desc->SdhciDmaType[i], + Desc[i].SoC->SdMmcDmaType, NULL, NULL, 1, - Desc->SdhciBaseAddresses[i], Desc->SdhciMemSize[i] + Desc[i].SoC->SdMmcBaseAddress, + Desc[i].SoC->SdMmcMemSize ); =20 if (EFI_ERROR(Status)) { @@ -174,22 +141,55 @@ NonDiscoverableEntryPoint ( IN EFI_SYSTEM_TABLE *SystemTable ) { + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_SDMMC_DESC *SdMmcBoardDesc; + MV_BOARD_AHCI_DESC *AhciBoardDesc; + MV_BOARD_XHCI_DESC *XhciBoardDesc; EFI_STATUS Status; =20 - Status =3D NonDiscoverableInitXhci(); + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Xhci */ + Status =3D BoardDescProtocol->BoardDescXhciGet (BoardDescProtocol, + &XhciBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D NonDiscoverableInitXhci (XhciBoardDesc); if (EFI_ERROR(Status)) { return Status; } + BoardDescProtocol->BoardDescFree (XhciBoardDesc); =20 - Status =3D NonDiscoverableInitAhci(); + /* Ahci */ + Status =3D BoardDescProtocol->BoardDescAhciGet (BoardDescProtocol, + &AhciBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D NonDiscoverableInitAhci (AhciBoardDesc); if (EFI_ERROR(Status)) { return Status; } + BoardDescProtocol->BoardDescFree (AhciBoardDesc); =20 - Status =3D NonDiscoverableInitSdhci(); + /* SdMmc */ + Status =3D BoardDescProtocol->BoardDescSdMmcGet (BoardDescProtocol, + &SdMmcBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D NonDiscoverableInitSdhci (SdMmcBoardDesc); if (EFI_ERROR(Status)) { return Status; } + BoardDescProtocol->BoardDescFree (SdMmcBoardDesc); =20 return EFI_SUCCESS; } diff --git a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.= inf b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf index b62b3fb..98e5b0c 100644 --- a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf +++ b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf @@ -52,10 +52,8 @@ NonDiscoverableDeviceRegistrationLib UefiDriverEntryPoint =20 -[Pcd] - gMarvellTokenSpaceGuid.PcdPciEAhci - gMarvellTokenSpaceGuid.PcdPciESdhci - gMarvellTokenSpaceGuid.PcdPciEXhci +[Protocols] + gMarvellBoardDescProtocolGuid =20 [Depex] TRUE --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:58 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ltdmB5euxu8ETubWsE4FyYvrI8fw+ZYI/DVSNa/+A18=; b=zlt5OyYdTdIWBWEtN5GotuSvozArYoyZlUehbbVFMkPk8NUvYIjSsl5tLOo58eYa7h LkECmGSQoNICFOhwWkd2KT5MzBbfjip68Pd0kudVl4j+1XmdcTPxY76Mgh+FH4uaOK02 NZBkrgNwf9rQW8N74UxR+MNTa5jpjUMcn2JvS0vrgJ4EDc1U4grQ6LfTbCCKUcUhlKQc Bnr14+sODTRq0QyAIuxR1oZImMVFMarH6qaZeYCnEZcfycFl6C8dd5utO7f9UfpBiNvi r+Wrtd4jep9O6XBT3Lu3EpdNBAOKqORc5q0tEVrAmIQ5R5eLW+TzzNLPmwSLJBOoj43y AO3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ltdmB5euxu8ETubWsE4FyYvrI8fw+ZYI/DVSNa/+A18=; b=Hmr6YSVZ3QF9KF/Gd5zv7hVwu0tGsdxXpppuirF22RhLQII0Yi353admRaMhJKAoGC HawlfAq4aay01IPHCCTulaOmtMtQXo/Em/+D5JYHavKcWjMJvGwtbTDFRXQ0FOCELhB3 SvOmwx/XcYvtGMFXcxy0TImc9tb7ZRjtBvxcGZQL3FY21xXwW1DkKQOZTMssFaQAn3Gw RGZJI16tqFN85Sb71zSyybOdEiP+NQk8+6VIT9y/z415YgRdFzC4lHiPr5zhr2A8xqHo 4mQUDu5oBgCmUHSHuRG/JmsbmqDb+tSKN9VTMwyThGb3rIUP6MReYRtMpKDsqosM3MSq 6D9Q== X-Gm-Message-State: APt69E21ydYavlkWVcWXWvps4E3Uyw2JaVvJKLojHXkHZjjisUTZ+xXl QLA4NUK0yU+Vf7klTKFObSqJLg8AjXA= X-Google-Smtp-Source: ADUXVKL0Xi4BkXZAhk7PngQ1fUr7IWrMvP/sYkVlZTlF3Vqre6lNZwYiKAegnn+5V3BiOTOlVTKOSg== X-Received: by 2002:a2e:1945:: with SMTP id p66-v6mr4841011lje.114.1528472098973; Fri, 08 Jun 2018 08:34:58 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:12 +0200 Message-Id: <1528472063-1660-15-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 14/25] Marvell/Library: ComPhyLib: Get AHCI data with MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" ComPhy Library used to get Armada7k8k AHCI/SDMMC/XHCI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this library. This patch updates the driver to get AHCI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 - Silicon/Marvell/Include/Library/MvHwDescLib.h | 60 --= ------------------ Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 50 ++= ++++++-------- Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 4 ++ Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 6 +- 5 files changed, 35 insertions(+), 86 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index f2c173c..e888566 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -47,7 +47,6 @@ =20 [LibraryClasses] ArmLib - ComPhyLib DebugLib MemoryAllocationLib MppLib diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 5fd514c..9f383f4 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -36,7 +36,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define __MVHWDESCLIB_H__ =20 #include -#include =20 // // Helper macros @@ -80,31 +79,6 @@ typedef struct { } MVHW_MDIO_DESC; =20 // -// NonDiscoverable devices description template definition -// -#define MVHW_MAX_XHCI_DEVS 4 -#define MVHW_MAX_AHCI_DEVS 4 -#define MVHW_MAX_SDHCI_DEVS 4 - -typedef struct { - // XHCI - UINT8 XhciDevCount; - UINTN XhciBaseAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN XhciMemSize[MVHW_MAX_XHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType[MVHW_MAX_XHCI_DEVS]; - // AHCI - UINT8 AhciDevCount; - UINTN AhciBaseAddresses[MVHW_MAX_AHCI_DEVS]; - UINTN AhciMemSize[MVHW_MAX_AHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType[MVHW_MAX_AHCI_DEVS]; - // SDHCI - UINT8 SdhciDevCount; - UINTN SdhciBaseAddresses[MVHW_MAX_SDHCI_DEVS]; - UINTN SdhciMemSize[MVHW_MAX_SDHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE SdhciDmaType[MVHW_MAX_SDHCI_DEVS]; -} MVHW_NONDISCOVERABLE_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -155,38 +129,4 @@ MVHW_MDIO_DESC mA7k8kMdioDescTemplate =3D {\ { MVHW_CP0_MDIO_BASE, MVHW_CP1_MDIO_BASE }\ } =20 -// -// Platform description of NonDiscoverable devices -// -#define MVHW_CP0_XHCI0_BASE 0xF2500000 -#define MVHW_CP0_XHCI1_BASE 0xF2510000 -#define MVHW_CP1_XHCI0_BASE 0xF4500000 -#define MVHW_CP1_XHCI1_BASE 0xF4510000 - -#define MVHW_CP0_AHCI0_BASE 0xF2540000 -#define MVHW_CP0_AHCI0_ID 0 -#define MVHW_CP1_AHCI0_BASE 0xF4540000 -#define MVHW_CP1_AHCI0_ID 1 - -#define MVHW_AP0_SDHCI0_BASE 0xF06E0000 -#define MVHW_CP0_SDHCI0_BASE 0xF2780000 - -#define DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE \ -STATIC \ -MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTemplate =3D {\ - 4, /* XHCI */\ - { MVHW_CP0_XHCI0_BASE, MVHW_CP0_XHCI1_BASE, MVHW_CP1_XHCI0_BASE, MVHW_CP= 1_XHCI1_BASE },\ - { SIZE_16KB, SIZE_16KB, SIZE_16KB, SIZE_16KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent,\ - NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent },\ - 2, /* AHCI */\ - { MVHW_CP0_AHCI0_BASE, MVHW_CP1_AHCI0_BASE },\ - { SIZE_8KB, SIZE_8KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent },\ - 2, /* SDHCI */\ - { MVHW_AP0_SDHCI0_BASE, MVHW_CP0_SDHCI0_BASE },\ - { SIZE_1KB, SIZE_1KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyCp110.c index 09994ca..3c696fb 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -33,7 +33,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. **************************************************************************= *****/ =20 #include "ComPhyLib.h" -#include #include =20 #define SD_LANE_ADDR_WIDTH 0x1000 @@ -46,8 +45,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CP110_PCIE_REF_CLK_TYPE0 0 #define CP110_PCIE_REF_CLK_TYPE12 1 =20 -DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; - /* * For CP-110 we have 2 Selector registers "PHY Selectors" * and " PIPE Selectors". @@ -1138,36 +1135,23 @@ ComPhySataCheckPll ( STATIC UINTN ComPhySataPowerUp ( + IN UINT8 ChipId, IN UINT32 Lane, IN EFI_PHYSICAL_ADDRESS HpipeBase, IN EFI_PHYSICAL_ADDRESS ComPhyBase, - IN UINT8 SataHostId + IN MV_BOARD_AHCI_DESC *Desc ) { EFI_STATUS Status; - UINT8 *SataDeviceTable; - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); EFI_PHYSICAL_ADDRESS SdIpAddr =3D SD_ADDR(HpipeBase, Lane); EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); =20 - SataDeviceTable =3D (UINT8 *) PcdGetPtr (PcdPciEAhci); - - if (SataDeviceTable =3D=3D NULL || SataHostId >=3D PcdGetSize (PcdPciEAh= ci)) { - DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is undefined\n", SataHo= stId)); - return EFI_INVALID_PARAMETER; - } - - if (!MVHW_DEV_ENABLED (Sata, SataHostId)) { - DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is disabled\n", SataHos= tId)); - return EFI_INVALID_PARAMETER; - } - DEBUG ((DEBUG_INFO, "ComPhySata: Initialize SATA PHYs\n")); =20 DEBUG((DEBUG_INFO, "ComPhySataPowerUp: stage: MAC configuration - power = down ComPhy\n")); =20 - ComPhySataMacPowerDown (Desc->AhciBaseAddresses[SataHostId]); + ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPh= y\n")); =20 @@ -1183,7 +1167,7 @@ ComPhySataPowerUp ( =20 DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); =20 - ComPhySataPhyPowerUp (Desc->AhciBaseAddresses[SataHostId]); + ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); =20 @@ -1884,6 +1868,8 @@ ComPhyCp110Init ( EFI_STATUS Status; COMPHY_MAP *PtrComPhyMap, *SerdesMap; EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_AHCI_DESC *AhciBoardDesc; UINT32 ComPhyMaxCount, Lane; UINT32 PcieWidth =3D 0; UINT8 ChipId; @@ -1927,11 +1913,29 @@ ComPhyCp110Init ( break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: - Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP0_AHCI0_ID); - break; case COMPHY_TYPE_SATA2: case COMPHY_TYPE_SATA3: - Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP1_AHCI0_ID); + /* Obtain AHCI board description */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D BoardDescProtocol->BoardDescAhciGet (BoardDescProtocol, + &AhciBoardDesc); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D ComPhySataPowerUp (ChipId, + Lane, + HpipeBaseAddr, + ComPhyBaseAddr, + AhciBoardDesc); + + BoardDescProtocol->BoardDescFree (AhciBoardDesc); break; case COMPHY_TYPE_USB3_HOST0: case COMPHY_TYPE_USB3_HOST1: diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.h index c675d74..090116d 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -35,6 +35,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __COMPHY_H__ #define __COMPHY_H__ =20 +#include #include #include #include @@ -43,6 +44,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include + +#include =20 #define MAX_LANE_OPTIONS 10 =20 diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyLib.inf index ce0af54..f36c701 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -52,12 +52,16 @@ PcdLib SampleAtResetLib IoLib + UefiBootServicesTableLib =20 [Sources.common] ComPhyLib.c ComPhyCp110.c ComPhyMux.c =20 +[Protocols] + gMarvellBoardDescProtocolGuid ## CONSUMES + [FixedPcd] gMarvellTokenSpaceGuid.PcdComPhyDevices =20 @@ -80,5 +84,3 @@ gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags - - gMarvellTokenSpaceGuid.PcdPciEAhci --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:59 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E/5a8Bl44AMufda52KG17v0a1dv+h8J5RRS4UOPMH6w=; b=EdlS+9XhJnAPYdTLCfFVc5pRSTM7gCyowLnqQu7xDuefXSneIxbYO5VicsfMoC3YTo Bcw1r0fVKslZ1saLHxZr6+soXI1U5DjFn0QwXPlu36cY8AQjpuOd9VGBavfFr9AAqsLw yUdCE723JgCULY1ubIF6ftvbwEMFfKVdc911GvGEmK4112E1gFwumlrHPd6tILmr6+ev qVR5hRVh2MSQw1NyBp77pRKzXyzbENz7zZNq3O170l2BZIX0iMW6U60B3f8MfhcBmxU3 FDcqtMMq50D2K0OB2DMk94GlOkUYWaAPScNWpj//HqQbGiaoqliJi/ASMrmhzfW37Hs7 R8cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E/5a8Bl44AMufda52KG17v0a1dv+h8J5RRS4UOPMH6w=; b=b02S1H1Uogaz3e3Tz2KnCnrKBe9l3vYn/yeknfqK8nD1tIcUIpUFbcv1oTTWm037nv PVbpLhQOz50qyQTxwPE6NXZHweNDKAipsuoLvnSIClwqXBl1F0eJUNe+QgQHuDARj3rZ 9x6AAjoFAX+GCqklULUgDKhdbWJEH/r+ic98N/bJiMw1OugLMoYkSI19mB+RLCsXc2/3 sf4Nrn5RmEgfoGuLHQDgHirarjQA41KznpLA4/B6bUmuh6+qCeGmIxaCPJk2OgZtcpku Sm9NSl+JL+SmlhNOXzydxTJVJc63McM6Kk8Y6Z37zrt2IHAFg2G9Bh3p7vfB9l8AT9B8 lR2w== X-Gm-Message-State: APt69E3rXnqsgFmgN7UuxvtPH/Sf+1mkWgdLsUfTNKv8vljWe1yKWh82 kivVtFsKnAzCQQto1p6jyTSrehaM4AA= X-Google-Smtp-Source: ADUXVKIDoC1PFMIhYoenfNnhy9lRoiFEc2GBYH6dhNvAjg4DXnIg3jGHDhB0rPU0q29kB4157dggDg== X-Received: by 2002:a2e:8151:: with SMTP id t17-v6mr4894704ljg.32.1528472100215; Fri, 08 Jun 2018 08:35:00 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:13 +0200 Message-Id: <1528472063-1660-16-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 15/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with ComPhy information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescComPhyGet ()), which dynamically allocates and fills MV_SOC_COMPHY_DESC structure with the SoC description of ComPhy SerDes controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 40 ++++++++++++++++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 20 ++++++++++ 2 files changed, 60 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index de57b47..ba44a0c 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -32,6 +32,46 @@ #define MV_SOC_CP_BASE(Cp) (0xF2000000 + (Cp) * 0x2000000) =20 // +// Platform description of ComPhy controllers +// +#define MV_SOC_COMPHY_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x441000) +#define MV_SOC_HPIPE3_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x120000) +#define MV_SOC_COMPHY_LANE_COUNT 6 +#define MV_SOC_COMPHY_MUX_BITS 4 + +EFI_STATUS +EFIAPI +ArmadaSoCDescComPhyGet ( + IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_COMPHY_DESC *Desc; + UINT8 CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + UINT8 CpIndex; + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_COMPHY_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].ComPhyBaseAddress =3D MV_SOC_COMPHY_BASE (CpIndex); + Desc[CpIndex].ComPhyHpipe3BaseAddress =3D MV_SOC_HPIPE3_BASE (CpIndex); + Desc[CpIndex].ComPhyLaneCount =3D MV_SOC_COMPHY_LANE_COUNT; + Desc[CpIndex].ComPhyMuxBitCount =3D MV_SOC_COMPHY_MUX_BITS; + Desc[CpIndex].ComPhyChipType =3D MvComPhyTypeCp110; + Desc[CpIndex].ComPhyId =3D CpIndex; + } + + *ComPhyDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +// // Platform description of NonDiscoverableDevices // =20 diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 438f838..791d58b 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -14,9 +14,29 @@ #ifndef __ARMADA_SOC_DESC_LIB_H__ #define __ARMADA_SOC_DESC_LIB_H__ =20 +#include #include =20 // +// ComPhy SoC description +// +typedef struct { + UINTN ComPhyId; + UINTN ComPhyBaseAddress; + UINTN ComPhyHpipe3BaseAddress; + UINTN ComPhyLaneCount; + UINTN ComPhyMuxBitCount; + MV_COMPHY_CHIP_TYPE ComPhyChipType; +} MV_SOC_COMPHY_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescComPhyGet ( + IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc, + IN OUT UINT8 *DescCount + ); + +// // NonDiscoverable devices SoC description // // AHCI --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472158481348.3214604802331; Fri, 8 Jun 2018 08:35:58 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E70EA2112388A; Fri, 8 Jun 2018 08:35:05 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6B75D21110029 for ; Fri, 8 Jun 2018 08:35:03 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id j13-v6so20697562lfb.13 for ; Fri, 08 Jun 2018 08:35:03 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:00 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SqjAQ4x0JHruDRSlJSVWOW//5VauAbIThz5/XephUL4=; b=0XQX9/P3c8z8aatOuGebstodtuhwT9ryp17ozfIJ7LVzkvSzBQYl5cg1ycceNsNxka h0D2BAHg2q8OJn1efVPZXsJw8k8rODjbrDX1EkkXf2tUiO2rQQoeflWsX/8yEAXvT5IU StxrVNFau6FsUdAHo0uvfOlz44PvDBm+NUZjZhI0Lz5g3RwUfuWiLglyhNs4bQWzjwoZ pdT/6egHOckxPXT/P3QBhYFx6iLIoPLRXfipMMTSLaZ/TScEmKOFgjklQpu1gA+KmgYt +VpiyXAudN57/0vTf3GU3UbYCxzjI7cbJgdFhpxh5U4VLMs9CeELgieCzgB68EMEYK7r rHIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SqjAQ4x0JHruDRSlJSVWOW//5VauAbIThz5/XephUL4=; b=L/eVADO8kplOU51XBS90qbZF/7qlCNUoJLpnAz7F4jNJFcY9rW8QTE6RLhaN4dTLl9 JNuLU0FhIXz/fWsSzboEDsZVGTIVuJwNDMXznT8btd7ppbnH8DeJBWg3grMzZ03lzpOZ Igttbn74d4nmJ/6a7iS1jQ3Vq15tQ3ZjJgt158m97KUbjEGWu5Ypo19SYAkf4HhbzL1y 8YJPLAmsn9s2lniQq5f38Qu4KJ1lxB/d+b7ayK1Jb21vzSyzhfND5Gt+o8dR0kEkHj8y zL+7aOzeMtufwzIDTAEdYQzCv/VBJ47ypdqqG8fV9ElvZs8407Lvn1LD1OKf9g5DfvxR KU/Q== X-Gm-Message-State: APt69E1R5FrF3OQovSzDpJvZK7lLpIMlo25PtoB3s4Q/kGD7rfcCyYGX RgzYDLMhzTX0opBk8E5SQSKSRhjTYgI= X-Google-Smtp-Source: ADUXVKLjQFdeqrOMH5xjtnJRVct7IQWsiEiQDL9nJXqS2h2LEIIpz8ApQ06YafjbWkKHdr3lY8ffnQ== X-Received: by 2002:a2e:5c89:: with SMTP id q131-v6mr4752527ljb.77.1528472101508; Fri, 08 Jun 2018 08:35:01 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:14 +0200 Message-Id: <1528472063-1660-17-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 16/25] Marvell/Drivers: MvBoardDesc: Extend protocol with COMPHY support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about COMPHY controllers to the ComPhyLib. Extend ArmadaBoardDescLib with new structure MV_BOARD_COMPHY_DESC, for holding board specific data. In further steps it can be extended and replace PCD SerDes lanes' representation with the appropriate structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 60 ++++++++++++++++= ++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 11 ++++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++ 4 files changed, 80 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 44d159e..d580319 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,65 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescComPhyGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_COMPHY_DESC **ComPhyDesc + ) +{ + UINT8 *ComPhyDeviceTable, ComPhyCount; + UINTN ComPhyDeviceTableSize, ComPhyIndex, Index; + MV_BOARD_COMPHY_DESC *BoardDesc; + MV_SOC_COMPHY_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available COMPHY controllers */ + Status =3D ArmadaSoCDescComPhyGet (&SoCDesc, &ComPhyCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled COMPHY controllers */ + ComPhyDeviceTable =3D (UINT8 *)PcdGetPtr (PcdComPhyDevices); + if (ComPhyDeviceTable =3D=3D NULL) { + /* No COMPHY controllers declared */ + return EFI_NOT_FOUND; + } + + ComPhyDeviceTableSize =3D PcdGetSize (PcdComPhyDevices); + + /* Check if PCD with COMPHY NICs is correctly defined */ + if (ComPhyDeviceTableSize > ComPhyCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdComPhyDevices format\n", __FUNCTION= __)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (ComPhyDeviceTableSize * sizeof (MV_BOARD= _COMPHY_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + ComPhyIndex =3D 0; + for (Index =3D 0; Index < ComPhyDeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (ComPhy, Index)) { + DEBUG ((DEBUG_ERROR, "%a: Skip ComPhy controller %d\n", __FUNCTION__= , Index)); + continue; + } + + BoardDesc[ComPhyIndex].SoC =3D &SoCDesc[Index]; + ComPhyIndex++; + } + + BoardDesc->ComPhyDevCount =3D ComPhyIndex; + + *ComPhyDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescAhciGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -374,6 +433,7 @@ MvBoardDescInitProtocol ( IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol ) { + BoardDescProtocol->BoardDescComPhyGet =3D MvBoardDescComPhyGet; BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; BoardDescProtocol->BoardDescXhciGet =3D MvBoardDescXhciGet; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index fe819ac..71b7ebd 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -57,6 +57,7 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] + gMarvellTokenSpaceGuid.PcdComPhyDevices gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled gMarvellTokenSpaceGuid.PcdUtmiPortType diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 938d283..1b56316 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,17 @@ #include =20 // +// COMPHY NIC devices per-board description +// +// TODO - Extend structure with entire +// ports description instead of PCDs. +// +typedef struct { + MV_SOC_COMPHY_DESC *SoC; + UINT8 ComPhyDevCount; +} MV_BOARD_COMPHY_DESC; + +// // NonDiscoverableDevices per-board description // =20 diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index a59ade5..27250db 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,13 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_COMPHY_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_COMPHY_DESC **ComPhyDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_AHCI_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -83,6 +90,7 @@ VOID ); =20 struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_COMPHY_GET BoardDescComPhyGet; MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:02 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7kg46wpudGnuKXZ9+WzIHAIOutj8O3Eax3yMW0qzr/4=; b=zkUgJFUHGZKhIEb9Q1QRB6hOo+ioWPyAPMW2Egc4+1qkWKAwbmjEAfr8DQ45frKwOj KllZKB+/zYE/WUiVaELM858iWKwe0VPBnz6IvJd/+irCni99n9D0TyLvDGzafIZ86HD/ 4NGK1TpS6W4jYN7bnZ3PT74fxZWs6IiFFkYiYk7EU1ueuw+hrontl2M3RF8eR7VjKZQ0 NSBv7Mj0v6QwutgfX6OYFrxnO3BUmLwYy1ncVgE67O267S5N79kJwaYf9hiDtXuuttx3 kKiBnBNKU1zrP92CGuelqk0p9T+kAulMr2XOD6ucjzFHNx+NyK1KKnYS/0vYj2sr5Og7 WmWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7kg46wpudGnuKXZ9+WzIHAIOutj8O3Eax3yMW0qzr/4=; b=VUKv1jWwsfHQAYrQ1drc4jyG/i6a+Fl9XOnQZCf0O1WzuA/54kiQeVElVN5GU9ZfAL aKOSMcAsrQ3h9ctlWEei3rjgPjtaFA5xZb0e3eXfhO/ttZ82O82sHBLpUbMLMPFqfjOt ARAyxAXXBFr/QeKDaL42iTaZC/HrcXnCE6SjdpVnrv2/H2Fs0FgMFc8YQGQV8I47wpxV f0dDOmimkcLr0pMm7oza+nucW+z/lxCh96eJ8+pafyBkDBOeEgjZGGfZN0mNp8XgLJLJ 1UdEYlStq9spQ/JRJEi1FVE/4f3rcHKB3JfvNDOrx9cRnPOFDC3dpy9eSUV6Woc8HBj3 vAiA== X-Gm-Message-State: APt69E3se4ySpOX1PrciLVtjoTmWOBXW00oNtj67TMncGPEAaWCpYEq+ vSnPeNRNeaLLzMODYH2GuCDS4+qnfr0= X-Google-Smtp-Source: ADUXVKIXfMmwTHHJiFj9UMAV6l3+1r4xVCA4WHwRaSYEQaaDW0qDDWa82y6wZ4ryOXBXmJYdsJtFug== X-Received: by 2002:a2e:129d:: with SMTP id 29-v6mr5136446ljs.102.1528472102713; Fri, 08 Jun 2018 08:35:02 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:15 +0200 Message-Id: <1528472063-1660-18-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 17/25] Marvell/Library: ComPhyLib: Switch library to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" MvComPhyLib library used to get Armada7k8k SerDes multiplexing controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this library. This patch updates the library, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Include/Library/MvHwDescLib.h | 39 ----------- Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 74 ++++++++++++-------- 2 files changed, 45 insertions(+), 68 deletions(-) diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 9f383f4..423ca17 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -35,8 +35,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MVHWDESCLIB_H__ #define __MVHWDESCLIB_H__ =20 -#include - // // Helper macros // @@ -45,20 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index]) =20 // -// CommonPhy devices description template definition -// -#define MVHW_MAX_COMPHY_DEVS 4 - -typedef struct { - UINT8 ComPhyDevCount; - UINTN ComPhyBaseAddresses[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyHpipe3BaseAddresses[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyLaneCount[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyMuxBitCount[MVHW_MAX_COMPHY_DEVS]; - MV_COMPHY_CHIP_TYPE ComPhyChipType[MVHW_MAX_COMPHY_DEVS]; -} MVHW_COMPHY_DESC; - -// // I2C devices description template definition // #define MVHW_MAX_I2C_DEVS 4 @@ -79,29 +63,6 @@ typedef struct { } MVHW_MDIO_DESC; =20 // -// Platform description of CommonPhy devices -// -#define MVHW_CP0_COMPHY_BASE 0xF2441000 -#define MVHW_CP0_HPIPE3_BASE 0xF2120000 -#define MVHW_CP0_COMPHY_LANES 6 -#define MVHW_CP0_COMPHY_MUX_BITS 4 -#define MVHW_CP1_COMPHY_BASE 0xF4441000 -#define MVHW_CP1_HPIPE3_BASE 0xF4120000 -#define MVHW_CP1_COMPHY_LANES 6 -#define MVHW_CP1_COMPHY_MUX_BITS 4 - -#define DECLARE_A7K8K_COMPHY_TEMPLATE \ -STATIC \ -MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate =3D {\ - 2,\ - { MVHW_CP0_COMPHY_BASE, MVHW_CP1_COMPHY_BASE },\ - { MVHW_CP0_HPIPE3_BASE, MVHW_CP1_HPIPE3_BASE },\ - { MVHW_CP0_COMPHY_LANES, MVHW_CP1_COMPHY_LANES },\ - { MVHW_CP0_COMPHY_MUX_BITS, MVHW_CP1_COMPHY_MUX_BITS },\ - { MvComPhyTypeCp110, MvComPhyTypeCp110 }\ -} - -// // Platform description of I2C devices // #define MVHW_CP0_I2C0_BASE 0xF2701000 diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.c index b03bc35..8555c4c 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -34,9 +34,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "ComPhyLib.h" #include -#include - -DECLARE_A7K8K_COMPHY_TEMPLATE; =20 CHAR16 * TypeStringTable [] =3D {L"unconnected", L"PCIE0", L"PCIE1", L"PCI= E2", L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3= ", @@ -182,22 +179,20 @@ VOID InitComPhyConfig ( IN OUT CHIP_COMPHY_CONFIG *ChipConfig, IN OUT PCD_LANE_MAP *LaneData, - IN UINT8 Id + IN MV_BOARD_COMPHY_DESC *Desc ) { - MVHW_COMPHY_DESC *Desc =3D &mA7k8kComPhyDescTemplate; - - ChipConfig->ChipType =3D Desc->ComPhyChipType[Id]; - ChipConfig->ComPhyBaseAddr =3D Desc->ComPhyBaseAddresses[Id]; - ChipConfig->Hpipe3BaseAddr =3D Desc->ComPhyHpipe3BaseAddresses[Id]; - ChipConfig->LanesCount =3D Desc->ComPhyLaneCount[Id]; - ChipConfig->MuxBitCount =3D Desc->ComPhyMuxBitCount[Id]; - ChipConfig->ChipId =3D Id; + ChipConfig->ChipType =3D Desc->SoC->ComPhyChipType; + ChipConfig->ComPhyBaseAddr =3D Desc->SoC->ComPhyBaseAddress; + ChipConfig->Hpipe3BaseAddr =3D Desc->SoC->ComPhyHpipe3BaseAddress; + ChipConfig->LanesCount =3D Desc->SoC->ComPhyLaneCount; + ChipConfig->MuxBitCount =3D Desc->SoC->ComPhyMuxBitCount; + ChipConfig->ChipId =3D Desc->SoC->ComPhyId; =20 /* * Below macro contains variable name concatenation (used to form PCD's = name). */ - switch (Id) { + switch (ChipConfig->ChipId) { case 0: GetComPhyPcd (LaneData, 0); break; @@ -219,32 +214,49 @@ MvComPhyInit ( ) { EFI_STATUS Status; - CHIP_COMPHY_CONFIG ChipConfig[MVHW_MAX_COMPHY_DEVS], *PtrChipCfg; - PCD_LANE_MAP LaneData[MVHW_MAX_COMPHY_DEVS]; + CHIP_COMPHY_CONFIG *ChipConfig, *PtrChipCfg; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_COMPHY_DESC *ComPhyBoardDesc; + PCD_LANE_MAP *LaneData; UINT32 Lane, MaxComphyCount; - UINT8 *ComPhyDeviceTable, Index; + UINT8 Index; =20 /* Obtain table with enabled ComPhy devices */ - ComPhyDeviceTable =3D (UINT8 *)PcdGetPtr (PcdComPhyDevices); - if (ComPhyDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdComPhyDevices\n")); - return EFI_INVALID_PARAMETER; + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D BoardDescProtocol->BoardDescComPhyGet (BoardDescProtocol, + &ComPhyBoardDesc); + if (EFI_ERROR (Status)) { + return Status; } =20 - if (PcdGetSize (PcdComPhyDevices) > MVHW_MAX_COMPHY_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdComPhyDevices format\n")); - return EFI_INVALID_PARAMETER; + ChipConfig =3D AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount * + sizeof (CHIP_COMPHY_CONFIG)); + if (ChipConfig =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + return EFI_OUT_OF_RESOURCES; + } + + LaneData =3D AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount * + sizeof (PCD_LANE_MAP)); + if (ChipConfig =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + FreePool (ChipConfig); + return EFI_OUT_OF_RESOURCES; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdComPhyDevices); Index++) { - if (!MVHW_DEV_ENABLED (ComPhy, Index)) { - DEBUG ((DEBUG_ERROR, "Skip ComPhy chip %d\n", Index)); - continue; - } + for (Index =3D 0; Index < ComPhyBoardDesc->ComPhyDevCount; Index++) { =20 PtrChipCfg =3D &ChipConfig[Index]; - InitComPhyConfig(PtrChipCfg, LaneData, Index); + InitComPhyConfig (PtrChipCfg, LaneData, &ComPhyBoardDesc[Index]); =20 /* Get the count of the SerDes of the specific chip */ MaxComphyCount =3D PtrChipCfg->LanesCount; @@ -275,5 +287,9 @@ MvComPhyInit ( PtrChipCfg->Init (PtrChipCfg); } =20 + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + FreePool (ChipConfig); + FreePool (LaneData); + return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472169625551.9112382498857; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:03 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9P2Ae/+7Fp4uwBbJgIw3rhSwymQ+bhresckobLx89xw=; b=IBmFZbz0A+VrvTRFUqgD6Wdeste8HYQaT09iFFOdhYurRjrOHNTmrjUt4HWz+vSFIZ CzsgdC8Ku+9sQ7ytrDuLJslRb3pMnjG6l1/mEHsMzkPjep7BrwpzIucgcxg4BILSJDNM nN9Ohdf8wDXibZ/IN0uNrZRXXjSz+qTZFKMPLm+cgXFR4gRwiSEIf1MbRs48g8j5/eU1 Ax14BtkW5S5r/1S3vdRzpE1B0WOrMuITNjA287Uthc6F6j4O/OoEHnpYSrgq2LGmXCS1 gVmBHRAzD0DECYPABWDDfhMX5I6khtYwfIz8ePHFD0vf9TtXxoPlJ3gkbe6zEk6H3815 rPcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9P2Ae/+7Fp4uwBbJgIw3rhSwymQ+bhresckobLx89xw=; b=TGB+GcNnB9A8QRizHbAsbncQi9gjzSDVANaev/oiD9UMCHWVlpNcSc8FrBKUEskInh q5bZdyN9zzDrk3ICUqXNsbANtdZp5h7Q2pgZwppeUDWhtESwCs1DJh1qE0KWQGrwya7f 6KEfNsdNZW1IYK0SrCjhVp+FIAi2BAmX6l7a/MVtbWqMtcO85hvmi3RuCgdrUxm1xbv5 6Is9mEWgZSOOW2G7c1SmOfuNLxlq6K573OU1I+IrtAXsjWVdBo9IpnXkBH63gH4jWfk8 Rzfo375QY+D07OYRIOXJsDdpWMjJaMVDhURqSHf1yTVZCdFatXlgAHOY1Kb0Qp57r8SC pRzQ== X-Gm-Message-State: APt69E20dx8wyrvgY2iiTXbJiY+hmX72gyXMffQpwAE51GsQTykmCpil +C9M2X2SY2/UpLQgrd8rvE3F42sfraQ= X-Google-Smtp-Source: ADUXVKLYZaR+dYC7uyNTtCisE465U5hbA/5jKITACAxIdRzyr1GasysaX4B4nNCtWkDHdVDtBrD2Tg== X-Received: by 2002:a2e:5142:: with SMTP id b2-v6mr4762293lje.30.1528472103940; Fri, 08 Jun 2018 08:35:03 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:16 +0200 Message-Id: <1528472063-1660-19-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 18/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with MDIO information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescMdioGet ()), which dynamically allocates and fills MV_SOC_MDIO_DESC structure with the SoC description of Mdio controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 34 ++++++++++++++++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 15 +++++++++ 2 files changed, 49 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index ba44a0c..515ff03 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -72,6 +72,40 @@ ArmadaSoCDescComPhyGet ( } =20 // +// Platform description of MDIO controllers +// +#define MV_SOC_MDIO_BASE(Cp) MV_SOC_CP_BASE ((Cp)) + 0x12A200 +#define MV_SOC_MDIO_ID(Cp) ((Cp)) + +EFI_STATUS +EFIAPI +ArmadaSoCDescMdioGet ( + IN OUT MV_SOC_MDIO_DESC **MdioDesc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_MDIO_DESC *Desc; + UINT8 CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + UINT8 CpIndex; + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_MDIO_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].MdioId =3D MV_SOC_MDIO_ID (CpIndex); + Desc[CpIndex].MdioBaseAddress =3D MV_SOC_MDIO_BASE (CpIndex); + } + + *MdioDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +// // Platform description of NonDiscoverableDevices // =20 diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 791d58b..41d9642 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -37,6 +37,21 @@ ArmadaSoCDescComPhyGet ( ); =20 // +// MDIO +// +typedef struct { + UINT8 MdioId; + UINTN MdioBaseAddress; +} MV_SOC_MDIO_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescMdioGet ( + IN OUT MV_SOC_MDIO_DESC **MdioDesc, + IN OUT UINT8 *DescCount + ); + +// // NonDiscoverable devices SoC description // // AHCI --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472174813925.0704047850634; Fri, 8 Jun 2018 08:36:14 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7391B21123B92; Fri, 8 Jun 2018 08:35:10 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 120672110A010 for ; Fri, 8 Jun 2018 08:35:07 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id g21-v6so18730719lfb.4 for ; Fri, 08 Jun 2018 08:35:06 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:04 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8Bru4zQ5E215rh2xwI0ek5og5uVeogcGXpCsJXvJYdY=; b=xQRnKhP/SENKDnCZ1Nfgtk5636g9fR+mvK6CBNmbg/M1rGm4D4pWzdcy1/tqqSz3rP mzFStkknU37A/7H8A4nKMz0TE42S3JgN9aW/NyRWr1kuG3bvxl6fp3aN0Cr8zV4UnpWZ kwBLUoT8kK/QCSvBu4dMKHulpZLws0xtfOWaBUn6Ya8nKvWXyG7nfNff6V4+DmzZESEX knZRNKmSck3hEtUqpZGl2X7jchvgoKCkHarLU4G1aG2mWcRzjRYEe/t3f17pKihghj+X Sb6ohIiksD/T2jgcgo7J5poTeM/LPQ8EAJozyEQw/f5rl9H4HETFhIfWvK7aeYr/jCGE jWVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8Bru4zQ5E215rh2xwI0ek5og5uVeogcGXpCsJXvJYdY=; b=Qg5ZboF3fx7/vTtmXsKhu6eBuArjHn/kPOdiEMCyU7HK9IIA6UxU2yDzU8d1+gxoYT +gFhnUKa+5ooxd2n8Glrhbg/J+uDuEzOoh+f64sCdhxz7mqdP18AC72LXgHfFzuMKc93 GuSmPmB+yU2Cv/NwJvnueI4R8Nqec48nPKTB87qlen/SZTFqqy61OePRRl0B2oP4kO9W i8tOrWa/liDsJXiDJRg7Fqu68z1D12se4qYhzXhTGkCtq+uPMEvOMtFuigaOEkMJuxmS dlu5f59+69g9xLpxy5J86uJhlTDNIadEnW3r7usnz4awLnTZOT1Vh1putMgTlV9dg6B2 KEeg== X-Gm-Message-State: APt69E1fkt9a7usHe3QyTHBOI7w6KIktYwU0IEA5gLcxxwfP9r9a92RN ivoii2nsa1smDoyfy1cw6GrIfnzw9SU= X-Google-Smtp-Source: ADUXVKIGaGz2oyRXApzyQ9piiYpWN+E247bQk8L3OjOKUb3XXnoXZEu26Jk9c8bawrXRjN46x47nbg== X-Received: by 2002:a2e:302:: with SMTP id 2-v6mr4872877ljd.9.1528472105123; Fri, 08 Jun 2018 08:35:05 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:17 +0200 Message-Id: <1528472063-1660-20-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 19/25] Marvell/Drivers: MvBoardDesc: Extend protocol with MDIO support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about MDIO controllers to the Mdio driver. Extend ArmadaBoardDescLib with new structure MV_BOARD_MDIO_DESC, for holding board specific data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 37 ++++++++++++++++= ++++ Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 8 +++++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++++ 3 files changed, 53 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index d580319..8f3bdfa 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -96,6 +96,42 @@ MvBoardDescComPhyGet ( =20 STATIC EFI_STATUS +MvBoardDescMdioGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_MDIO_DESC **MdioDesc + ) +{ + MV_BOARD_MDIO_DESC *BoardDesc; + MV_SOC_MDIO_DESC *SoCDesc; + EFI_STATUS Status; + UINT8 MdioCount; + UINTN Index; + + /* Get SoC data about all available MDIO controllers */ + Status =3D ArmadaSoCDescMdioGet (&SoCDesc, &MdioCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (MdioCount * sizeof (MV_BOARD_MDIO_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < MdioCount; Index++) { + BoardDesc[Index].SoC =3D &SoCDesc[Index]; + } + + BoardDesc->MdioDevCount =3D MdioCount; + *MdioDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescAhciGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -434,6 +470,7 @@ MvBoardDescInitProtocol ( ) { BoardDescProtocol->BoardDescComPhyGet =3D MvBoardDescComPhyGet; + BoardDescProtocol->BoardDescMdioGet =3D MvBoardDescMdioGet; BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; BoardDescProtocol->BoardDescXhciGet =3D MvBoardDescXhciGet; diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 1b56316..5379679 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -28,6 +28,14 @@ typedef struct { } MV_BOARD_COMPHY_DESC; =20 // +// MDIO devices per-board description +// +typedef struct { + MV_SOC_MDIO_DESC *SoC; + UINT8 MdioDevCount; +} MV_BOARD_MDIO_DESC; + +// // NonDiscoverableDevices per-board description // =20 diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index 27250db..cff802a 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -50,6 +50,13 @@ EFI_STATUS =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_MDIO_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_MDIO_DESC **MdioDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_AHCI_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -91,6 +98,7 @@ VOID =20 struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_COMPHY_GET BoardDescComPhyGet; + MV_BOARD_DESC_MDIO_GET BoardDescMdioGet; MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472179751659.0205936878098; Fri, 8 Jun 2018 08:36:19 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A547321123B9E; Fri, 8 Jun 2018 08:35:10 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6D6C921123883 for ; Fri, 8 Jun 2018 08:35:08 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id u4-v6so20731100lff.3 for ; Fri, 08 Jun 2018 08:35:08 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:05 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E75mTbrivFd7M1oHrism5mRDaLeUvq1/0kwfaLpCbPk=; b=a6Z7Nsa/BoMVx9WS0cvy4pQMJEPZN2ObmYcAe/y6Y3+qEhNfRFmkOKHmovxYVCDCDa s/B7G2UqSC0WDRTYoX+QElgjkF8tv/NmStrCg6BbssmQNy2uLNZSg8vCmepdm4EsxbwH mUUCPdXDW0py60HYN/2QK5txEalcM3++21hSf/06cHoWNTHLat5qDYtlc8LWURaBaOXD AVZq+70ll4VLu8L4A3/aQeyEYAlaNS+FrpKDuJNLytRCFmh1p7LgIPyDO2C9aQOv2tH5 vtMfEEJSNI6TScaY2B+Gb193OlPYFQqKBjd8UIU48HzL7OgYbLHD9QBhvFSJcw2V5j9/ u6wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E75mTbrivFd7M1oHrism5mRDaLeUvq1/0kwfaLpCbPk=; b=qWLO3X/6iMgHX/0vl77FX0N7sR2RL8U8zbK7TCk80zSMsHO9eUGrUDbCf+50nYYkA8 oNx9EVIeMkAyiJdmpmn/xyFOufQpEXHNkvG3aPli2x12e8YqdAdwExG6A5DH1n22KcTU sDUVwhJbBPMfkjNI1vwhY6NwF46YpNe140w3dTebuLnK5y+dka2cI9piKkfd58M6QLl/ wcE4TzuJ60UJgzWPoEbAzpHwTMc3qmaKw88A6Nls/8ygYy2xA+KfU7feMqpYGYTQ2Z2K v0bB3nXRJgLel2iWLEgaT0dEqpv+K7H4IfPkh6zq9U4R0ZPqgGaJPVOGtjmAnAty3giQ oqEA== X-Gm-Message-State: APt69E2WaNDvYi5qp91+RUl3So0/6SDiSsgaaPm3MvB2Ivn0WfhnUK+J lQTd+f+UpW3ZbWJWqXvVp4VawI/4ma8= X-Google-Smtp-Source: ADUXVKIb0iyy5m6DjAj2qn8NXCPzYFJDn48KMvUt5iNhI9U0odlE3y9ofbbqOgqkuFOeNdNDByZGKw== X-Received: by 2002:a2e:9dd0:: with SMTP id x16-v6mr4890755ljj.142.1528472106429; Fri, 08 Jun 2018 08:35:06 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:18 +0200 Message-Id: <1528472063-1660-21-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 20/25] Marvell/Drivers: MvMdioDxe: Enable 64bit addressing X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In order to be prepared for operating on registers in 64-bit address space, this patch adjusts the MDIO controllers base address array. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c b/Silicon/Ma= rvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c index 12aabad..6c0a129 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c @@ -70,7 +70,7 @@ MdioCheckParam ( STATIC EFI_STATUS MdioWaitReady ( - UINT32 MdioBase + UINTN MdioBase ) { UINT32 Timeout =3D MVEBU_SMI_TIMEOUT; @@ -92,7 +92,7 @@ MdioWaitReady ( STATIC EFI_STATUS MdioWaitValid ( - UINT32 MdioBase + UINTN MdioBase ) { UINT32 Timeout =3D MVEBU_SMI_TIMEOUT; @@ -122,7 +122,7 @@ MdioOperation ( IN OUT UINT32 *Data ) { - UINT32 MdioBase =3D This->BaseAddresses[MdioIndex]; + UINTN MdioBase =3D This->BaseAddresses[MdioIndex]; UINT32 MdioReg; EFI_STATUS Status; =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472184605156.5001613707077; Fri, 8 Jun 2018 08:36:24 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CE38821123E12; Fri, 8 Jun 2018 08:35:10 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C5CE821123B87 for ; Fri, 8 Jun 2018 08:35:09 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id n15-v6so20685756lfn.10 for ; Fri, 08 Jun 2018 08:35:09 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:06 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5dZERmuEiHF5TY01HgKj8H15UdE5nXrx0S4hXit2OFA=; b=NZB7r/I8k+1U1B6+8b0Mb+ROVufDgLTnMl/7zaBUmo76rse8TziHkeDW6MPgcc7zHk x/MOcS9A/pHdKQC92QzugTNBisq9W2AqMnfha3Y/NdaxOSNXoqk0AS6Zw5zIHkdxiXRj IGeIm9uIWbA11tR3ltTf/gIJuZbK41UoCnPPka4I8nsUMZSi4Uh0xFPJjp112H6qyiVs dedwTzm+hqsz5h4jsJYIjF8fsmC3w0ycmnZnhfL9ko4M21MJlgcZUdxLRXnOedbtbzEQ pUWso/GCKj+/u7ayNNw1Qb4q2tI5uk85HexASmWuScpp11PdPBMX6OjbxfU+wmQI8rMt twPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5dZERmuEiHF5TY01HgKj8H15UdE5nXrx0S4hXit2OFA=; b=BEsyqMuJ9uMgZel2HPP2fOymr8Eh2XAQbWHvlZU0gPClCo72HhxlJuWIIujuQ0cRKI VWC4l0+wMWyLIE5yB7rYXL9jwtg2QlNuhwKwVfpZsEbmelt9cBxe8DiFzPE0aWTvyjaV XYhavzl0IND7ZbGteXegxyb+6qZYndFj05H+Y5PVjxqng+nxfH4vK21nriQ4Ytv7iKgg 0U2Vk60vYAgM8sfjUJqR8wN7WPPniItZiJohhe/uREDgjY7EsQXOPdOL7gqbXXBbGeh2 0vSd7hGwSr2yof4vW8x9o/E0ca//gqrwp0JnfoHx7sun4omXkErTtnhWDZncMa/4pb/Q 9GMQ== X-Gm-Message-State: APt69E1IO2mRqbBLL05IQjPqdC7Lax9BDadilmipzzRsNrPXOPkVnP7W 8HGGuCk2Bb1T+eg/E8MufUYC2DjS48M= X-Google-Smtp-Source: ADUXVKKy6gcoLRSX3IuD1Vt2iCXttkT0oYjVk7Tdr14B6yk9rcS2meMuu2jPb3JMklxwElhkIQN3nQ== X-Received: by 2002:a2e:161d:: with SMTP id w29-v6mr5124725ljd.105.1528472107808; Fri, 08 Jun 2018 08:35:07 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:19 +0200 Message-Id: <1528472063-1660-22-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 21/25] Marvell/Drivers: MvMdioDxe: Switch driver to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" MvMdioDxe driver used to get Armada7k8k controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c | 35 ++++++++++++++++-= --- Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 1 + Silicon/Marvell/Include/Library/MvHwDescLib.h | 23 ------------- Silicon/Marvell/Include/Protocol/Mdio.h | 4 +-- 4 files changed, 31 insertions(+), 32 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c b/Silicon/Ma= rvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c index 6c0a129..72e88bd 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 **************************************************************************= *****/ =20 +#include #include #include =20 @@ -46,8 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "MvMdioDxe.h" =20 -DECLARE_A7K8K_MDIO_TEMPLATE; - STATIC EFI_STATUS MdioCheckParam ( @@ -216,24 +215,46 @@ MvMdioDxeInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_MDIO_DESC *Desc =3D &mA7k8kMdioDescTemplate; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_MDIO_DESC *MdioBoardDesc; UINT8 Index; MARVELL_MDIO_PROTOCOL *Mdio; EFI_STATUS Status; EFI_HANDLE Handle =3D NULL; =20 + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D BoardDescProtocol->BoardDescMdioGet (BoardDescProtocol, + &MdioBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Mdio =3D AllocateZeroPool (sizeof (MARVELL_MDIO_PROTOCOL)); if (Mdio =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "MdioDxe: Protocol allocation failed\n")); return EFI_OUT_OF_RESOURCES; } =20 + Mdio->BaseAddresses =3D AllocateZeroPool (MdioBoardDesc->MdioDevCount * + sizeof (UINTN)); + if (Mdio->BaseAddresses =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "MdioDxe: Protocol allocation failed\n")); + return EFI_OUT_OF_RESOURCES; + } + /* Obtain base addresses of all possible controllers */ - for (Index =3D 0; Index < Desc->MdioDevCount; Index++) { - Mdio->BaseAddresses[Index] =3D Desc->MdioBaseAddresses[Index]; + for (Index =3D 0; Index < MdioBoardDesc->MdioDevCount; Index++) { + Mdio->BaseAddresses[Index] =3D MdioBoardDesc[Index].SoC->MdioBaseAddre= ss; } =20 - Mdio->ControllerCount =3D Desc->MdioDevCount; + Mdio->ControllerCount =3D MdioBoardDesc->MdioDevCount; Mdio->Read =3D MvMdioRead; Mdio->Write =3D MvMdioWrite; =20 @@ -248,5 +269,7 @@ MvMdioDxeInitialise ( return Status; } =20 + BoardDescProtocol->BoardDescFree (MdioBoardDesc); + return EFI_SUCCESS; } diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf b/Silicon/= Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf index c070785..739576f 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf @@ -60,6 +60,7 @@ UefiLib =20 [Protocols] + gMarvellBoardDescProtocolGuid gMarvellMdioProtocolGuid =20 [Depex] diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 423ca17..0de435d 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -53,16 +53,6 @@ typedef struct { } MVHW_I2C_DESC; =20 // -// MDIO devices description template definition -// -#define MVHW_MAX_MDIO_DEVS 2 - -typedef struct { - UINT8 MdioDevCount; - UINTN MdioBaseAddresses[MVHW_MAX_MDIO_DEVS]; -} MVHW_MDIO_DESC; - -// // Platform description of I2C devices // #define MVHW_CP0_I2C0_BASE 0xF2701000 @@ -77,17 +67,4 @@ MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ { MVHW_CP0_I2C0_BASE, MVHW_CP0_I2C1_BASE, MVHW_CP1_I2C0_BASE, MVHW_CP1_I= 2C1_BASE }\ } =20 -// -// Platform description of MDIO devices -// -#define MVHW_CP0_MDIO_BASE 0xF212A200 -#define MVHW_CP1_MDIO_BASE 0xF412A200 - -#define DECLARE_A7K8K_MDIO_TEMPLATE \ -STATIC \ -MVHW_MDIO_DESC mA7k8kMdioDescTemplate =3D {\ - 2,\ - { MVHW_CP0_MDIO_BASE, MVHW_CP1_MDIO_BASE }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Include/Protocol/Mdio.h b/Silicon/Marvell/Incl= ude/Protocol/Mdio.h index d077a8f..076ea26 100644 --- a/Silicon/Marvell/Include/Protocol/Mdio.h +++ b/Silicon/Marvell/Include/Protocol/Mdio.h @@ -35,8 +35,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MDIO_H__ #define __MDIO_H__ =20 -#include - #define MARVELL_MDIO_PROTOCOL_GUID { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0= x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} =20 typedef struct _MARVELL_MDIO_PROTOCOL MARVELL_MDIO_PROTOCOL; @@ -64,7 +62,7 @@ EFI_STATUS struct _MARVELL_MDIO_PROTOCOL { MARVELL_MDIO_READ Read; MARVELL_MDIO_WRITE Write; - UINTN BaseAddresses[MVHW_MAX_MDIO_DEVS]; + UINTN *BaseAddresses; UINTN ControllerCount; }; =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472189647428.13794478034094; Fri, 8 Jun 2018 08:36:29 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 02BD421123B9A; Fri, 8 Jun 2018 08:35:13 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EC83221123E26 for ; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:08 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KT5QRtbDgwbXtcwA3t39e0jGJBkylObyDkexSA3FiK0=; b=UYb7Zzj5onT3l+rlxTQY31S/iWZjQaZKLEFqlPJ8kn+q7LVW9lZ4jfbYeY/dxTYK2v 8TxeOGoJbkazjW1UxOPA5usCh8x7rsxt67N3VkyomqAA9oVt4IIDCYU2z5tJgFQFAqAK YIk2vU6fhwU9cfjsLXn1qx5w31kCeIv9f4wUu/r/+caVbWoW2JD82FMJo58glzv9NmU4 oC+jBj6DlsLGH8L9fwFOS3+F5h6848XvV/5YNn3fNYzPD5MqygYPKdOLa1jtMQQ8Rx9s LvcQXO3Ki9XVWLed0J8XB8aFF7D3/xf7kXH6i4Ub+jGD5JY/D0IBvHSplE8F0AHV7DHD 45dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KT5QRtbDgwbXtcwA3t39e0jGJBkylObyDkexSA3FiK0=; b=jQWc9c/FkbSnbwx/BIPxjUKXZYfU0uacgp3l2CjeF3u6u23upMYeJyGQw/VLnbjRqu UznsWTjQHcti0Kn5+cVeqtqa0l971F8wWLnJTPqMgcdLrswy8IHusr3HzLylBTHulJqC fFcTII/fzvGWqF9mkmwWK5He18FXzG9q1Likte/DVzc9560dsiWBtID/t6tjz2aK804D FsyDIRf7m87knL6bjgaP00Y2AWQW4TGf9a3AcNiwwsmBd+1iWcKs2MRQ9Gvl1hnoaEn0 0B9GWTxQCCp/kbb7UNw1OZ/qIX6bBjsmjHzZOcHMr0I8CIuVDAxdEnGluBFDXcEKXBmx UnGA== X-Gm-Message-State: APt69E1OHwEdkpDbg20dZVco6SzpNqb3ZAX3Z9cZC9pFnF2FM4RwBB6l DBulMl3Mo1FHQPGXZ7lgk2xUapStMwI= X-Google-Smtp-Source: ADUXVKJIieyQjzl8UBkUcEbjGdKwP1tcbToTk01UKcWjVwirq1oBwC7HHCSFwaVyGv9VN8glTUA41Q== X-Received: by 2002:a2e:f11:: with SMTP id 17-v6mr5090998ljp.47.1528472109034; Fri, 08 Jun 2018 08:35:09 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:20 +0200 Message-Id: <1528472063-1660-23-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 22/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with I2C information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescI2cGet ()), which dynamically allocates and fills MV_SOC_I2C_DESC structure with the SoC description of I2c controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 38 ++++++++++++++++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 15 ++++++++ 2 files changed, 53 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 515ff03..36441c0 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -72,6 +72,44 @@ ArmadaSoCDescComPhyGet ( } =20 // +// Platform description of I2C controllers +// +#define MV_SOC_I2C_PER_CP_COUNT 2 +#define MV_SOC_I2C_BASE(I2c) (0x701000 + (I2c) * 0x100) + +EFI_STATUS +EFIAPI +ArmadaSoCDescI2cGet ( + IN OUT MV_SOC_I2C_DESC **I2cDesc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_I2C_DESC *Desc; + UINT8 CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + UINT8 Index, CpIndex, I2cIndex =3D 0; + + Desc =3D AllocateZeroPool (CpCount * MV_SOC_I2C_PER_CP_COUNT * + sizeof (MV_SOC_I2C_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_I2C_PER_CP_COUNT; Index++) { + Desc[I2cIndex].I2cBaseAddress =3D + MV_SOC_CP_BASE (CpIndex) + MV_SOC_I2C_BASE (Index= ); + I2cIndex++; + } + } + + *I2cDesc =3D Desc; + *DescCount =3D I2cIndex; + + return EFI_SUCCESS; +} + +// // Platform description of MDIO controllers // #define MV_SOC_MDIO_BASE(Cp) MV_SOC_CP_BASE ((Cp)) + 0x12A200 diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 41d9642..b608c8c 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -37,6 +37,21 @@ ArmadaSoCDescComPhyGet ( ); =20 // +// I2C +// +typedef struct { + UINT8 I2cId; + UINTN I2cBaseAddress; +} MV_SOC_I2C_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescI2cGet ( + IN OUT MV_SOC_I2C_DESC **I2cDesc, + IN OUT UINT8 *DescCount + ); + +// // MDIO // typedef struct { --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472194892576.494212145991; Fri, 8 Jun 2018 08:36:34 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2B56C2112501D; Fri, 8 Jun 2018 08:35:14 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 62F5C21124FF7 for ; Fri, 8 Jun 2018 08:35:12 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id g21-v6so18731094lfb.4 for ; Fri, 08 Jun 2018 08:35:12 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:09 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kaDewu0chaAURppnrPuBcw1wnumVQipr2QYL0cgmlX4=; b=IP88tQ7+1EFQJgzDVr7ueth1AN0dBZ7WzybEyW3O8c9q6Q9iONYf6Xl6PUO9xOH2e1 1K7rdVJEoGDch7lYtF5PmWW28yGp3ppPIMzh48DzGlMKWOkdTcPqoCLiYbvrxko8d8tz +oNrxVdIaEfvz8eb3PaADaWQ48OvHbulndnsp3RFQSvXeXQ1vH/2WJjurcJP/pGy3t1R zVZXaSegm0F6Pi5c6u6rDC7f3VIu2/54gVoXGD9tAgZm8jtYS4vCxMt/o2/PUQYg7ytA 5qYbd+ELg8GJDRy5yrvKPd36lqiuI0/Pj3SH9OdIGXJoL6kvWwRJ4ntUyy8KZybPZehC MqHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kaDewu0chaAURppnrPuBcw1wnumVQipr2QYL0cgmlX4=; b=Hiq4qiTxrmdHQG8IOxwlg9l1dXakmYzwx2VOU+WA++PiOPV6LTaVWv6GluhuANo7jm kmK5F0PYRsq3qqU8xvZdpbh2Nsh7+w7OYccuYBV8+S6f+y1uTAVRBHe0l2fZlHv2TcrM /FBR/NlGXcrQi2fmtIeA10Uv7MsOCU2LXkRfl3PhIplbSTUI9QyBFd9V43jIDs0lIKzw I/1sQmwNja1Yoxz3vtwrnFSHyGJqNrXJjVFXIRdbrKGO52QGGG94JcC0XLhjzNOnaP/7 3ohYqT8kmI8ROM6E21RZeaEwQnGGY06sb7woSScaucsNzm6/Gro9f4nnWh+gp2o+rU4N 5WiQ== X-Gm-Message-State: APt69E3klv/El62+vHFTW0hyutZaKQs5wsknm/HTGQ6zW0R6E7xyAzw8 DvrCN0GsW3hgyr7rPCurLXwgwb8x7E4= X-Google-Smtp-Source: ADUXVKLxaeJig3U+D2nyYFJd8FZYo1gQcEe/dj9vSFKiCfycTzYo0ieoQjF4bxCgYudkSsraYb4aEw== X-Received: by 2002:a2e:5f8f:: with SMTP id x15-v6mr4801442lje.70.1528472110293; Fri, 08 Jun 2018 08:35:10 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:21 +0200 Message-Id: <1528472063-1660-24-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 23/25] Marvell/Drivers: MvBoardDesc: Extend protocol with I2C support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about I2C controllers to the I2c driver. Extend ArmadaBoardDescLib with new structure MV_BOARD_I2C_DESC, for holding board specific data. In further steps it should be extended and replace PCD I2C devices' representation with the appropriate structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 62 ++++++++++++++++= ++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 11 ++++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++ 4 files changed, 82 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 8f3bdfa..a133085 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -96,6 +96,67 @@ MvBoardDescComPhyGet ( =20 STATIC EFI_STATUS +MvBoardDescI2cGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_I2C_DESC **I2cDesc + ) +{ + UINT8 *I2cDeviceTable, I2cCount; + UINTN I2cDeviceTableSize, I2cIndex, Index; + MV_BOARD_I2C_DESC *BoardDesc; + MV_SOC_I2C_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available I2C controllers */ + Status =3D ArmadaSoCDescI2cGet (&SoCDesc, &I2cCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled I2C controllers */ + I2cDeviceTable =3D (UINT8 *)PcdGetPtr (PcdI2cControllersEnabled); + if (I2cDeviceTable =3D=3D NULL) { + /* No I2C on platform */ + return EFI_SUCCESS; + } + + I2cDeviceTableSize =3D PcdGetSize (PcdI2cControllersEnabled); + + /* Check if PCD with I2C controllers is correctly defined */ + if (I2cDeviceTableSize > I2cCount) { + DEBUG ((DEBUG_ERROR, + "%a: Wrong PcdI2cControllersEnabled format\n", + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (I2cDeviceTableSize * sizeof (MV_BOARD_I2= C_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + I2cIndex =3D 0; + for (Index =3D 0; Index < I2cDeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (I2c, Index)) { + DEBUG ((DEBUG_INFO, "%a: Skip I2c controller %d\n", __FUNCTION__, In= dex)); + continue; + } + + BoardDesc[I2cIndex].SoC =3D &SoCDesc[Index]; + I2cIndex++; + } + + BoardDesc->I2cDevCount =3D I2cIndex; + + *I2cDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescMdioGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_MDIO_DESC **MdioDesc @@ -470,6 +531,7 @@ MvBoardDescInitProtocol ( ) { BoardDescProtocol->BoardDescComPhyGet =3D MvBoardDescComPhyGet; + BoardDescProtocol->BoardDescI2cGet =3D MvBoardDescI2cGet; BoardDescProtocol->BoardDescMdioGet =3D MvBoardDescMdioGet; BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index 71b7ebd..cc93eba 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -58,6 +58,7 @@ =20 [Pcd] gMarvellTokenSpaceGuid.PcdComPhyDevices + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled gMarvellTokenSpaceGuid.PcdUtmiPortType diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 5379679..74361d4 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -28,6 +28,17 @@ typedef struct { } MV_BOARD_COMPHY_DESC; =20 // +// I2C devices per-board description +// +// TODO - Extend structure with entire +// ports description instead of PCDs. +// +typedef struct { + MV_SOC_I2C_DESC *SoC; + UINT8 I2cDevCount; +} MV_BOARD_I2C_DESC; + +// // MDIO devices per-board description // typedef struct { diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index cff802a..0b73d27 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -50,6 +50,13 @@ EFI_STATUS =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_I2C_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_I2C_DESC **I2cDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_MDIO_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_MDIO_DESC **MdioDesc @@ -98,6 +105,7 @@ VOID =20 struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_COMPHY_GET BoardDescComPhyGet; + MV_BOARD_DESC_I2C_GET BoardDescI2cGet; MV_BOARD_DESC_MDIO_GET BoardDescMdioGet; MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472204390242.74211852880342; Fri, 8 Jun 2018 08:36:44 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 523FC21125468; Fri, 8 Jun 2018 08:35:15 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C52542112500C for ; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:11 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pkbl1baEnS4Ft4q4RUz3QrHFCPwP0zkmf08HS3bYnJo=; b=tARhoWiJozZRYFJoICMg1SAG4OTEcgz1ls7tSm3g2bAfW9RbbtkTlQIIy3x3P4bIpo ZN7F/05bL6ELkeZx0h2aGGSqeddWBsrqR8/nSRs/NJYR8fC/+UPDjLm9xf7Scb3YxfO3 W0xk4behElbf9xST95TmGMLZF/o7waiiMBP6qkoVdD0mNBIYtSa4n23xPpwur4KJRiLA kcnEOwakrRx5cYQLLUG+l5cAuYqmDnoLI8sEE4b+bF8sAjUY5CkjygOHUDJHYleXOpxj zJEIElJ5zZ3BI1oegMqSSQlAKzI+ACKfpdVJ25tcQ+bq9Emg2kl2rUx20qjGDcVcS3Kt GsVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pkbl1baEnS4Ft4q4RUz3QrHFCPwP0zkmf08HS3bYnJo=; b=M8eXuDpN996iavOM5wGopRyqS3GRYQEWA3eh7dbOXB1Itt/FU4MKqO7rWJoGbOHlYg xSpGe5c3K/7pqyCHpjQ0pOusYmaPea1wZ+fJHSx+Y5zXB6F2JFWM85H9+9Sa2kxRQzpu Cv7r1ApG3HXtdVErAbo77OPlXtTNIR8R3IAeXMPLqzCTwvJdoBFLR4tTlekQTqe0HsU8 BDjuObAvKa4BCwX9XkuFGANZj8XgsHoSsLmKsGmfIEgX4aQ/HEWlxvRKM27uzgVnBnu0 e2hvbuxOdzzTb5TAwvZDfTFSFhITJhYNI6fZswJ/tYGGxcMNVFgawW7AfwHcR6o7GXsK kPPg== X-Gm-Message-State: APt69E34WSIRDLgsYXsfxTEMHFABveCG/YLmFq7+EaJHkz7LDW/1CuiH Ak7Gk5IQON1s2BXjuxiy6+fhz+kOpa4= X-Google-Smtp-Source: ADUXVKLsKNvgBOJF6nf0p3Lkkg/iSH0tFOjefBQ3xVWcw+gVjcFJ6TmviRyNS5ZzMc2Iu+/f+hl04w== X-Received: by 2002:a2e:96c6:: with SMTP id d6-v6mr4910117ljj.21.1528472111704; Fri, 08 Jun 2018 08:35:11 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:22 +0200 Message-Id: <1528472063-1660-25-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 24/25] Marvell/Drivers: MvI2cDxe: Switch driver to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" MvI2cDxe driver used to get Armada7k8k controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 37 +++++++++----------- Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 1 + 2 files changed, 18 insertions(+), 20 deletions(-) diff --git a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Silicon/Marv= ell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index d6f590d..8694198 100755 --- a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 **************************************************************************= *****/ =20 +#include #include #include #include @@ -43,13 +44,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include #include #include -#include #include =20 #include "MvI2cDxe.h" =20 -DECLARE_A7K8K_I2C_TEMPLATE; - STATIC MV_I2C_BAUD_RATE baud_rate; =20 STATIC MV_I2C_DEVICE_PATH MvI2cDevicePathProtocol =3D { @@ -174,38 +172,37 @@ MvI2cInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_I2C_DESC *Desc =3D &mA7k8kI2cDescTemplate; - UINT8 *I2cDeviceTable, Index; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_I2C_DESC *Desc; + UINT8 Index; EFI_STATUS Status; =20 - /* Obtain table with enabled I2c devices */ - I2cDeviceTable =3D (UINT8 *)PcdGetPtr (PcdI2cControllersEnabled); - if (I2cDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdI2cControllersEnabled\n")); - return EFI_INVALID_PARAMETER; + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } =20 - if (PcdGetSize (PcdI2cControllersEnabled) > MVHW_MAX_I2C_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdI2cControllersEnabled format\n")); - return EFI_INVALID_PARAMETER; + Status =3D BoardDescProtocol->BoardDescI2cGet (BoardDescProtocol, &Desc); + if (EFI_ERROR (Status)) { + return Status; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdI2cControllersEnabled); Index++= ) { - if (!MVHW_DEV_ENABLED (I2c, Index)) { - DEBUG ((DEBUG_ERROR, "Skip I2c chip %d\n", Index)); - continue; - } - + for (Index =3D 0; Index < Desc->I2cDevCount; Index++) { Status =3D MvI2cInitialiseController( ImageHandle, SystemTable, - Desc->I2cBaseAddresses[Index] + Desc[Index].SoC->I2cBaseAddress ); if (EFI_ERROR(Status)) return Status; } =20 + BoardDescProtocol->BoardDescFree (Desc); + return EFI_SUCCESS; } =20 diff --git a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf b/Silicon/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf index a7cf52e..0eef350 100755 --- a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf +++ b/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf @@ -61,6 +61,7 @@ gEfiDevicePathProtocolGuid gEfiI2cEnumerateProtocolGuid gEfiI2cBusConfigurationManagementProtocolGuid + gMarvellBoardDescProtocolGuid =20 [Pcd] gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 02:37:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472207671277.60448259723046; Fri, 8 Jun 2018 08:36:47 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 76C5B2112500C; Fri, 8 Jun 2018 08:35:16 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E6A472112500C for ; Fri, 8 Jun 2018 08:35:14 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id i15-v6so10404860lfc.2 for ; Fri, 08 Jun 2018 08:35:14 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B03h/2YqxQWoBY9mLV/J6V1z3Fgh5LWPbdDU9UR/MWA=; b=AQiQN7uq7cHk5WPzhV30GOZn0wt3GMOh6uwVKSTWGBOd+dh4xNrslbqzz2+hCDBhrj wHydNFMIkkzPkmsCr3JbofZmkreqHJ4qmdAShlDYGWnQFs7Jt11EVVDBfEy0HUCz5rDX bmLtjMSelJvbZFTmnINempXrUs4Rn/D/ZkSbBdq1BGHVkkOLV7HTo0F9IGheOBnzEckj xj0Xqy3BcGaQjc43dfBryACWWDUWNhu/wkLgqsDqhWq8GtU81NlyS3OUBKSUX0PohjRt UfkFJVZdeBlhAEvgmr34kyZ9CJSwUw3oEVDktb7ps+xEm/78KEVb4kMHyjKsVA/P2HZ8 ynbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=B03h/2YqxQWoBY9mLV/J6V1z3Fgh5LWPbdDU9UR/MWA=; b=on/PLlkLQFEMWu5xXVVe5dhca9pIwrW4ZXfsLz+yZ2hoSHj3ujXJsEsJDDfqINu9lD Sp2IRlzzYfKUug32cFPQNp8VTdtVnmTUCF4+sAx0IOfbvb6D+sXE7JFWYh4VCDoj+lHH 6CE/Qqyoe1XNILQo8gbyT1hSDlXm68P9xY2pedyF/rIS3U4zddVgqmitQKiAM1suUTp+ qZxbDU9J2Z7jSAidnSHd9pZIv08PWO+5XG6EhaRMjxT8Ut6FynXTDkOSsOfoDfMLyyzd r0vv8XN/ANui1uwnxtLdVYf+F5CNhcbgbrHWi6JT9wxiCHzlDrC8txkw2FHQzziVvusd lfxw== X-Gm-Message-State: APt69E0QrJmJznursvbJpCGlxGEi08fa/crI7pY+TewPuY2vVcQ7Fjbb EpphN7zNeq94UY2afHyu8dkQ4c39krQ= X-Google-Smtp-Source: ADUXVKILNYH7RrrI2iktykfcoYdRkqMPDKWPMxTFe8OKyiRPLYTBDu1RQvPfT+baguhIWXXFnKpUUw== X-Received: by 2002:a2e:29cf:: with SMTP id p76-v6mr5181903ljp.12.1528472112952; Fri, 08 Jun 2018 08:35:12 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:23 +0200 Message-Id: <1528472063-1660-26-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 25/25] Marvell/Drivers: MvPhyDxe: Remove MvHwDescLib.h dependency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Finally, after switching to new MV_BOARD_DESC solution in all drivers, stop using MvHwDescLib.h by its last user and safely remove this header. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing Reviewed-by: Kostya Porotchkin Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c | 3 +- Silicon/Marvell/Include/Library/MvHwDescLib.h | 70 -------------------- 2 files changed, 1 insertion(+), 72 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c b/Silicon/Marv= ell/Drivers/Net/MvPhyDxe/MvPhyDxe.c index dd2edae..3deb286 100644 --- a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c +++ b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c @@ -41,7 +41,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include #include #include #include @@ -380,7 +379,7 @@ MvPhyInit ( MdioIndex =3D Phy2MdioController[PhyIndex]; =20 /* Verify correctness of PHY <-> MDIO assignment */ - if (!MVHW_DEV_ENABLED (Mdio, MdioIndex) || MdioIndex >=3D Mdio->Controll= erCount) { + if (MdioDeviceTable[MdioIndex] =3D=3D 0 || MdioIndex >=3D Mdio->Controll= erCount) { DEBUG ((DEBUG_ERROR, "MvPhyDxe: Incorrect Mdio controller assignment f= or PHY#%d", PhyIndex)); return EFI_INVALID_PARAMETER; } diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h deleted file mode 100644 index 0de435d..0000000 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ /dev/null @@ -1,70 +0,0 @@ -/*************************************************************************= ******* -Copyright (C) 2017 Marvell International Ltd. - -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute a= nd/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modific= ation, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -* Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -**************************************************************************= *****/ - -#ifndef __MVHWDESCLIB_H__ -#define __MVHWDESCLIB_H__ - -// -// Helper macros -// - -// Check if device is enabled - it expects PCD to be read to 'Device= Table' array -#define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index]) - -// -// I2C devices description template definition -// -#define MVHW_MAX_I2C_DEVS 4 - -typedef struct { - UINT8 I2cDevCount; - UINTN I2cBaseAddresses[MVHW_MAX_I2C_DEVS]; -} MVHW_I2C_DESC; - -// -// Platform description of I2C devices -// -#define MVHW_CP0_I2C0_BASE 0xF2701000 -#define MVHW_CP0_I2C1_BASE 0xF2701100 -#define MVHW_CP1_I2C0_BASE 0xF4701000 -#define MVHW_CP1_I2C1_BASE 0xF4701100 - -#define DECLARE_A7K8K_I2C_TEMPLATE \ -STATIC \ -MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ - 4,\ - { MVHW_CP0_I2C0_BASE, MVHW_CP0_I2C1_BASE, MVHW_CP1_I2C0_BASE, MVHW_CP1_I= 2C1_BASE }\ -} - -#endif /* __MVHWDESCLIB_H__ */ --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel