From nobody Wed May 14 20:08:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472137295129.37757201110242; Fri, 8 Jun 2018 08:35:37 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2BC0D2111002D; Fri, 8 Jun 2018 08:35:00 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 603132110A00B for ; Fri, 8 Jun 2018 08:34:58 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id 36-v6so20678298lfr.11 for ; Fri, 08 Jun 2018 08:34:58 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:55 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QWeNHRFTjDIlZ+55j7RSixIGSaaGhtSUtsP5IFNT+PU=; b=SJTU3lwEQlMdhqtJpLgnom4jERNJ7EAufhONMxcRX48UwzNrbCONvp6chp3CzDvJMJ eVLUvBlpqmaJV0+DUh3jD46z5QuFVI3QtjArbB15X+MTdvj9jQgpVHZsiJkLTJp/K1Ya bnHLCrLMPbpbGkKA72IeSjTcakA3ToZ9zpgD2Ow/FVp1ZeMKSuM+DJxBec3n1l72nEGV bsiZBjePmc7iPfrwwcmSbbxfLJNvt2zDyhZ2GDydjR77UOyOiJeQm8eggR+cTumK0O3c NqM49iALzGUVVRPO1xWJ8pYdJqQDDlRi9pIfwesjjQQDDBx04v9gFPHb5b/NynShoWiY vTSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QWeNHRFTjDIlZ+55j7RSixIGSaaGhtSUtsP5IFNT+PU=; b=eY/iH+blaFbRZumknkiBDN+cVEyygpIyd/ltgf/HRRboy7r/fTFZWBIGCd1p+AlJVA nCXrsospBp0x58KlwFAW+l1rP6reDb785EUtUIPua9Nu1ztedjfglfW0jye2N3jOv+mL rsd9NXo0ExYiy3PGXjVaCuXJ9ZBLC208WjMeNcC3rRYNvXnr70IRLWGx31eRzL3XGAA9 I5PWZLPxDssmHONJcVZVIhgqLeYvkP6S/EBG3LUdW1CUNF+YYIRCTuYyix1evVEWq/Pj AU/NUp26jOvbrmQMDnMrobDwdIQGLe/RVYVEAktGpf6gfybGKDDTcFPm7TYoHZnyZJSn bP4A== X-Gm-Message-State: APt69E3rFWxOJ4byF6vrbH/at1CHdMY3yJqlJHEc0st+6jZ2w9TFnWNe lPjQirbczDKNQXyaT3gFOt3AOQy6zxs= X-Google-Smtp-Source: ADUXVKIU2x/dpWJ84CwucQQiQUcyrcVGYQnmPOL1XNEcU8xM6xEJyujNWJJnrWK/FcGK1pKM8lYgSw== X-Received: by 2002:a2e:28b:: with SMTP id y11-v6mr4810065lje.27.1528472096389; Fri, 08 Jun 2018 08:34:56 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:10 +0200 Message-Id: <1528472063-1660-13-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 12/25] Marvell/Drivers: MvBoardDesc: Extend protocol with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about NonDiscoverableDevices to the relevant drivers and libraries. Extend ArmadaBoardDescLib with new structures (MV_BOARD_AHCI_DESC/ MV_BOARD_SDMMC_DESC/MV_BOARD_XHCI_DESC) for holding board specific data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 180 +++++++++++++++= +++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 2 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 31 ++++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 24 +++ 4 files changed, 237 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 86bddad..44d159e 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,183 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescAhciGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_AHCI_DESC **AhciDesc + ) +{ + UINT8 *AhciDeviceTable, AhciCount; + UINTN AhciDeviceTableSize, AhciIndex, Index; + MV_BOARD_AHCI_DESC *BoardDesc; + MV_SOC_AHCI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available AHCI controllers */ + Status =3D ArmadaSoCDescAhciGet (&SoCDesc, &AhciCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled AHCI controllers */ + AhciDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciEAhci); + if (AhciDeviceTable =3D=3D NULL) { + /* No AHCI on platform */ + return EFI_SUCCESS; + } + + AhciDeviceTableSize =3D PcdGetSize (PcdPciEAhci); + + /* Check if PCD with AHCI controllers is correctly defined */ + if (AhciDeviceTableSize > AhciCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEAhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (AhciDeviceTableSize * sizeof (MV_BOARD_A= HCI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + AhciIndex =3D 0; + for (Index =3D 0; Index < AhciDeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (Ahci, Index)) { + DEBUG ((DEBUG_INFO, "%a: Skip Ahci controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[AhciIndex].SoC =3D &SoCDesc[Index]; + AhciIndex++; + } + + BoardDesc->AhciDevCount =3D AhciIndex; + + *AhciDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvBoardDescSdMmcGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + UINT8 *SdMmcDeviceTable, SdMmcCount; + UINTN SdMmcDeviceTableSize, SdMmcIndex, Index; + MV_BOARD_SDMMC_DESC *BoardDesc; + MV_SOC_SDMMC_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available SDMMC controllers */ + Status =3D ArmadaSoCDescSdMmcGet (&SoCDesc, &SdMmcCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled SDMMC controllers */ + SdMmcDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciESdhci); + if (SdMmcDeviceTable =3D=3D NULL) { + /* No SDMMC on platform */ + return EFI_SUCCESS; + } + + SdMmcDeviceTableSize =3D PcdGetSize (PcdPciESdhci); + + /* Check if PCD with SDMMC controllers is correctly defined */ + if (SdMmcDeviceTableSize > SdMmcCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciESdhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (SdMmcDeviceTableSize * sizeof (MV_BOARD_= SDMMC_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + SdMmcIndex =3D 0; + for (Index =3D 0; Index < SdMmcDeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (SdMmc, Index)) { + DEBUG ((DEBUG_INFO, "%a: Skip SdMmc controller %d\n", __FUNCTION__, = Index)); + continue; + } + + BoardDesc[SdMmcIndex].SoC =3D &SoCDesc[Index]; + SdMmcIndex++; + } + + BoardDesc->SdMmcDevCount =3D SdMmcIndex; + + *SdMmcDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvBoardDescXhciGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_XHCI_DESC **XhciDesc + ) +{ + UINT8 *XhciDeviceTable, XhciCount; + UINTN XhciDeviceTableSize, XhciIndex, Index; + MV_BOARD_XHCI_DESC *BoardDesc; + MV_SOC_XHCI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available XHCI controllers */ + Status =3D ArmadaSoCDescXhciGet (&SoCDesc, &XhciCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled XHCI controllers */ + XhciDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciEXhci); + if (XhciDeviceTable =3D=3D NULL) { + /* No XHCI on platform */ + return EFI_SUCCESS; + } + + XhciDeviceTableSize =3D PcdGetSize (PcdPciEXhci); + + /* Check if PCD with XHCI controllers is correctly defined */ + if (XhciDeviceTableSize > XhciCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEXhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (XhciDeviceTableSize * sizeof (MV_BOARD_X= HCI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + XhciIndex =3D 0; + for (Index =3D 0; Index < XhciDeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (Xhci, Index)) { + DEBUG ((DEBUG_INFO, "%a: Skip Xhci controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[XhciIndex].SoC =3D &SoCDesc[Index]; + XhciIndex++; + } + + BoardDesc->XhciDevCount =3D XhciIndex; + + *XhciDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescPp2Get ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_PP2_DESC **Pp2Desc @@ -197,6 +374,9 @@ MvBoardDescInitProtocol ( IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol ) { + BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; + BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; + BoardDescProtocol->BoardDescXhciGet =3D MvBoardDescXhciGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index c7d5fe2..fe819ac 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -60,6 +60,8 @@ gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled gMarvellTokenSpaceGuid.PcdUtmiPortType + gMarvellTokenSpaceGuid.PcdPciEAhci + gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdPciEXhci =20 [Depex] diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 78cf698..938d283 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,37 @@ #include =20 // +// NonDiscoverableDevices per-board description +// + +// +// AHCI devices per-board description +// +typedef struct { + MV_SOC_AHCI_DESC *SoC; + UINT8 AhciDevCount; +} MV_BOARD_AHCI_DESC; + +// +// SDMMC devices per-board description +// +// TODO - Extend structure with entire +// ports description instead of PCDs. +// +typedef struct { + MV_SOC_SDMMC_DESC *SoC; + UINT8 SdMmcDevCount; +} MV_BOARD_SDMMC_DESC; + +// +// XHCI devices per-board description +// +typedef struct { + MV_SOC_XHCI_DESC *SoC; + UINT8 XhciDevCount; +} MV_BOARD_XHCI_DESC; + +// // PP2 NIC devices per-board description // // TODO - Extend structure with entire diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index 114a0ec..a59ade5 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,27 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_AHCI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_AHCI_DESC **AhciDesc + ); + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_SDMMC_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ); + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_XHCI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_XHCI_DESC **XhciDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_PP2_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_PP2_DESC **Pp2Desc @@ -62,6 +83,9 @@ VOID ); =20 struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; + MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; + MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; MV_BOARD_DESC_FREE BoardDescFree; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel