From nobody Mon Dec 15 01:57:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528472158481348.3214604802331; Fri, 8 Jun 2018 08:35:58 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E70EA2112388A; Fri, 8 Jun 2018 08:35:05 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6B75D21110029 for ; Fri, 8 Jun 2018 08:35:03 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id j13-v6so20697562lfb.13 for ; Fri, 08 Jun 2018 08:35:03 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.35.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:35:00 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SqjAQ4x0JHruDRSlJSVWOW//5VauAbIThz5/XephUL4=; b=0XQX9/P3c8z8aatOuGebstodtuhwT9ryp17ozfIJ7LVzkvSzBQYl5cg1ycceNsNxka h0D2BAHg2q8OJn1efVPZXsJw8k8rODjbrDX1EkkXf2tUiO2rQQoeflWsX/8yEAXvT5IU StxrVNFau6FsUdAHo0uvfOlz44PvDBm+NUZjZhI0Lz5g3RwUfuWiLglyhNs4bQWzjwoZ pdT/6egHOckxPXT/P3QBhYFx6iLIoPLRXfipMMTSLaZ/TScEmKOFgjklQpu1gA+KmgYt +VpiyXAudN57/0vTf3GU3UbYCxzjI7cbJgdFhpxh5U4VLMs9CeELgieCzgB68EMEYK7r rHIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SqjAQ4x0JHruDRSlJSVWOW//5VauAbIThz5/XephUL4=; b=L/eVADO8kplOU51XBS90qbZF/7qlCNUoJLpnAz7F4jNJFcY9rW8QTE6RLhaN4dTLl9 JNuLU0FhIXz/fWsSzboEDsZVGTIVuJwNDMXznT8btd7ppbnH8DeJBWg3grMzZ03lzpOZ Igttbn74d4nmJ/6a7iS1jQ3Vq15tQ3ZjJgt158m97KUbjEGWu5Ypo19SYAkf4HhbzL1y 8YJPLAmsn9s2lniQq5f38Qu4KJ1lxB/d+b7ayK1Jb21vzSyzhfND5Gt+o8dR0kEkHj8y zL+7aOzeMtufwzIDTAEdYQzCv/VBJ47ypdqqG8fV9ElvZs8407Lvn1LD1OKf9g5DfvxR KU/Q== X-Gm-Message-State: APt69E1R5FrF3OQovSzDpJvZK7lLpIMlo25PtoB3s4Q/kGD7rfcCyYGX RgzYDLMhzTX0opBk8E5SQSKSRhjTYgI= X-Google-Smtp-Source: ADUXVKLjQFdeqrOMH5xjtnJRVct7IQWsiEiQDL9nJXqS2h2LEIIpz8ApQ06YafjbWkKHdr3lY8ffnQ== X-Received: by 2002:a2e:5c89:: with SMTP id q131-v6mr4752527ljb.77.1528472101508; Fri, 08 Jun 2018 08:35:01 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 8 Jun 2018 17:34:14 +0200 Message-Id: <1528472063-1660-17-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH 16/25] Marvell/Drivers: MvBoardDesc: Extend protocol with COMPHY support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about COMPHY controllers to the ComPhyLib. Extend ArmadaBoardDescLib with new structure MV_BOARD_COMPHY_DESC, for holding board specific data. In further steps it can be extended and replace PCD SerDes lanes' representation with the appropriate structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 60 ++++++++++++++++= ++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 11 ++++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++ 4 files changed, 80 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 44d159e..d580319 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,65 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescComPhyGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_COMPHY_DESC **ComPhyDesc + ) +{ + UINT8 *ComPhyDeviceTable, ComPhyCount; + UINTN ComPhyDeviceTableSize, ComPhyIndex, Index; + MV_BOARD_COMPHY_DESC *BoardDesc; + MV_SOC_COMPHY_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available COMPHY controllers */ + Status =3D ArmadaSoCDescComPhyGet (&SoCDesc, &ComPhyCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Obtain table with enabled COMPHY controllers */ + ComPhyDeviceTable =3D (UINT8 *)PcdGetPtr (PcdComPhyDevices); + if (ComPhyDeviceTable =3D=3D NULL) { + /* No COMPHY controllers declared */ + return EFI_NOT_FOUND; + } + + ComPhyDeviceTableSize =3D PcdGetSize (PcdComPhyDevices); + + /* Check if PCD with COMPHY NICs is correctly defined */ + if (ComPhyDeviceTableSize > ComPhyCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdComPhyDevices format\n", __FUNCTION= __)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (ComPhyDeviceTableSize * sizeof (MV_BOARD= _COMPHY_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + ComPhyIndex =3D 0; + for (Index =3D 0; Index < ComPhyDeviceTableSize; Index++) { + if (!MVHW_DEV_ENABLED (ComPhy, Index)) { + DEBUG ((DEBUG_ERROR, "%a: Skip ComPhy controller %d\n", __FUNCTION__= , Index)); + continue; + } + + BoardDesc[ComPhyIndex].SoC =3D &SoCDesc[Index]; + ComPhyIndex++; + } + + BoardDesc->ComPhyDevCount =3D ComPhyIndex; + + *ComPhyDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescAhciGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -374,6 +433,7 @@ MvBoardDescInitProtocol ( IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol ) { + BoardDescProtocol->BoardDescComPhyGet =3D MvBoardDescComPhyGet; BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; BoardDescProtocol->BoardDescXhciGet =3D MvBoardDescXhciGet; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index fe819ac..71b7ebd 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -57,6 +57,7 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] + gMarvellTokenSpaceGuid.PcdComPhyDevices gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled gMarvellTokenSpaceGuid.PcdUtmiPortType diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 938d283..1b56316 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,17 @@ #include =20 // +// COMPHY NIC devices per-board description +// +// TODO - Extend structure with entire +// ports description instead of PCDs. +// +typedef struct { + MV_SOC_COMPHY_DESC *SoC; + UINT8 ComPhyDevCount; +} MV_BOARD_COMPHY_DESC; + +// // NonDiscoverableDevices per-board description // =20 diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index a59ade5..27250db 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,13 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_COMPHY_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_COMPHY_DESC **ComPhyDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_AHCI_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -83,6 +90,7 @@ VOID ); =20 struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_COMPHY_GET BoardDescComPhyGet; MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel