From nobody Thu May 2 18:43:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528880596972526.0742582593924; Wed, 13 Jun 2018 02:03:16 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 42823212E2584; Wed, 13 Jun 2018 02:03:15 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CCAF5212BC466 for ; Wed, 13 Jun 2018 02:03:12 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id t134-v6so2725525lff.6 for ; Wed, 13 Jun 2018 02:03:12 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q35-v6sm478023lfi.68.2018.06.13.02.03.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Jun 2018 02:03:09 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dujST/CLiXMjzNV9G+SCVHnxa4TijuFVXwOInBiT7Og=; b=MYpwmtLEKaWHkQn+HvI2WsJAsPjY56ywPG4eoO2gESMG2c6UOCmBVHT6VE3EPY+pii wCSDnl3ehhdPhoSko6fC8P0DpmwnRKu4zcasFbEPf4sLICMzHQjvYACZ881o8+7dQOZu ZoaO0M1DC/NFWZohhbjUvBis0j0as8QMNVJ0bEM6m89SwUJ+I5jQdMRdJ33QDw0y+SAV asR7I3Vbi0aEjqNT8ASekPkgib3NIK6iT2afUYESB2f8yZcOinhog4wrCB1qCj2zJele /KYGhB0gM9xmgmeOEHWEsjx04Oalr8tMgc7T6aHlJThJr2MTM0XNOAH+kHDX25bHNUwK M8Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dujST/CLiXMjzNV9G+SCVHnxa4TijuFVXwOInBiT7Og=; b=h3lBlgBj3dbahlbyoa/UGVPQcVQql534DQNp3eKD2PI/sGKjmgto+p6CxgDAGwcmL9 tVV9Df72yfHmx3j5ht82ivPlaJ3Wcmk52DAkThSLJPA6ZrbJyzS1FoviW28UOo1fqOxV oOtAmjQ9NEm01zACzAEdccCOEYBRdLTxrgM2sxdPEQsUwvwKDAegstU6lXfhvHIzGmaW /tBBo4w7GqYRj6nmhngu/7HRYNUQPKip+UR+HYSDBqQnk519QLIRxXG8rLdB6ocwv2+2 PzzWxpMiaTDP6T6SKTXDtjeTFt8Gg0Y5eCeZY4Ez03QDiAqfwrwxkZmV6CaCRsP1mds8 jieQ== X-Gm-Message-State: APt69E14iaS2/ZNP/gIhTn1LHZnRuVcbb3py6KqU7VZNPo5ogP5EFnKs dTY0wzTKaKYLowKbPdKZlxI3UNVR08I= X-Google-Smtp-Source: ADUXVKJGNiyCIBF/SFPAKzAn1LoLmD9b3pXlNz8ZxFSvT7GoXAsw/ujJqMbpZ8AY+S/k/47nv0/0Pw== X-Received: by 2002:a19:ea99:: with SMTP id y25-v6mr2523653lfi.20.1528880590884; Wed, 13 Jun 2018 02:03:10 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 13 Jun 2018 11:02:50 +0200 Message-Id: <1528880573-29494-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528880573-29494-1-git-send-email-mw@semihalf.com> References: <1528880573-29494-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 1/4] Marvell/Armada7k8k: Use common .fdf file X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" As for the preparation for adding multiple boards support, move common part of the .fdf file to the SoC family directory and change output FD file name to more generic. Once needed, possible per-board differences will be resolved by including custom .fdf.inc file. This way adding new common changes for entire SoC family won't require any duplication and at the same time the per-board .fdf.inc will allow better suiting the .FD file contents. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc = | 2 +- Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf =3D> Silicon/Marvell/Armada= 7k8k/Armada7k8k.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf =3D> Silicon/Marvell= /Armada7k8k/Armada7k8k.fdf (97%) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 46a1ea9..eedb025 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -43,7 +43,7 @@ SUPPORTED_ARCHITECTURES =3D AARCH64|ARM BUILD_TARGETS =3D DEBUG|RELEASE SKUID_IDENTIFIER =3D DEFAULT - FLASH_DEFINITION =3D Platform/Marvell/Armada70x0Db/Armada7= 0x0Db.fdf + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =20 diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Silicon/Marve= ll/Armada7k8k/Armada7k8k.fdf similarity index 97% rename from Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf rename to Silicon/Marvell/Armada7k8k/Armada7k8k.fdf index e5e5443..180b6c9 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -24,7 +24,7 @@ # ##########################################################################= ###### =20 -[FD.Armada70x0Db_EFI] +[FD.Armada_EFI] BaseAddress =3D 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The ba= se address of the Firmware in NOR Flash. Size =3D 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The si= ze in bytes of the FLASH Device ErasePolarity =3D 1 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 18:43:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528880598162803.4707221838516; Wed, 13 Jun 2018 02:03:18 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 70905212E25AC; Wed, 13 Jun 2018 02:03:16 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CFFB3212C344F for ; Wed, 13 Jun 2018 02:03:14 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id j13-v6so2699321lfb.13 for ; Wed, 13 Jun 2018 02:03:14 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q35-v6sm478023lfi.68.2018.06.13.02.03.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Jun 2018 02:03:11 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YvqBfV0/i+UB/eECSWLznh7ly4W650zNo1JwoMYaWQ4=; b=Sib8cdHJR1y0+DJhQYHZafNi5i8mBFjFvzAQKkpraXWdXIY1mh8uyBeqiINQymjpeg WeF+jQYS3r4SnSpMI9Ri+Yp+RkB858DK1YgyXa1244b6epyfB75ddNX5V4Hxrrz+I//0 0S5ZxqCZUFyHFpX5DYx3zGXSSq2haZta3/k3GEN58VzCKQ5T0BZ0UakRNSd5qFRzf6ay CfjI/AE/oMYa5baLKlssLgTiWLeBBSoIGH/eaMPC3oLSAUF/+oKQF33EMiPDiyRrJ7IN Rp7uy2FtzV97l2gL3u7OGguCDoDMdq4+vz0XP/Kk5v4oeG2JZfWkXFOVCXPNvUbq6HEa JC3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YvqBfV0/i+UB/eECSWLznh7ly4W650zNo1JwoMYaWQ4=; b=ZfIcnO3WwIArfDXnPQOTIWAhL64emUK7SY4M3+55ncyiQXytBI9zzxakcr7MTMGv0p +vBhr+5xdL3gAxSoswk0nolu2YgqCt4vI+Epm/shZYBN7oduUWhTC0QwUHs3Mir4ryHx pen1kV0z7UK2wMfvgNCXNu9oZ6cQmW0fAvsnHtes7L+AKxrAIgd1YxrUmiGla3Tlmfey JniSqdOVy4YkbTrIwGOvTQ7ITi3i9pzsNhVpE/4EHSSkqSEtlliXQ/71BoBWaOMjdq/5 PW701Hd4gZzKJRTMp8RHBgOdsnZ5+PK9t1cuifaW9ztuBs9J03TLvhPjB75g1O3KydOk S/yw== X-Gm-Message-State: APt69E1lleKUZpF1HJ9Lpy1tctSkQuBzT6uZFBmyhyW9gE9qbXXqIM60 KEl8Kk0udfyDDgPF0pyyZddrgz8RSDQ= X-Google-Smtp-Source: ADUXVKLk4PfSDYX5UUpRhMHSjGuM2ak1o8Zdj9XNLL7XT+zqRBkBDf5k+zPPYwQ5TvmuVM6fcfh0qA== X-Received: by 2002:a2e:8350:: with SMTP id l16-v6mr2472808ljh.7.1528880592373; Wed, 13 Jun 2018 02:03:12 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 13 Jun 2018 11:02:51 +0200 Message-Id: <1528880573-29494-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528880573-29494-1-git-send-email-mw@semihalf.com> References: <1528880573-29494-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 2/4] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add new board description file Armada80x0McBin.dsc, which uses common Armada7k8k.fdf file. By default build capsule components. Most of the interfaces are fully functional, except for: - USB ports - it requires merging GPIO support and VBUS power supply enabling - SdMmc ports - they are kept enabled, as no issues were observed on v1.3 board so far. However higher speed modes (HS200) and full stability will be gained after Xenon driver improvements merge. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++= ++++++ 1 file changed, 149 insertions(+) create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc new file mode 100644 index 0000000..8230d67 --- /dev/null +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -0,0 +1,149 @@ +#Copyright (C) 2017 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute = and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modifi= cation, +#are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS I= S" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMP= LIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIAB= LE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DA= MAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVIC= ES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED A= ND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF = THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D Armada80x0McBin + PLATFORM_GUID =3D 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001A + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + CAPSULE_ENABLE =3D TRUE + +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + #MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|3 + + # APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + + # CP110 MPP SET - master + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, = 0x2, 0x2, 0x2, 0xA } + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0= xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # CP110 MPP SET - slave + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0= x8, 0x8, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0= x3, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x= FF, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xF= F, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0 } + + #SPI + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680 + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + + #ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + # ComPhy0 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: PCIE0 5 Gbps + # 3: PCIE0 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SATA1 5 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + # ComPhy1 + # 0: SGMII1 1.25 Gbps + # 1: SATA0 5 Gbps + # 2: USB3_HOST0 5 Gbps + # 3: SATA1 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SGMII2 3.125 Gbps + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), = $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) } + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(C= P_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) } + + #UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + #MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + #PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + #NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI)= , $(PHY_SGMII), $(PHY_SGMII) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + + #PciEmulation + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + + #RTC + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 18:43:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528880601060325.85976884184765; Wed, 13 Jun 2018 02:03:21 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9DDC1212E46EC; Wed, 13 Jun 2018 02:03:17 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1EC6C212E15B0 for ; Wed, 13 Jun 2018 02:03:16 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id v135-v6so2711353lfa.9 for ; Wed, 13 Jun 2018 02:03:16 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q35-v6sm478023lfi.68.2018.06.13.02.03.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Jun 2018 02:03:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LPh7MSaYeDvF098/CZvTuut7tZ5vRGc9RjhXkLyHGo0=; b=ie4bv3o/vtDR/iV0zeeMHSRK+kG1HVq0LdZxz6XdGgx5+hymZKiSLV1BHyZsfNK2RS uBRsORPlm1GyxM6uHtN+AFuF8t+i0zZaXxZMlVaA2TLizzsgyn+GI7rxynT/WKvtxNk3 RlB+XlBtHfGZMVN9GfujGEN2cyq6PnTngQXjLLfnWuJ1aAzJl5ERGfEL8GXgbT8u8pqV dU0SMCaxG/ZvX26rGWkhXK5C1JEkDZMlarxlRUb35L2fpfLgZdmUDSE0rj6O60hke5Z4 SlbV4I6/NX7gM0pD/aqdO5cgqpqiJqIzAAT4g+zY37jEh20pB1PLBKEg0OtiO3NsX1bd o+ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LPh7MSaYeDvF098/CZvTuut7tZ5vRGc9RjhXkLyHGo0=; b=qYlGumcNjxOmW4kbTw8WftfU64OEdDNmhDm2Hj281wOMPBfew76T0ObmSsXRN7QMZD NrL4eFNNuk3dQV9I4+YaMtjYnKj/ZgnlpiVqy0MzuzdynlwIrZFEC1yXUKuULhU+Pcxk VupoeAsyF8+mMLHClf3IA4C+bUh/nKsAIMWYiZ5ua+2bGs8GMjDE245yGCbfR8tkXwvq zMkHWVD9ThqYea0LC+rcF5yQ3pfQiJSyEIrSQNk0EMRRgqusrigMCcqDkjn6Z/C100/c 9CPyCyRoDHLwK7U8ez1WOMv8Keg22YZa4njnUDIs1dkm7sBsxEDbMROxMJ0drP1E5xhz mZOQ== X-Gm-Message-State: APt69E3DC1jIdRtqUSR2ZSpI7D/UuqwjyTiT3HklQpjpFvzKjfMn4JxL U3L7Dju9O3xB1AdskQRiW0yIAux2RcE= X-Google-Smtp-Source: ADUXVKKDzRNUlwlNcH6pN/PRxV40rJrPdXMCEqyt8R6/Pf13JhYKzqTu8DJSWAH6htqsP3Dr4mJ5hg== X-Received: by 2002:a2e:18b:: with SMTP id f11-v6mr2482981lji.83.1528880594047; Wed, 13 Jun 2018 02:03:14 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 13 Jun 2018 11:02:52 +0200 Message-Id: <1528880573-29494-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528880573-29494-1-git-send-email-mw@semihalf.com> References: <1528880573-29494-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 3/4] Marvell/Armada7k8k: Introduce support for Armada-8040-Db X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add new board description file Armada80x0Db.dsc, which uses common Armada7k8k.fdf file. Most of the interfaces are fully functional, except for: - USB ports - it requires merging GPIO support and VBUS power supply enabling Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 158 ++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc new file mode 100644 index 0000000..582e939 --- /dev/null +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -0,0 +1,158 @@ +#Copyright (C) 2017 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute = and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modifi= cation, +#are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS I= S" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMP= LIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIAB= LE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DA= MAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVIC= ES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED A= ND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF = THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D Armada80x0Db + PLATFORM_GUID =3D 5cc803a0-9c42-498e-9086-e176d4a1f598 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001A + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + #MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|3 + + # APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + + # CP110 MPP SET - master + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7, 0x0, 0x7, 0= xA, 0xA, 0x2, 0x2, 0x5 } + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x9, 0x9, 0x8, 0x8, 0x1, 0= x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + + # CP110 MPP SET - slave + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3, 0x3 } + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0x8, 0x9, 0xA } + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0xA, 0x8, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + + # I2C + gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0x57, 0x= 21, 0x25 } + gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, 0x57 } + gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + + #SPI + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680 + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + + #ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + # ComPhy0 + # 0: PCIE0 5 Gbps + # 1: SATA0 5 Gbps + # 2: SFI 10.31 Gbps + # 3: SATA1 5 Gbps + # 4: USB_HOST1 5 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA0), $= (CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_1= 0_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + # ComPhy1 + # 0: PCIE0 5 Gbps + # 1: SATA0 5 Gbps + # 2: SFI 10.31 Gbps + # 3: SATA1 5 Gbps + # 4: PCIE1 5 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA2), $= (CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) } + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= _15625G), $(CP_5G), $(CP_5G), $(CP_5G) } + + #UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + #MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 } + + #PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + #NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SFI), $(PHY_RGMII) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + + #PciEmulation + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + + #RTC + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 18:43:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528880604350765.6966227189745; Wed, 13 Jun 2018 02:03:24 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D720C212E471B; Wed, 13 Jun 2018 02:03:18 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2A01D212E15B0 for ; Wed, 13 Jun 2018 02:03:17 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id n15-v6so2717231lfn.10 for ; Wed, 13 Jun 2018 02:03:17 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q35-v6sm478023lfi.68.2018.06.13.02.03.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Jun 2018 02:03:14 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sjslLEewp/w05zyrt+nGRgt6zr6XhDm1i0OvXgHX7dY=; b=c/wbnSfY6+z8AK4EghhB9PNi1X5hStWTeBIEx1z7PCqOIlL63FtdAHUFWC6kwyctgL L4Ki7liv/ct/UM0Da2igG7uhk7whUJw9UILlQqLDmQFfvTS0uA8z818LIiSgiZDQGduK VH0PabF9hzfxOoWxewoH7A8amEeaBaFdmZ3rgHOQwhjKNBFHVujAwtbSOKHjWKgfURt4 aBOXHUw9xyqqEAIZHZLOjQLoM5fK6uVE31rYakTY91S2+uTd++ErHyP3kARHADjaTvuC wz1GUcvYE9LPV8OCJid6uQ89uULOBtcueqmNyoSBtQRC3/5xGhZJYK848JU53yznMz7R pl6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sjslLEewp/w05zyrt+nGRgt6zr6XhDm1i0OvXgHX7dY=; b=czxlGpYGFe5GVjVv//2F4AMreDN4DXyxsU3JuLSvFPsOd7fRirTvsvPas4li3cIU6O 7RYC77j+pkBdRnnV2MhqrYso5qTl3qvXyA/WX7mLzNizwVyym4gOlHQUfrfqiM6b9hEL aYNESxie+lS+v75ptgq9TT8X2k/SOcBKvSXEqez6qa+zvU60oWnQIhtBofxdr3ZFFdTC 0nqSKMzeLfZ7BRMxNx3OUY1EaAc5XrqX56sW5TBo9kgczwt/K13CNIujIKHkNjXB8Ec+ ZO+X7wYlBUkIoA3OSCvZqOPlpz5yP49NmOvfVLY1gxH37ng+UTb/00WW2Tn5sLLsqf2R nRKw== X-Gm-Message-State: APt69E2hEj/TWX1qd0cTp1obdiws++vvmec7+m2TsfVJmkAOJFlUP7sB uMs8PxA846WixVqPaoTmUPlW1aHAO+Y= X-Google-Smtp-Source: ADUXVKKsqz6LCCbXl/DlvBfsTHpy1ebLaHkl3WdjdVdpKar8HTETkPbchFvinmh7LBBGYcXs45Lc4g== X-Received: by 2002:a2e:2bcb:: with SMTP id r72-v6mr2622570ljr.133.1528880595228; Wed, 13 Jun 2018 02:03:15 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 13 Jun 2018 11:02:53 +0200 Message-Id: <1528880573-29494-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528880573-29494-1-git-send-email-mw@semihalf.com> References: <1528880573-29494-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 4/4] Marvell/Armada70x0Db: Enable building with NOOPT flag X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Newly added boards can build with TARGET set to NOOPT, so align the Armada70x0Db. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index eedb025..68813f8 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -41,7 +41,7 @@ DSC_SPECIFICATION =3D 0x00010005 OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) SUPPORTED_ARCHITECTURES =3D AARCH64|ARM - BUILD_TARGETS =3D DEBUG|RELEASE + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel