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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q35-v6sm478023lfi.68.2018.06.13.02.03.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Jun 2018 02:03:11 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YvqBfV0/i+UB/eECSWLznh7ly4W650zNo1JwoMYaWQ4=; b=Sib8cdHJR1y0+DJhQYHZafNi5i8mBFjFvzAQKkpraXWdXIY1mh8uyBeqiINQymjpeg WeF+jQYS3r4SnSpMI9Ri+Yp+RkB858DK1YgyXa1244b6epyfB75ddNX5V4Hxrrz+I//0 0S5ZxqCZUFyHFpX5DYx3zGXSSq2haZta3/k3GEN58VzCKQ5T0BZ0UakRNSd5qFRzf6ay CfjI/AE/oMYa5baLKlssLgTiWLeBBSoIGH/eaMPC3oLSAUF/+oKQF33EMiPDiyRrJ7IN Rp7uy2FtzV97l2gL3u7OGguCDoDMdq4+vz0XP/Kk5v4oeG2JZfWkXFOVCXPNvUbq6HEa JC3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YvqBfV0/i+UB/eECSWLznh7ly4W650zNo1JwoMYaWQ4=; b=ZfIcnO3WwIArfDXnPQOTIWAhL64emUK7SY4M3+55ncyiQXytBI9zzxakcr7MTMGv0p +vBhr+5xdL3gAxSoswk0nolu2YgqCt4vI+Epm/shZYBN7oduUWhTC0QwUHs3Mir4ryHx pen1kV0z7UK2wMfvgNCXNu9oZ6cQmW0fAvsnHtes7L+AKxrAIgd1YxrUmiGla3Tlmfey JniSqdOVy4YkbTrIwGOvTQ7ITi3i9pzsNhVpE/4EHSSkqSEtlliXQ/71BoBWaOMjdq/5 PW701Hd4gZzKJRTMp8RHBgOdsnZ5+PK9t1cuifaW9ztuBs9J03TLvhPjB75g1O3KydOk S/yw== X-Gm-Message-State: APt69E1lleKUZpF1HJ9Lpy1tctSkQuBzT6uZFBmyhyW9gE9qbXXqIM60 KEl8Kk0udfyDDgPF0pyyZddrgz8RSDQ= X-Google-Smtp-Source: ADUXVKLk4PfSDYX5UUpRhMHSjGuM2ak1o8Zdj9XNLL7XT+zqRBkBDf5k+zPPYwQ5TvmuVM6fcfh0qA== X-Received: by 2002:a2e:8350:: with SMTP id l16-v6mr2472808ljh.7.1528880592373; Wed, 13 Jun 2018 02:03:12 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 13 Jun 2018 11:02:51 +0200 Message-Id: <1528880573-29494-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528880573-29494-1-git-send-email-mw@semihalf.com> References: <1528880573-29494-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 2/4] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add new board description file Armada80x0McBin.dsc, which uses common Armada7k8k.fdf file. By default build capsule components. Most of the interfaces are fully functional, except for: - USB ports - it requires merging GPIO support and VBUS power supply enabling - SdMmc ports - they are kept enabled, as no issues were observed on v1.3 board so far. However higher speed modes (HS200) and full stability will be gained after Xenon driver improvements merge. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++= ++++++ 1 file changed, 149 insertions(+) create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc new file mode 100644 index 0000000..8230d67 --- /dev/null +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -0,0 +1,149 @@ +#Copyright (C) 2017 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute = and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modifi= cation, +#are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS I= S" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMP= LIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIAB= LE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DA= MAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVIC= ES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED A= ND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF = THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D Armada80x0McBin + PLATFORM_GUID =3D 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001A + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + CAPSULE_ENABLE =3D TRUE + +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + #MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|3 + + # APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + + # CP110 MPP SET - master + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, = 0x2, 0x2, 0x2, 0xA } + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0= xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # CP110 MPP SET - slave + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0= x8, 0x8, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0= x3, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x= FF, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xF= F, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0 } + + #SPI + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680 + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + + #ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + # ComPhy0 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: PCIE0 5 Gbps + # 3: PCIE0 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SATA1 5 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + # ComPhy1 + # 0: SGMII1 1.25 Gbps + # 1: SATA0 5 Gbps + # 2: USB3_HOST0 5 Gbps + # 3: SATA1 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SGMII2 3.125 Gbps + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), = $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) } + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(C= P_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) } + + #UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + #MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + #PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + #NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI)= , $(PHY_SGMII), $(PHY_SGMII) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + + #PciEmulation + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + + #RTC + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel