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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:26 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nxOjacw8Yp+vuQuW9SvRLrj5RkbGO8rVJwVGRQLuFv8=; b=LxDYRt9ve0aLA9vIPqSRTT3ip6tmzssLISbRlFt0X5BtrI9Duf89GPDNvQ57gtUCZZ HzqvJE1GLqVdZvrPfOGTbPRV5iQNvoWRvnpJlopbibfguG2FF/4ZLa5oqFy4bT+fuWvi AAPuUefW7ksxBOolOAMyIJUgWvXahtHLUhHqrIBb0h8NdnQO0adSyw6fJAcJ6XL1klrO nE6nfvnbSmDhLmhiEPXUgT/siYRAUEnPf04YxbCfb9SU/amCe/vdgJAAYxcQkDMp7Eox p8r1Hg2Itmq/6VUmwWemzAMcDvZzWX0aEnFo6Tp5b9P5oCU5uvTbGzyIiMuFEvtN8FmE H18Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nxOjacw8Yp+vuQuW9SvRLrj5RkbGO8rVJwVGRQLuFv8=; b=MYGCH57YJ4sZgxooaBl1H/uR+tSbM3g/lZbDny5UomQz2hmDVjq9hUD3pqDoMR535a iDVIYXLzKMDiL2w5U9HQha375Od6CBNDp2n2p2FuJmHNh6UPnrEVxZ4o7BI4+mQL3WJz eLjsamg3nfzLh47fA8X9+J+vMV9EsHfTyVfsDYnvu/cxG8nGAAU7zY17GqAUAiIXy/Mh 37szPSG2Nw093LRvs/zMpcClRATtNd4SdJJRKf+SgCMPqWqcYYnGXB+GYt6AkOY+RNr2 TgcfIBz9wii5Ob0jekRLF/yQPndZc5U3htgv+Bn4pUDAdVxfgrh8sGifITpHOa18RYzM WVIg== X-Gm-Message-State: APt69E3tz7LRsTwiZ/vw38p9EJFSpo2HWYyB4Wo/8X1b5+HTIElVDgV+ 34NxVPsR/A1U+y26sVBldD+CPwBmwFU= X-Google-Smtp-Source: ADUXVKJ4M2OmgCuzUbmAesa6aYX4pnWNuBmsFB8ZZTHeAWTHuDOLX2/y74K6oN7uAqgJvbiUBfF07w== X-Received: by 2002:a2e:9e57:: with SMTP id g23-v6mr6017711ljk.14.1529266347425; Sun, 17 Jun 2018 13:12:27 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:41 +0200 Message-Id: <1529266325-18371-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 01/25] Marvell/Library: Introduce ArmadaSoCDescLib class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua ArmadaSoCDescLib is a per SoC family library, which provides SoC description, like register base of some hardware module controller, COMPHY/I2C/NETWORK etc., which right now is hardcoded in MvHwDescLib.h. There will be a new protocol, which gets SoC description from this library, and provides board description based on enable/disable values of each hardware module controller in dsc file. As a first example implement obtaining UTMI controllers information. Remaining interfaces will be added in follow-up commits. This patch introduces new library callback (ArmadaSoCDescUtmiGet ()), which dynamically allocates and fills MV_SOC_UTMI_DESC structure, SoC description of UTMI PHYs. A new PCD is introduced (PcdMaxCpCount) which stores maximal amount of CP110 blocks in the SoC family. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: jinghua Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Marvell.dec = | 4 ++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.inf | 37 +++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 35 +++++++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 33 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 65 ++++++++++++++++++++ 5 files changed, 174 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.inf create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.h create mode 100644 Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.c diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index be74b4e..2a92eff 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -60,6 +60,7 @@ gMarvellSpiFlashDxeGuid =3D { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, = 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } } =20 [LibraryClasses] + ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h SampleAtResetLib|Include/Library/SampleAtResetLib.h =20 [Protocols] @@ -68,6 +69,9 @@ gMarvellPlatformInitCompleteProtocolGuid =3D { 0x465b8cf7, 0x016f, 0x4ba= 6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } } =20 [PcdsFixedAtBuild.common] +#Board description + gMarvellTokenSpaceGuid.PcdMaxCpCount|0x2|UINT8|0x30000072 + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001 =20 diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLi= b/Armada7k8kSoCDescLib.inf new file mode 100644 index 0000000..2b73b73 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.inf @@ -0,0 +1,37 @@ +## @file +# +# Copyright (C) 2018, Marvell International Ltd. and its affiliates
+# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Armada7k8kDescLib + FILE_GUID =3D c64f0048-4ca3-4573-b0a6-c2e9e6457285 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmadaSoCDescLib + +[Sources] + Armada7k8kSoCDescLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib + PcdLib + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdMaxCpCount diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h new file mode 100644 index 0000000..c5711b0 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -0,0 +1,35 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implemen= tation: +* AP - Application Processor hardware block (Armada 7k8k incorporates AP8= 06) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +**/ + +#ifndef __ARMADA7K8K_SOC_DESC_LIB_H__ +#define __ARMADA7K8K_SOC_DESC_LIB_H__ + +// +// Common macros +// +#define MV_SOC_CP_BASE(Cp) (0xF2000000 + ((Cp) * 0x2000000)) + +// +// Platform description of UTMI PHY's +// +#define MV_SOC_UTMI_PER_CP_COUNT 2 +#define MV_SOC_UTMI_ID(Utmi) (Utmi) +#define MV_SOC_UTMI_BASE(Utmi) (0x580000 + ((Utmi) * 0x1000)) +#define MV_SOC_UTMI_CFG_BASE 0x440440 +#define MV_SOC_UTMI_USB_CFG_BASE 0x440420 + +#endif diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h new file mode 100644 index 0000000..0d45684 --- /dev/null +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -0,0 +1,33 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ +#ifndef __ARMADA_SOC_DESC_LIB_H__ +#define __ARMADA_SOC_DESC_LIB_H__ + +// +// UTMI PHY devices SoC description +// +typedef struct { + UINT8 UtmiPhyId; + UINTN UtmiBaseAddress; + UINTN UtmiConfigAddress; + UINTN UsbConfigAddress; +} MV_SOC_UTMI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescUtmiGet ( + IN OUT MV_SOC_UTMI_DESC **UtmiDesc, + IN OUT UINTN *DescCount + ); +#endif /* __ARMADA_SOC_DESC_LIB_H__ */ diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c new file mode 100644 index 0000000..63fb224 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -0,0 +1,65 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implemen= tation: +* AP - Application Processor hardware block (Armada 7k8k incorporates AP8= 06) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +**/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "Armada7k8kSoCDescLib.h" + +EFI_STATUS +EFIAPI +ArmadaSoCDescUtmiGet ( + IN OUT MV_SOC_UTMI_DESC **UtmiDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_UTMI_DESC *Desc; + UINTN CpCount, CpIndex, Index, UtmiIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *DescCount =3D CpCount * MV_SOC_UTMI_PER_CP_COUNT; + Desc =3D AllocateZeroPool (*DescCount * sizeof (MV_SOC_UTMI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + *UtmiDesc =3D Desc; + + UtmiIndex =3D 0; + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_UTMI_PER_CP_COUNT; Index++) { + Desc->UtmiPhyId =3D MV_SOC_UTMI_ID (UtmiIndex); + Desc->UtmiBaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_BAS= E (Index); + Desc->UtmiConfigAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_C= FG_BASE; + Desc->UsbConfigAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_US= B_CFG_BASE; + Desc++; + UtmiIndex++; + } + } + + return EFI_SUCCESS; +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266357213325.3742234027119; Sun, 17 Jun 2018 13:12:37 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6908B2096FAD5; Sun, 17 Jun 2018 13:12:32 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C1695209605BF for ; Sun, 17 Jun 2018 13:12:30 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id i83-v6so21558471lfh.5 for ; Sun, 17 Jun 2018 13:12:30 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:27 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+lN9UQE+rRm5n1BZPza6g+loU+Hw3BoX8N8yXY24gZ4=; b=xvdZt44GEb2mK+/FffHx3jGEINBGmYOnSMnqy152Hec3aQWbKBOErYTuhc5GzM6rpK SAVvhJGvptjHvtGPB3OAcFRGMNbdXS4SHFC+ds7JIbG3c8p8oOwRKK0duW2OBbGHaFaR EergHdWjP0EX0qU0bgG11kpLe7v2tVFSaXPA+yumNQF/UcLVA+0WZ0Si3EoYcWgd8XW9 zcBrBrRjq0GTniJKrw6eev9tJUsc0p73WiLKVBlhAFyf83NALArT8v3OtgVgaQBFh06D gHowFzTc5RlQSTyFSV7C+T1IgMrfM3/sRUb69Trit9s+gaN8b/iuKZ1VCr0QNwMogNa9 sjAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+lN9UQE+rRm5n1BZPza6g+loU+Hw3BoX8N8yXY24gZ4=; b=t4DfAGCdn8vd2GN8Nmxssj/r97v8dyE5D9421fb9AWgokvpRhfWZTkVEIlBTmhg07c o+xnpcs0lu7fO0R87fNWPIeK7Ajqs3g8Y4yxrZ1C6cXd91lewpjd0f/oOpKP/hK3CIiX Hvt5qY4G53MfOnYJmrmnrnDEKakK+XQPTM+vsQpYKDdJE1sLLZc05sqxuoSC6sHATUcS 96Yby6CxSpAd1xXjijJqRnv+2KCKoN1n/E0Oxmmt4Xu5oEII2gfSDUlo9UhS56emPD0j I04HnyixjYswxZ06MbRb4UW23yjGziL3IegZO5TgmjL66bLy+dRu6p3DhV2PNYLrg3iM 6UNw== X-Gm-Message-State: APt69E2LPA4BoJl5OjjwcTzkKV5Dzy8PhxASXsv7bcRZYSCruzrOR13l GRhXgCbzQa6PIfcuISR3+mOIduDFZi4= X-Google-Smtp-Source: ADUXVKIGRoSjQSQBvLrxqKRbeke+n95QnkHAg4g/5dVy/uNMvbox4FKN7qVzH+nnzMXM/EiZIGyaTw== X-Received: by 2002:a2e:4dcc:: with SMTP id c73-v6mr6129773ljd.135.1529266348880; Sun, 17 Jun 2018 13:12:28 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:42 +0200 Message-Id: <1529266325-18371-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 02/25] Marvell/Library: Introduce ArmadaBoardDescLib class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch adds a new library class that will be helpful to describe a per-board information, which will be processed by BoardDesc protocol. Together with ArmadaSoCDescLib data it will be a flexible solution allowing to provide complete information to the drivers, replacing faulty MvHwDescLib.h. Initially ArmadaBoardDescLib defines per-board UTMI PHYs information structure. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Marvell.dec | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 27 ++++++++++++++++= ++++ 2 files changed, 28 insertions(+) create mode 100644 Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 2a92eff..db49300 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -60,6 +60,7 @@ gMarvellSpiFlashDxeGuid =3D { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, = 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } } =20 [LibraryClasses] + ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h SampleAtResetLib|Include/Library/SampleAtResetLib.h =20 diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h new file mode 100644 index 0000000..068535a --- /dev/null +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -0,0 +1,27 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ +#ifndef __ARMADA_BOARD_DESC_LIB_H__ +#define __ARMADA_BOARD_DESC_LIB_H__ + +#include + +// +// UTMI PHY devices per-board description +// +typedef struct { + MV_SOC_UTMI_DESC *SoC; + UINTN UtmiDevCount; + UINTN UtmiPortType; +} MV_BOARD_UTMI_DESC; +#endif /* __ARMADA_SOC_DESC_LIB_H__ */ --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266365342417.45060974457897; Sun, 17 Jun 2018 13:12:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C1DD12096FADF; Sun, 17 Jun 2018 13:12:35 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 10401209605C7 for ; Sun, 17 Jun 2018 13:12:33 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id y20-v6so21586295lfy.0 for ; Sun, 17 Jun 2018 13:12:33 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:29 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oot0NebwYefIIx2VwG3tr0hQB6bKe5u5G569MyD3GA0=; b=afOpIVnGdVj6NH7Kyad79TVI4/2h05GNoun1g86eWnj9OY74r9RLSgR/YQ3LPsuUr6 ntvaY3zJwa9AFfFeZTulryYuU9yX6D0lplvy1j2nAkSxLSix5Lpe1bIpFCQqbhZ6zToP LlZ2RV1+f+vCgOG/l4IjD8qBcdwF9gojFYqPFUI+6xSxvdmY3aD6/iqpEl1nAADiXV5b oCECdftDtNMgXx2K1j5/KRNRmcgyhLv9lWSXk3363oJp1sDyl4aEMBEd3+3qjok9BBiF eN/EdiV0PdnowY1+si6H0JctZT5KPehdrROW/1TXI+kiN75v0ezzlamG5SCe514vJgsF 22lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oot0NebwYefIIx2VwG3tr0hQB6bKe5u5G569MyD3GA0=; b=QSqN5d2uI9PpPhIlsLDsOajN3Ov8BjkVZvVoeOPAtbblju9+Com25yv9+PPME6y/lF EhH8wXTxpcUS6ig0oa0w0V06dwEEYzRQRO2yZNtM2a2X4G04D3mGZhduomG4PtteeVJH 4gDEBwQmxu1+5wkZpbsbxH37VPAGmqWqWnT9CkaaY3Oj3xc+KOniO56m2beHMEM3Aj5w 4+GbP8/iAaCwdhJ6HeVkGnbmsKoAb4FpNqS0iOOFCww4GgdN389ua81fp4bv3MNbSDtN Y6o6yDNFAbXBM0lTdUlVbwu+fu2K878Wcip8PrC0KimCQY7IdHGQnQdqRcfYYIHqocrO OfvA== X-Gm-Message-State: APt69E0CE8uHzT3mP1zgnf/BDDQGMeF0ZSSkS9nnlE06PelljuDcceP9 TRnK9EEN73QV085zlNoBFfR//PZuGTE= X-Google-Smtp-Source: ADUXVKIp0+5jC0eBL+bolb0md7oz4jGsFh5HTlQQQH62ELOw1LRk/x9KFtk2QCBlltspXSWnCzVi8g== X-Received: by 2002:a2e:1155:: with SMTP id f82-v6mr6106317lje.75.1529266350063; Sun, 17 Jun 2018 13:12:30 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:43 +0200 Message-Id: <1529266325-18371-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 03/25] Marvell: Introduce MARVELL_BOARD_DESC_PROTOCOL X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua This patch introduces protocol that exposes generic API to get board description. It uses ArmadaSoCDescLib library, which is implemented per SoC family to get the SoC level description for hardware module controller. Together with the information obtained from ArmadaBoardDescLib the protocol allows the drivers to get per-board information about used hardware and settings. As a first usage a UTMI information obtaining is implemented. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: jinghua Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Marvell.dec | 1 + Silicon/Marvell/Include/Protocol/BoardDesc.h | 62 ++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 Silicon/Marvell/Include/Protocol/BoardDesc.h diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index db49300..6861cc4 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -212,6 +212,7 @@ gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0|UINT32|0x50000001 =20 [Protocols] + gMarvellBoardDescProtocolGuid =3D { 0xebed8738, 0xd4a6, 0x400= 1, { 0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }} gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} gMarvellPhyProtocolGuid =3D { 0x32f48a43, 0x37e3, 0x4ac= f, { 0x93, 0xc4, 0x3e, 0x57, 0xa7, 0xb0, 0xfb, 0xdc }} diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h new file mode 100644 index 0000000..f8a2902 --- /dev/null +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -0,0 +1,62 @@ +/*************************************************************************= ****** +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ +#ifndef __MARVELL_BOARD_DESC_PROTOCOL_H__ +#define __MARVELL_BOARD_DESC_PROTOCOL_H__ + +#include +#include + +extern EFI_GUID gMarvellBoardDescProtocolGuid; + +typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOARD_DESC_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_UTMI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_UTMI_DESC **UtmiDesc + ); + +typedef +VOID +(EFIAPI *MV_BOARD_DESC_FREE) ( + IN VOID *BoardDesc + ); + +struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; + MV_BOARD_DESC_FREE BoardDescFree; +}; + +#endif // __MARVELL_BOARD_DESC_PROTOCOL_H__ --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266361081695.6065618516064; Sun, 17 Jun 2018 13:12:41 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 94DBC2096FADA; Sun, 17 Jun 2018 13:12:34 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3D665209605C7 for ; Sun, 17 Jun 2018 13:12:33 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id p23-v6so9859789lfh.11 for ; Sun, 17 Jun 2018 13:12:33 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:30 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OX506bKF0y6Un0Dq3tLGxcjtvYVs/ZxFA6HsOmmjtHo=; b=bKSXtVnTDimfsNrcL/XOK0l4LkMQzvle2mGSmg08X38mfbRSlwD4TJcl0AcTYgKM6T yvLwKM57HfR7MN6/TT7w0Q394JByYJxj/tz6sOmntPq5PbrKBeXBKYoKKRxUJL7JAPnF 0tGfZj+ms8sbQpgxpMSHP6OZT/acyH755eIPb0AVjtLb0j2/vF/MWeFf+J30HliWpdNT XvQe5IWehxTS9QyTnp5b9y3Ip22vC+ss3/trz3J1xyLX0cydBy/8p5dPSdZ4DctGIhsS EEtXrtcwENIRxYgre/yR8uKKpXvOfQJUnMpnOOJXdi2DzaYdX66Vj9CE1ZzLUS04RsNy Ss7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OX506bKF0y6Un0Dq3tLGxcjtvYVs/ZxFA6HsOmmjtHo=; b=FIbya94qmZeWpmM6WGdX8TmXMurNgALyrecZK5CGhwKUwcrrWvss4cdzoqj2NNMyJx xGqJKjg7kT6LNkces3YzhKf30N4tANe6bogslXh2I5MkVJFtl3tkfdd4V1b2iI7yBB8B oHyemC80R0q9gKFrJ6Iex7q+wa0EJMWfMy/95rC0Uw5COEi05p+rH2jVYM41/akx59JG qoG8Coghu+R/83mfFDn36pOJQRy7Tvo0xOVsrR02VZPYwaXb8+4M3V5UV3KVdI6I+/Kr GFlm20cZpcUGwHS3GYIOLU5Y/W2XuuWL+FyreVsVSOv9OZidQl0ijKASQuYEn7akhlc/ fT3A== X-Gm-Message-State: APt69E1w8LbMEEADs9ZEbdsd0YS6uc9rXfysvmpQAWshCmBNO9v4IFva XpjK9ZZ992bzXe3wmRHQaBgHi/vTO0s= X-Google-Smtp-Source: ADUXVKLRnLmo99eY49WuJqmQpvBeOwy0gSK0DT0eYAdMMDLRuuhTEBxQAm7T783b2J1QSOAHESrCrA== X-Received: by 2002:a2e:1414:: with SMTP id u20-v6mr6535390ljd.134.1529266351248; Sun, 17 Jun 2018 13:12:31 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:44 +0200 Message-Id: <1529266325-18371-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 04/25] Marvell/Drivers: MvBoardDesc: Introduce board description driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua This patch introduces a producer of MARVELL_BOARD_DESC_PROTOCOL, which gets SoC description from ArmadaSoCDescLib, then based on dsc file, provide only enabled hardware module controllers for the consumers, which are typically controllers' drivers. Thanks to that there is a separation between obtaining the platform description and the drivers. A first example of the board description callback is information about UTMI controllers and type. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: jinghua Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 65 ++++++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h | 57 +++++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 176 +++++++++++++++= +++++ 3 files changed, 298 insertions(+) create mode 100644 Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf create mode 100644 Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h create mode 100644 Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf new file mode 100644 index 0000000..5da5f21 --- /dev/null +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -0,0 +1,65 @@ +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute +# and/or modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are m= et: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS = IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPO= SE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIA= BLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTI= AL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS = OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEV= ER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABI= LITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF TH= E USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D BoardDescDxe + FILE_GUID =3D 4ed385f9-5d2c-4774-95c5-d5d9d70b3c37 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D MvBoardDescEntryPoint + +[Sources] + MvBoardDescDxe.c + MvBoardDescDxe.h + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + ArmadaSoCDescLib + DebugLib + MemoryAllocationLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gMarvellBoardDescProtocolGuid + +[Pcd] + gMarvellTokenSpaceGuid.PcdPciEXhci + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled + gMarvellTokenSpaceGuid.PcdUtmiPortType + +[Depex] + TRUE diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.h new file mode 100644 index 0000000..2813f0d --- /dev/null +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h @@ -0,0 +1,57 @@ +/*************************************************************************= ****** +Copyright (C) 2018 Marvell International Ltd. +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ +#ifndef __MV_BOARD_DESC_H__ +#define __MV_BOARD_DESC_H__ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define MV_BOARD_DESC_SIGNATURE SIGNATURE_64 ('M', 'V', 'B', 'R', 'D', 'D'= , 'S', 'C') + +typedef struct { + MARVELL_BOARD_DESC_PROTOCOL BoardDescProtocol; + UINTN Signature; + EFI_HANDLE Handle; + EFI_LOCK Lock; +} MV_BOARD_DESC; + +#endif // __MV_BOARD_DESC_H__ diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c new file mode 100644 index 0000000..0232a21 --- /dev/null +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -0,0 +1,176 @@ +/*************************************************************************= ****** +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ +#include "MvBoardDescDxe.h" + +MV_BOARD_DESC *mBoardDescInstance; + +STATIC +EFI_STATUS +MvBoardDescUtmiGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_UTMI_DESC **UtmiDesc + ) +{ + UINT8 *UtmiDeviceEnabled, *XhciDeviceEnabled, *UtmiPortType; + UINTN UtmiCount, UtmiDeviceTableSize, UtmiIndex, Index; + MV_BOARD_UTMI_DESC *BoardDesc; + MV_SOC_UTMI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available UTMI controllers */ + Status =3D ArmadaSoCDescUtmiGet (&SoCDesc, &UtmiCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled Utmi PHY's, + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + UtmiDeviceEnabled =3D PcdGetPtr (PcdUtmiControllersEnabled); + if (UtmiDeviceEnabled =3D=3D NULL) { + /* No UTMI PHY on platform */ + return EFI_SUCCESS; + } + + /* Make sure XHCI controllers table is present */ + XhciDeviceEnabled =3D PcdGetPtr (PcdPciEXhci); + if (XhciDeviceEnabled =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Missing PcdPciEXhci\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + UtmiDeviceTableSize =3D PcdGetSize (PcdUtmiControllersEnabled); + + /* Check if PCD with UTMI PHYs is correctly defined */ + if ((UtmiDeviceTableSize > UtmiCount) || + (UtmiDeviceTableSize > PcdGetSize (PcdPciEXhci))) { + DEBUG ((DEBUG_ERROR, + "%a: Wrong PcdUtmiControllersEnabled format\n", + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Obtain port type table - also stored as UINT8 array */ + UtmiPortType =3D PcdGetPtr (PcdUtmiPortType); + if ((UtmiPortType =3D=3D NULL) || + (PcdGetSize (PcdUtmiPortType) !=3D UtmiDeviceTableSize)) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdUtmiPortType format\n", __FUNCTION_= _)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (UtmiDeviceTableSize * sizeof (MV_BOARD_U= TMI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + UtmiIndex =3D 0; + for (Index =3D 0; Index < UtmiDeviceTableSize; Index++) { + if (!UtmiDeviceEnabled[Index]) { + continue; + } + + /* UTMI PHY without enabled XHCI controller is useless */ + if (!XhciDeviceEnabled[Index]) { + DEBUG ((DEBUG_ERROR, + "%a: Disabled Xhci controller %d\n", + Index, + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + BoardDesc[UtmiIndex].SoC =3D &SoCDesc[Index]; + BoardDesc[UtmiIndex].UtmiPortType =3D UtmiPortType[Index]; + UtmiIndex++; + } + + BoardDesc->UtmiDevCount =3D UtmiIndex; + + *UtmiDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +VOID +MvBoardDescFree ( + IN VOID *BoardDesc + ) +{ + FreePool (BoardDesc); +} + +STATIC +EFI_STATUS +MvBoardDescInitProtocol ( + IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol + ) +{ + BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; + BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvBoardDescEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mBoardDescInstance =3D AllocateZeroPool (sizeof (MV_BOARD_DESC)); + if (mBoardDescInstance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + MvBoardDescInitProtocol (&mBoardDescInstance->BoardDescProtocol); + + mBoardDescInstance->Signature =3D MV_BOARD_DESC_SIGNATURE; + + Status =3D gBS->InstallMultipleProtocolInterfaces (&(mBoardDescInstance-= >Handle), + &gMarvellBoardDescProtocolGuid, + &(mBoardDescInstance->BoardDescProtocol)); + if (EFI_ERROR (Status)) { + FreePool (mBoardDescInstance); + return Status; + } + + return EFI_SUCCESS; +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266370038754.9545767122108; Sun, 17 Jun 2018 13:12:50 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EE05920971732; Sun, 17 Jun 2018 13:12:35 -0700 (PDT) Received: from mail-lf0-x235.google.com (mail-lf0-x235.google.com [IPv6:2a00:1450:4010:c07::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 78FE32096FACF for ; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:31 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::235; helo=mail-lf0-x235.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kU5Kd8gvrOs+69UVdMpwE4UznithCZszW62QEu6YV3U=; b=QaTFEOyUmPkx1FFZyq3A8aM17XpvYcfmj0onvM0mLFuY9ObgvdgxWz46YCSUv5Mc7W oiRYCicamU9sFEUawupLRhzjw3TfEaMf7vaodISMuObinzGUwp/nYdSk2ujALVY0p/cw Ynz3vK34V2AH7B47pU3Gp4sx5efOIXe5/tQc0KToSs/nB2o8VAoWCQ6wENUPpIM/S7mX xMo5qd6m5bAh5unkKtF2hyWVFHGOFD7X6rlt4QdHwkbmzWRURh2Pl3QKzHO1dU8Lhnxh 2YCkVnHu7tIBFbMlFgpBLv6jZAXWf1NRp436twJ6Jed0v191TH9GMsCKwOQOZFlNrA14 YFig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kU5Kd8gvrOs+69UVdMpwE4UznithCZszW62QEu6YV3U=; b=BZP0zP0KJfjGmeSPt2YQvjU4zVt8LJNjl2rX63cSzgJdJ6TW39biQiTQNZCOjK26Ry zA3VLoZuC74gNbHqnmI5G0I1KGuaO+3G/dvXBoafloyLvHsXSMSxlJ5VqRYa2X5+M9Xw vWEMG5lxkjqrHcATxT5xYvz0Levn5MQa9V/h6FqyECIruN228yYKzkLUiQ0C7iayef0a al2x/bfEwAXc3Uc1HaQgLMiAXWHtWS9V8TXX82ZJAXDCQhC478nFuCfks6fyhgNjllio gVgrS6A+fn8s1qy6nQ+jkuuELD7VneOU3F4IIRkoYJL5Ilmi3jwm1QJ3Ucom07nGvU44 Oadg== X-Gm-Message-State: APt69E2Q/DalWrlf1+AhzExRazd+aF0c4M6S8rdO04NwjPRD7cl1MAuk traW1mkwkhMAyA6ucwQEkqFU3LJVwDo= X-Google-Smtp-Source: ADUXVKKdmfysR/6Ae7IrNU9OecCVBvaz2GDY0osA4MK3SaEUZS35VQX0bmYE8iXYxc6i/tRhwE5chw== X-Received: by 2002:a2e:575c:: with SMTP id r28-v6mr6007574ljd.51.1529266352527; Sun, 17 Jun 2018 13:12:32 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:45 +0200 Message-Id: <1529266325-18371-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 05/25] Marvell/Armada7k8k: Enable board description driver compilation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua This patch enables compilation of MvBoardDescDxe driver for Armada70x0-DB, Armada80x0-DB and Armada80x0McBin. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: jinghua Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 2 ++ Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 1 + 2 files changed, 3 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index 75fa3d4..a9d67a2 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -32,6 +32,7 @@ #SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # [LibraryClasses.common] + ArmadaSoCDescLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.inf ArmPlatformLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k= 8kLib.inf ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf MppLib|Silicon/Marvell/Library/MppLib/MppLib.inf @@ -449,6 +450,7 @@ ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf =20 # Platform Initialization + Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf =20 # Platform drivers diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Ar= mada7k8k/Armada7k8k.fdf index 180b6c9..18d5d06 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -106,6 +106,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c # # Platform Initialization # + INF Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf INF Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf =20 # PI DXE Drivers producing Architectural Protocols (EFI Services) --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266373548893.1367690411537; Sun, 17 Jun 2018 13:12:53 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 241392096FACF; Sun, 17 Jun 2018 13:12:38 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C15902096FADD for ; Sun, 17 Jun 2018 13:12:35 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id y20-v6so21586420lfy.0 for ; Sun, 17 Jun 2018 13:12:35 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:33 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TAtE7VEjUKzZp16sVpTG1jivhBdQ7OZzl6m6Mkwnpao=; b=JKw6TkjskKf0VXJ+3cCMJVKEnY+nLVQONbsh6woWgQ1V+hmz1+e5/H8prPBL2MyvFr LF13LZgqJ5JyCOKJL84GsBsLBDMBEGiQV4m2ex1DP2PzBg/m0q0iweJ8ghfd7q2rtFQG rpdDcslzAb8n70rTPXM6RNGuj5NkRl6SeSzUG17pa1+qP6T8K5eqQ+2PRhL3nizxbpd2 SwAhtDEQFLezVHB97NCGVmjabbXgwmYI3NfNDCDLTVtqgZuzE4jTuW182p+F0pkBTBkB G6Peni/uuNGXLOs8RQEsYAt3b2JpR/btseQegL71fW3Q0EATLON81Xe9pgMyoR26V0d2 qY3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TAtE7VEjUKzZp16sVpTG1jivhBdQ7OZzl6m6Mkwnpao=; b=jV114qk/6fGWN85+MbC4c7h9A10tv+lH4M/iHCVem5yaAIwm47suCnnCVygeUVG7Dv B/nEEj8+hgM9LmR5ebA4UBUYlOSWy81f8aW6qxrCSVOE1vhtl63P4OlGLlcj3FqwsRut k+exXSAhRCOuSE5f2FeUIM2zg9ayoqE5kKwQPkroNpAwazGi61G60O/5yMYrdU2WhECn 2PipN6gmWYODU1016DUBSuZJPo5/ys8nmhw+T2jV6PU8fcVviv7BC078qDncqIyUyMLK 6ggyYE1Yxdm0q5igflAnoJQ4q0/TlCsaeqyGYCxYvWP0x0IpjDLJbU88UY1KtxNVvNr/ bT4w== X-Gm-Message-State: APt69E0GjDkraIQLjEfj1I275tboUphYrKhJI0poJlvw8eIg1kl9zO2a XxUAG/EMuvbc5q99mdfMHhBp61dzv4c= X-Google-Smtp-Source: ADUXVKLL5DWeC4Jj0VHC9WmqxgTJuIukRB3jr2DjCQHXPlmKii2Fx4n6RoXBJrvACjZXGJU5wD6ffA== X-Received: by 2002:a2e:4d0e:: with SMTP id a14-v6mr6567837ljb.106.1529266353747; Sun, 17 Jun 2018 13:12:33 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:46 +0200 Message-Id: <1529266325-18371-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 06/25] Marvell/Library: UtmiPhyLib: Switch to use MARVELL_BOARD_DESC protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" UTMI driver used to get Armada7k8k UTMI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get UTMI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Use the protocol and pass information to further to the library init routine. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 - Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 9 ++- Silicon/Marvell/Include/Library/MvHwDescLib.h | 47 --= ------------ Silicon/Marvell/Include/Library/UtmiPhyLib.h | 2 + Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 5 ++ Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 65 ++= +++++------------- 6 files changed, 32 insertions(+), 97 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index d38b467..f2c173c 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -51,7 +51,6 @@ DebugLib MemoryAllocationLib MppLib - UtmiPhyLib =20 [Sources.common] Armada7k8kLib.c diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf b/Silicon/Ma= rvell/Library/UtmiPhyLib/UtmiPhyLib.inf index 0876879..e2381f4 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf @@ -51,11 +51,10 @@ IoLib MemoryAllocationLib PcdLib + UefiBootServicesTableLib + +[Protocols] + gMarvellBoardDescProtocolGuid ## CONSUMES =20 [Sources.common] UtmiPhyLib.c - -[Pcd] - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled - gMarvellTokenSpaceGuid.PcdUtmiPortType - gMarvellTokenSpaceGuid.PcdPciEXhci diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 9ae03d0..e13814a 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -127,19 +127,6 @@ typedef struct { } MVHW_RTC_DESC; =20 // -// UTMI PHY's description template definition -// - -typedef struct { - UINT8 UtmiDevCount; - UINT32 UtmiPhyId[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiBaseAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiConfigAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiUsbConfigAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiMuxBitCount[MVHW_MAX_XHCI_DEVS]; -} MVHW_UTMI_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -253,38 +240,4 @@ MVHW_RTC_DESC mA7k8kRtcDescTemplate =3D {\ { SIZE_4KB, SIZE_4KB }\ } =20 -// -// Platform description of UTMI PHY's -// -#define MVHW_CP0_UTMI0_BASE 0xF2580000 -#define MVHW_CP0_UTMI0_CFG_BASE 0xF2440440 -#define MVHW_CP0_UTMI0_USB_CFG_BASE 0xF2440420 -#define MVHW_CP0_UTMI0_ID 0x0 -#define MVHW_CP0_UTMI1_BASE 0xF2581000 -#define MVHW_CP0_UTMI1_CFG_BASE 0xF2440444 -#define MVHW_CP0_UTMI1_USB_CFG_BASE 0xF2440420 -#define MVHW_CP0_UTMI1_ID 0x1 -#define MVHW_CP1_UTMI0_BASE 0xF4580000 -#define MVHW_CP1_UTMI0_CFG_BASE 0xF4440440 -#define MVHW_CP1_UTMI0_USB_CFG_BASE 0xF4440420 -#define MVHW_CP1_UTMI0_ID 0x0 -#define MVHW_CP1_UTMI1_BASE 0xF4581000 -#define MVHW_CP1_UTMI1_CFG_BASE 0xF4440444 -#define MVHW_CP1_UTMI1_USB_CFG_BASE 0xF4440420 -#define MVHW_CP1_UTMI1_ID 0x1 - -#define DECLARE_A7K8K_UTMI_TEMPLATE \ -STATIC \ -MVHW_UTMI_DESC mA7k8kUtmiDescTemplate =3D {\ - 4,\ - { MVHW_CP0_UTMI0_ID, MVHW_CP0_UTMI1_ID,\ - MVHW_CP1_UTMI0_ID, MVHW_CP1_UTMI1_ID },\ - { MVHW_CP0_UTMI0_BASE, MVHW_CP0_UTMI1_BASE,\ - MVHW_CP1_UTMI0_BASE, MVHW_CP1_UTMI1_BASE },\ - { MVHW_CP0_UTMI0_CFG_BASE, MVHW_CP0_UTMI1_CFG_BASE,\ - MVHW_CP1_UTMI0_CFG_BASE, MVHW_CP1_UTMI1_CFG_BASE },\ - { MVHW_CP0_UTMI0_USB_CFG_BASE, MVHW_CP0_UTMI1_USB_CFG_BASE,\ - MVHW_CP1_UTMI0_USB_CFG_BASE, MVHW_CP1_UTMI1_USB_CFG_BASE }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Include/Library/UtmiPhyLib.h b/Silicon/Marvell= /Include/Library/UtmiPhyLib.h index 7c62cba..6f4e355 100644 --- a/Silicon/Marvell/Include/Library/UtmiPhyLib.h +++ b/Silicon/Marvell/Include/Library/UtmiPhyLib.h @@ -35,6 +35,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __UTMIPHYLIB_H__ #define __UTMIPHYLIB_H__ =20 +#include + EFI_STATUS UtmiPhyInit ( VOID diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/Marv= ell/Library/UtmiPhyLib/UtmiPhyLib.h index 0d7d72e..7e56f1a 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h @@ -35,6 +35,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __UTMIPHY_H__ #define __UTMIPHY_H__ =20 +#include + #include #include #include @@ -42,6 +44,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include + +#include =20 #define UTMI_USB_CFG_DEVICE_EN_OFFSET 0 #define UTMI_USB_CFG_DEVICE_EN_MASK (0x1 << UTMI_USB_CFG_DEV= ICE_EN_OFFSET) diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marv= ell/Library/UtmiPhyLib/UtmiPhyLib.c index 2cd9cfa..cef1279 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c @@ -33,9 +33,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. **************************************************************************= *****/ =20 #include "UtmiPhyLib.h" -#include - -DECLARE_A7K8K_UTMI_TEMPLATE; =20 typedef struct { EFI_PHYSICAL_ADDRESS UtmiBaseAddr; @@ -288,67 +285,47 @@ UtmiPhyInit ( VOID ) { + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_UTMI_DESC *BoardDesc; UTMI_PHY_DATA UtmiData; - UINT8 *UtmiDeviceTable, *XhciDeviceTable, *UtmiPortType, Index; - MVHW_UTMI_DESC *Desc =3D &mA7k8kUtmiDescTemplate; - - /* Obtain table with enabled Utmi PHY's*/ - UtmiDeviceTable =3D (UINT8 *)PcdGetPtr (PcdUtmiControllersEnabled); - if (UtmiDeviceTable =3D=3D NULL) { - /* No UTMI PHY on platform */ - return EFI_SUCCESS; - } - - if (PcdGetSize (PcdUtmiControllersEnabled) > MVHW_MAX_XHCI_DEVS) { - DEBUG ((DEBUG_ERROR, "UTMI: Wrong PcdUtmiControllersEnabled format\n")= ); - return EFI_INVALID_PARAMETER; - } + EFI_STATUS Status; + UINTN Index; =20 - /* Make sure XHCI controllers table is present */ - XhciDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciEXhci); - if (XhciDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "UTMI: Missing PcdPciEXhci\n")); - return EFI_INVALID_PARAMETER; + /* Obtain board description */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } =20 - /* Obtain port type table */ - UtmiPortType =3D (UINT8 *)PcdGetPtr (PcdUtmiPortType); - if (UtmiPortType =3D=3D NULL || - PcdGetSize (PcdUtmiPortType) !=3D PcdGetSize (PcdUtmiControllersEnab= led)) { - DEBUG ((DEBUG_ERROR, "UTMI: Wrong PcdUtmiPortType format\n")); - return EFI_INVALID_PARAMETER; + Status =3D BoardDescProtocol->BoardDescUtmiGet (BoardDescProtocol, &Boar= dDesc); + if (EFI_ERROR (Status)) { + return Status; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdUtmiControllersEnabled); Index+= +) { - if (!MVHW_DEV_ENABLED (Utmi, Index)) { - continue; - } - - /* UTMI PHY without enabled XHCI controller is useless */ - if (!MVHW_DEV_ENABLED (Xhci, Index)) { - DEBUG ((DEBUG_ERROR, "UTMI: Disabled Xhci controller %d\n", Index)); - return EFI_INVALID_PARAMETER; - } - + for (Index =3D 0; Index < BoardDesc->UtmiDevCount; Index++) { /* Get base address of UTMI phy */ - UtmiData.UtmiBaseAddr =3D Desc->UtmiBaseAddresses[Index]; + UtmiData.UtmiBaseAddr =3D BoardDesc[Index].SoC->UtmiBaseAddress; =20 /* Get usb config address */ - UtmiData.UsbCfgAddr =3D Desc->UtmiUsbConfigAddresses[Index]; + UtmiData.UsbCfgAddr =3D BoardDesc[Index].SoC->UsbConfigAddress; =20 /* Get UTMI config address */ - UtmiData.UtmiCfgAddr =3D Desc->UtmiConfigAddresses[Index]; + UtmiData.UtmiCfgAddr =3D BoardDesc[Index].SoC->UtmiConfigAddress; =20 /* Get UTMI PHY ID */ - UtmiData.PhyId =3D Desc->UtmiPhyId[Index]; + UtmiData.PhyId =3D BoardDesc[Index].SoC->UtmiPhyId; =20 /* Get the usb port type */ - UtmiData.UtmiPhyPort =3D UtmiPortType[Index]; + UtmiData.UtmiPhyPort =3D BoardDesc[Index].UtmiPortType; =20 /* Currently only Cp110 is supported */ Cp110UtmiPhyInit (&UtmiData); } =20 + BoardDescProtocol->BoardDescFree (BoardDesc); + return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:34 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::230; helo=mail-lf0-x230.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xnONXDCn3YY9eWDSQ1sDzbqHt9ZFBilN3//e9F1/318=; b=Rw/ri47dBtgWOwv5deTgKX2sHnHFF7rrP7q7rBzsZRATJKH77Oxz+qdujYEwU7O+cd dLuaJmF8i2sFemATe69+zFKUZQQyqbaCnmMJKm2TGCvpywP1iIRGVohx0cccVzLDNXRA nDCf7FmDKSRnl5BlqjU7aKBIgOyQn1LJlRyhu8W5BZSs25PNxI6ELi9J/PRcV26Ga5fY uuwT2Spcgm4jraAtMxTj1jOtwEmOq2OGkDJUs49pO0ruRhyJcN2TZhfB9qrnsFwZ6yJd NNBu/AiLzF0Jg9r3DiVwbp8xmB54VGeFUW5zOCL1Hax6dIpXrHmd/IZUyKTXGEalftjW W8nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xnONXDCn3YY9eWDSQ1sDzbqHt9ZFBilN3//e9F1/318=; b=FyYPD3U6TyvfVwnSvlQJ71gEcNdNiilYk+xLMCV5oP4U+/1n3joygHo2NrihDMmrQ5 VGGeLnyRUK5Py5oM/PZpQqNhSucoANPlC0mFJt5BX2wlSiiSxvq/WP4rQgPeNA7HVjsb Johzw8EEVM4NXNbOvgS85/W5erJ4fXMakdJb1rZ4nLii9naNAP+WlKJ7jTEiOWy671r8 rzgnUnnpfLJHM8y0gQPDYY3OVXqP7FaFn6AQGtVIGsuUR73V3udo3mAd9H8uGT5H7Akp QU9S3CqruXhWUbkOKV4ePfJzKaGnoYF1wInq/sovhGodPpte6M9uX1GFam4+R1SoQQqL lhuw== X-Gm-Message-State: APt69E26u532Yj3VH+zD9fe0nH39G0FxI3j5w0VjCeqn4/SCjurvcgBY HW8B5qFGLslCKTyo5nTNn6b3W20ODj8= X-Google-Smtp-Source: ADUXVKKAIxdXi794Hkgv1L+6qjVQKxWy+3fEry+i7DVGl8OhaNxsLKUhok4sd5WeFsRq7ga/Gwu9Cg== X-Received: by 2002:a2e:944e:: with SMTP id o14-v6mr6138153ljh.118.1529266355062; Sun, 17 Jun 2018 13:12:35 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:47 +0200 Message-Id: <1529266325-18371-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 07/25] Marvell/Library: RealTimeClockLib: Simplify obtaining base address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Hitherto mechanism of obtaining RTC base address proved to be not flexible enough to support more than one SoC family. Because there can be a single controller in use anyway, this patch drops utilization of MvHwDescLib header with hardcoded structure and replace it with simple UINT64 PCD. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Marvell.dec |= 2 +- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc |= 2 +- Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc |= 2 +- Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc |= 2 +- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.inf |= 2 +- Silicon/Marvell/Include/Library/MvHwDescLib.h |= 25 ----------------- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c |= 29 ++++---------------- 7 files changed, 11 insertions(+), 53 deletions(-) diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 6861cc4..4def897 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -195,7 +195,7 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT64|0x40000052 =20 #TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 68813f8..5ccee1b 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -134,4 +134,4 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x1 } + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc index 582e939..2425c45 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -155,4 +155,4 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000 diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc index 8230d67..1baed88 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -146,4 +146,4 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000 diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.inf b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.inf index 59c71c4..1ecd444 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.= inf +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.= inf @@ -49,7 +49,7 @@ gEfiEventVirtualAddressChangeGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdRtcEnabled + gMarvellTokenSpaceGuid.PcdRtcBaseAddress =20 [Depex.common.DXE_RUNTIME_DRIVER] gEfiCpuArchProtocolGuid diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index e13814a..34d03d4 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -116,17 +116,6 @@ typedef struct { } MVHW_PP2_DESC; =20 // -// RealTimeClock devices description template definition -// -#define MVHW_MAX_RTC_DEVS 2 - -typedef struct { - UINT8 RtcDevCount; - UINTN RtcBaseAddresses[MVHW_MAX_RTC_DEVS]; - UINTN RtcMemSize[MVHW_MAX_RTC_DEVS]; -} MVHW_RTC_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -226,18 +215,4 @@ MVHW_PP2_DESC mA7k8kPp2DescTemplate =3D {\ { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \ } =20 -// -// Platform description of RealTimeClock devices -// -#define MVHW_CP0_RTC0_BASE 0xF2284000 -#define MVHW_CP1_RTC0_BASE 0xF4284000 - -#define DECLARE_A7K8K_RTC_TEMPLATE \ -STATIC \ -MVHW_RTC_DESC mA7k8kRtcDescTemplate =3D {\ - 2,\ - { MVHW_CP0_RTC0_BASE, MVHW_CP1_RTC0_BASE },\ - { SIZE_4KB, SIZE_4KB }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.c b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCloc= kLib.c index d671b6a..087bd9a 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -34,7 +33,6 @@ #include #include "RealTimeClockLib.h" =20 -DECLARE_A7K8K_RTC_TEMPLATE; STATIC EFI_EVENT mRtcVirtualAddrChangeEvent; STATIC UINTN mArmadaRtcBase; =20 @@ -216,28 +214,13 @@ LibRtcInitialize ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_RTC_DESC *Desc =3D &mA7k8kRtcDescTemplate; - UINT8 *RtcDeviceTable, Index; EFI_HANDLE Handle; EFI_STATUS Status; =20 - // Pick RTC device and initialize its data - RtcDeviceTable =3D (UINT8 *) PcdGetPtr (PcdRtcEnabled); - if (RtcDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "RTC: Missing PcdRtcEnabled\n")); - return EFI_INVALID_PARAMETER; - } - - // Initialize only first of enabled controllers - for (Index =3D 0; Index < PcdGetSize (PcdRtcEnabled); Index++) { - if (MVHW_DEV_ENABLED (Rtc, Index)) { - DEBUG ((DEBUG_ERROR, "RTC: Initialize controller %d\n", Index)); - mArmadaRtcBase =3D Desc->RtcBaseAddresses[Index]; - break; - } - } + // Obtain RTC device base address + mArmadaRtcBase =3D PcdGet64 (PcdRtcBaseAddress); =20 - // Check if any of the controllers can be initialized + // Check if the controller can be initialized if (mArmadaRtcBase =3D=3D 0) { DEBUG ((DEBUG_ERROR, "RTC: None of controllers enabled\n")); return EFI_INVALID_PARAMETER; @@ -247,7 +230,7 @@ LibRtcInitialize ( Status =3D gDS->AddMemorySpace ( EfiGcdMemoryTypeMemoryMappedIo, mArmadaRtcBase, - Desc->RtcMemSize[Index], + SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ); if (EFI_ERROR (Status)) { @@ -257,7 +240,7 @@ LibRtcInitialize ( =20 Status =3D gDS->SetMemorySpaceAttributes ( mArmadaRtcBase, - Desc->RtcMemSize[Index], + SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ); if (EFI_ERROR (Status)) { @@ -304,7 +287,7 @@ LibRtcInitialize ( ErrEvent: gBS->UninstallProtocolInterface (Handle, &gEfiRealTimeClockArchProtocolG= uid, NULL); ErrSetMem: - gDS->RemoveMemorySpace (mArmadaRtcBase, Desc->RtcMemSize[Index]); + gDS->RemoveMemorySpace (mArmadaRtcBase, SIZE_4KB); =20 return Status; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:35 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22f; helo=mail-lf0-x22f.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Mjgzmn58C7WmtjaKUN1XZQ/XRzuZd9iVtQDnq5YaQ/g=; b=01jkW+dE1J/JgqsD3DtEER9qGkfCUdARwrGIaBHn2A+IitJBekCQILWgd2ckD2pxJX oMoiFEUiCEKT142CITvL4su69jpzCSY37llX5bBrFZehSSgZehNY/iN5kEYdRogru5gZ zHcD41c7ndSFwinhwnqMOdMlOtG6StrYFB1llUTx9S57nQcKua+aDV/oMMvxHVZG6Cb5 rAb92/l/ZhMrdClCl9oHRLVR15NbeQnUsTDh/641u80Go+7htwMn9MLCs6u/Ng0vFIEL cTzsooBJ1Tci1Ffswlst0zOoU00dd1m+l3+mNEK/QOOtjUY7z5VU9Zsp8tVtMn5dLM4B nWVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Mjgzmn58C7WmtjaKUN1XZQ/XRzuZd9iVtQDnq5YaQ/g=; b=cxXa7N1hk1dEBqRH85ZcmuUq6ijpJv88y1g+qt+GdUQXX/v+yDfitEEokkWAei8Wk1 AR4ehKupu0+VcN+zZSVIkajI+5he0TAJq8m6zyTpSg1nQmgyXNSUjexxt9w/1CQ4btcI A1KrEmJc2AbDHjxQvJHIsvLcQQaMnR3EAx0DSQr6kgkUmBN7ju28PYl05IFas7trOr4B 1j0KX29VUJAsCNJf+eJw5KC+9flcSvxSaFZNkHWPGmCxdDCh/q61CSBodTAj0lfeywrW 5BzFBJSKBQl69eFkI8LXDjrgWpBgXjDka4enEcaC0N2s1YE2qtLFqXYbpWqgU4AsQZwD mv/Q== X-Gm-Message-State: APt69E3RijNoRDN/F8CES/gklzFOX7ADpicD7bJzvfKMkjziP+C11OtX w5UHtm+upzc+S19s8q0PWWSSR63tYYI= X-Google-Smtp-Source: ADUXVKKVHfxtcIvhs2akOKGnXDwVzYl6I73RVFhGZhqz0yxK4aTZrRMu65Ikw1P940zi2XaUVZpZXA== X-Received: by 2002:a19:13da:: with SMTP id 87-v6mr3782538lft.135.1529266356318; Sun, 17 Jun 2018 13:12:36 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:48 +0200 Message-Id: <1529266325-18371-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 08/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with PP2 information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescPp2Get ()), which dynamically allocates and fills MV_SOC_PP2_DESC structure with the SoC description of PP2 NICs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 6 ++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 15 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 29 ++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index c5711b0..d63c3b5 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -24,6 +24,12 @@ #define MV_SOC_CP_BASE(Cp) (0xF2000000 + ((Cp) * 0x2000000)) =20 // +// Platform description of PP2 NIC +// +#define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE ((Cp)) +#define MV_SOC_PP2_CLK_FREQ 333333333 + +// // Platform description of UTMI PHY's // #define MV_SOC_UTMI_PER_CP_COUNT 2 diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 0d45684..cafcc0f 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -15,6 +15,21 @@ #define __ARMADA_SOC_DESC_LIB_H__ =20 // +// PP2 NIC devices SoC description +// +typedef struct { + UINTN Pp2BaseAddress; + UINTN Pp2ClockFrequency; +} MV_SOC_PP2_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescPp2Get ( + IN OUT MV_SOC_PP2_DESC **Pp2Desc, + IN OUT UINTN *DescCount + ); + +// // UTMI PHY devices SoC description // typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 63fb224..61b4e30 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -30,6 +30,35 @@ =20 EFI_STATUS EFIAPI +ArmadaSoCDescPp2Get ( + IN OUT MV_SOC_PP2_DESC **Pp2Desc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_PP2_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_PP2_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].Pp2BaseAddress =3D MV_SOC_PP2_BASE (CpIndex); + Desc[CpIndex].Pp2ClockFrequency =3D MV_SOC_PP2_CLK_FREQ; + } + + *Pp2Desc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescUtmiGet ( IN OUT MV_SOC_UTMI_DESC **UtmiDesc, IN OUT UINTN *DescCount --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266384015726.7278568251337; Sun, 17 Jun 2018 13:13:04 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A2FEF20972134; Sun, 17 Jun 2018 13:12:40 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 88D1F20972132 for ; Sun, 17 Jun 2018 13:12:39 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id o9-v6so21581604lfk.1 for ; Sun, 17 Jun 2018 13:12:39 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:36 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ponM3jgvNe9csdxeVQcUf2w8WTGRPULIyNFLQk5E76k=; b=RPgBK0BJ0OiSZO2wrdOrZ/A61DbUfJ2rDv3FT7fxmA4zpJvSr5cZ0M1byiOvVqXz8f /qw4UwmMZ23IQNJOVOKfjjQl80S6CT5KmtbBvPInibJR019LBQ74SfnLLMqlwLOkWjbX XE3owlL4ngrzP5LuzhwZGg5VsU/91gm85YMPdNRZuBpsWJbctMUlvN+EkN8ZkRr6atBs ltkkuUJYPzgF4T/B490LHIZLKVCRpRHku4GrT/g5y1sfO0SNIvaBUzqHFmpUdAzCokxD IqXePL57eYrofngJ2Uo2/zHofTV9OdTsFdAQ21Eit2LHSG3iTJFtRN5gtoroqFX5xKUK /GVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ponM3jgvNe9csdxeVQcUf2w8WTGRPULIyNFLQk5E76k=; b=l512mkbZousWuvPRqnI9k1sHAVz/ZKsRl3yBPLPD+ZCpusI5SOaPlyihLTTCPW3NlR qxyv3CrmDo+VzCzFNu5tta9JieUlNPnGKbFoBylkV8coGAiOw7FWmx0Vk0QnO4eV28B0 nJOz5ttD8UfoOYKdoaKGqRcgarG4IUl5Tg6qz0pH9H+ZmDVTCBlQmpnQRv45TUV++Wj/ veRESjqRhJ8W1iunzyCGsCN+lLkHpESF7RmLrvUP95G+blV8jH05AnneF3wurNaIOkRZ PFQzZduJblZhgW0vOD28x0UFTDbAAZ5h2i+t/eijMfupMFNrNSstZX61iCVL2LViGcT7 M/TA== X-Gm-Message-State: APt69E2pEEJo6troZYYB6L08WjAOJIH5l7nAPT3LHxi+WHYtDROXpO2o jGYiQa70uckcxuJV+xrAyrMTfwM5ohc= X-Google-Smtp-Source: ADUXVKLexjwdlS8NDifKIBi/apPzbnvf/aDYqfEc/qDbcO9h46K3lyAb0+4EeVRzqTwsj5XOeWge3A== X-Received: by 2002:a19:9601:: with SMTP id y1-v6mr5584637lfd.130.1529266357554; Sun, 17 Jun 2018 13:12:37 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:49 +0200 Message-Id: <1529266325-18371-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 09/25] Marvell/Drivers: MvBoardDesc: Extend protocol with PP2 support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about PP2 NICs to the Pp2Dxe driver. Extend ArmadaBoardDescLib with new structure MV_BOARD_PP2_DESC, for holding board specific data. In further steps it should be extended and replace PCD port's representation with the appropriate structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 8 +++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 63 ++++++++++++++++= ++++ 4 files changed, 80 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index 5da5f21..6f57f06 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -58,6 +58,7 @@ =20 [Pcd] gMarvellTokenSpaceGuid.PcdPciEXhci + gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled gMarvellTokenSpaceGuid.PcdUtmiPortType =20 diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 068535a..ab94877 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,14 @@ #include =20 // +// PP2 NIC devices per-board description +// +typedef struct { + MV_SOC_PP2_DESC *SoC; + UINT8 Pp2DevCount; +} MV_BOARD_PP2_DESC; + +// // UTMI PHY devices per-board description // typedef struct { diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index f8a2902..114a0ec 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,13 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_PP2_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PP2_DESC **Pp2Desc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_UTMI_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_UTMI_DESC **UtmiDesc @@ -55,6 +62,7 @@ VOID ); =20 struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; MV_BOARD_DESC_FREE BoardDescFree; }; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 0232a21..7c0bc39 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,68 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescPp2Get ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PP2_DESC **Pp2Desc + ) +{ + UINT8 *Pp2DeviceEnabled; + UINTN Pp2Count, Pp2DeviceTableSize, Pp2Index, Index; + MV_BOARD_PP2_DESC *BoardDesc; + MV_SOC_PP2_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available PP2 controllers */ + Status =3D ArmadaSoCDescPp2Get (&SoCDesc, &Pp2Count); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled Pp2 controllers, + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + Pp2DeviceEnabled =3D PcdGetPtr (PcdPp2Controllers); + if (Pp2DeviceEnabled =3D=3D NULL) { + /* No PP2 NIC on platform */ + return EFI_SUCCESS; + } + + Pp2DeviceTableSize =3D PcdGetSize (PcdPp2Controllers); + + /* Check if PCD with PP2 NICs is correctly defined */ + if (Pp2DeviceTableSize > Pp2Count) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPp2Controllers format\n", __FUNCTIO= N__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (Pp2DeviceTableSize * sizeof (MV_BOARD_PP= 2_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + Pp2Index =3D 0; + for (Index =3D 0; Index < Pp2DeviceTableSize; Index++) { + if (!Pp2DeviceEnabled[Index]) { + continue; + } + + BoardDesc[Pp2Index].SoC =3D &SoCDesc[Index]; + Pp2Index++; + } + + BoardDesc->Pp2DevCount =3D Pp2Index; + + *Pp2Desc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescUtmiGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_UTMI_DESC **UtmiDesc @@ -140,6 +202,7 @@ MvBoardDescInitProtocol ( IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol ) { + BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:38 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mTGLnXpyErt35R2Uws/yu/dRtBA1QNCvH2TeebRNxh8=; b=I2WA+l10nnHIq+Sv0AtkQ9/vOJ1bqV+A8dhX/m4XU3JANLkOyGOo/HucCZsdMXXHUs WSTcqE+Q1ZKLmUgIXFDUai2g8+fbjaBw4hnyPK4ffqxylM7etTC4W0tzqXHmKjlUIXtY dgcGQGO0pfffbKzI8nRB2HNSa8WO/ikTcIjNFigcLdKrI9xpVjOQ40tr/1dWZSSD2cQY 0aShallYbAbKf8X5xxHNoeh2XhAmT7I36yYZF6nwZtHeKDeN8JOMlpol4GgRYBeyhY09 CluQbWC74XQFe/Nxu8mk24rLJu/jpsbzR7j9AvK/t1avCJ55TAqfpOohhp1bekKDD6TN lS4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mTGLnXpyErt35R2Uws/yu/dRtBA1QNCvH2TeebRNxh8=; b=SU0Ld1sI1U3E1iGU3wmcgxk9H9JYZF8SLl++1i00HXrtwOv40yP1+pzeumtAo8ew+i TOHLTIpyoJEjsv7d0/F/UeS+nv+k/9wmRzBz2yeDBbJJwibmu8JoX4IENw5h856Lqr2S GjwQ2UgnO7CowAwGnNXBtjys5lx6iWcG7oboKo3PJAJrhc1PDpsX+b6a5TAlHgBMQcXx HayEC8PkABbq7DFfiXP9znEiRtmhH8CEI5SjAhgtk1jMtRWj9zxG/IWE6n74UdHO4x0c m2IAXsXLuPrvae0mU667koFxRqJTZcPUzIneFgrvIleo0G9B1+UixjQR3lxW6Jn1zXAu O5QA== X-Gm-Message-State: APt69E1K67Bp7DZrCYQT2P14VlvNByiCv/O8GgH+jqsdkLlgpn41Qage pFU4w5IIzT0koY51O38Et9BR64mx+eI= X-Google-Smtp-Source: ADUXVKKjAuOJ7uHS8bydK6Mf08GGHUVQAwL68dbIQSMi1/uNAk713srx7fJXmVxU2pXRKfAXwjNHaQ== X-Received: by 2002:a19:c30b:: with SMTP id t11-v6mr3572435lff.127.1529266358728; Sun, 17 Jun 2018 13:12:38 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:50 +0200 Message-Id: <1529266325-18371-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 10/25] Marvell/Drivers: Pp2Dxe: Switch to use MARVELL_BOARD_DESC protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Pp2Dxe driver used to get Armada7k8k PP2 controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get PP2 controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 2 +- Silicon/Marvell/Include/Library/MvHwDescLib.h | 26 ------------ Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 43 ++++++++------------ 3 files changed, 19 insertions(+), 52 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Silicon/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index fcd0611..be536ab 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -67,11 +67,11 @@ gEfiSimpleNetworkProtocolGuid gEfiDevicePathProtocolGuid gEfiCpuArchProtocolGuid + gMarvellBoardDescProtocolGuid gMarvellMdioProtocolGuid gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 34d03d4..5fd514c 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -105,17 +105,6 @@ typedef struct { } MVHW_NONDISCOVERABLE_DESC; =20 // -// PP2 NIC devices description template definition -// -#define MVHW_MAX_PP2_DEVS 4 - -typedef struct { - UINT8 Pp2DevCount; - UINTN Pp2BaseAddresses[MVHW_MAX_PP2_DEVS]; - UINTN Pp2ClockFrequency[MVHW_MAX_PP2_DEVS]; -} MVHW_PP2_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -200,19 +189,4 @@ MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTem= plate =3D {\ { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent }\ } =20 -// -// Platform description of Pp2 NIC devices -// -#define MVHW_CP0_PP2_BASE 0xF2000000 -#define MVHW_CP1_PP2_BASE 0xF4000000 -#define MVHW_PP2_CLK_FREQ 333333333 - -#define DECLARE_A7K8K_PP2_TEMPLATE \ -STATIC \ -MVHW_PP2_DESC mA7k8kPp2DescTemplate =3D {\ - 2,\ - { MVHW_CP0_PP2_BASE, MVHW_CP1_PP2_BASE },\ - { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Silicon/Marvell/= Drivers/Net/Pp2Dxe/Pp2Dxe.c index 3ed10f6..02b2798 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 **************************************************************************= *****/ =20 +#include #include #include #include @@ -42,7 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include #include #include #include @@ -54,8 +54,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #define ReturnUnlock(tpl, status) do { gBS->RestoreTPL (tpl); return (stat= us); } while(0) =20 -DECLARE_A7K8K_PP2_TEMPLATE; - STATIC PP2_DEVICE_PATH Pp2DevicePathTemplate =3D { { { @@ -1343,35 +1341,28 @@ Pp2DxeInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_PP2_DESC *Desc =3D &mA7k8kPp2DescTemplate; - UINT8 *Pp2DeviceTable, Index; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_PP2_DESC *Pp2BoardDesc; MVPP2_SHARED *Mvpp2Shared; EFI_STATUS Status; + UINTN Index; =20 /* Obtain table with enabled Pp2 devices */ - Pp2DeviceTable =3D (UINT8 *)PcdGetPtr (PcdPp2Controllers); - if (Pp2DeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdPp2Controllers\n")); - return EFI_INVALID_PARAMETER; - } - - if (PcdGetSize (PcdPp2Controllers) > MVHW_MAX_PP2_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdPp2Controllers format\n")); - return EFI_INVALID_PARAMETER; + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } =20 - /* Check amount of declared ports */ - if (PcdGetSize (PcdPp2Port2Controller) > Desc->Pp2DevCount * MVPP2_MAX_P= ORT) { - DEBUG ((DEBUG_ERROR, "Pp2Dxe: Wrong too many ports declared\n")); - return EFI_INVALID_PARAMETER; + Status =3D BoardDescProtocol->BoardDescPp2Get (BoardDescProtocol, + &Pp2BoardDesc); + if (EFI_ERROR (Status)) { + return Status; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdPp2Controllers); Index++) { - if (!MVHW_DEV_ENABLED (Pp2, Index)) { - DEBUG ((DEBUG_ERROR, "Skip Pp2 controller %d\n", Index)); - continue; - } + for (Index =3D 0; Index < Pp2BoardDesc->Pp2DevCount; Index++) { =20 /* Initialize private data */ Mvpp2Shared =3D AllocateZeroPool (sizeof (MVPP2_SHARED)); @@ -1383,8 +1374,8 @@ Pp2DxeInitialise ( Status =3D Pp2DxeInitialiseController ( Index, Mvpp2Shared, - Desc->Pp2BaseAddresses[Index], - Desc->Pp2ClockFrequency[Index] + Pp2BoardDesc[Index].SoC->Pp2BaseAddress, + Pp2BoardDesc[Index].SoC->Pp2ClockFrequency ); if (EFI_ERROR(Status)) { FreePool (Mvpp2Shared); @@ -1393,5 +1384,7 @@ Pp2DxeInitialise ( } } =20 + BoardDescProtocol->BoardDescFree (Pp2BoardDesc); + return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:39 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nF+kpVvFgyjSctsFDLeETWjRrb+yd7hyV0x/Jpc6Rm8=; b=VlkeM2GJaBcNRD3Df6KdHbDfDEJe9TxgwjDR5I0ASOMfNGaKN6gV10csvq2oLPutpo uyg7PUQT2WK2qMFn3Okawd1hOuE1GnVocBaFqzTSm3x4PCWbUIuhFO1yptRvDVeMyc/M 5FGFqBKGJY9g80D56MmSjWesp6dLEKSXa98P+hP/+hCB50HSwdUbW3eaPSsz+GVkNVCu LGc5Q2lmH3WhC3Ebvm5d+RguD6jOWDWiqo4bBf0PpWF1CThKQYsaUO4dDWJ83oS0PhQP B5HxEenwYaK9GAGyq19YyZ98OrUUfQF09cLMth4rS0m4yBFyU34Mcll+FPPEa6X/Z0W0 /scw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nF+kpVvFgyjSctsFDLeETWjRrb+yd7hyV0x/Jpc6Rm8=; b=AWF4NAU/1le1fqE3QmIs4pbbw/S9x0cYEv0Mtndi6cxkIPJNe45scOnfLL8F5TJBXy 9jqZYg3KvgzbDRQdLwbzVnriNEJfHUEPmiwvqoyDsuyYCEfoAGsxR0n7dOIiCLZhQkc8 9PdzZJ0zg29y6Orez3zZT7VI3fc/0ou0JZ+lX+h7sjqWUwXwEuJCLV09CiiTyUXgmsJq F1fwafOKgJVydQZf39XNlnGi0Xok4ygj6aUg/ra5JBOC9vdsCpse4U/sok8H2b2zUTQO RORWGYksFjiALFSuVihdB7EgTXPubHyfMNGd0gCfBKIevmth8vrISwdrxxqUHKBfdXCI v7tw== X-Gm-Message-State: APt69E2zHijsw7oVEuwedAXbmOKhxuZo1knNQZg5SqYODiCrrXp6Ehaq N7L0YZil9GmCD5VKMHkLdEPjOItFoPA= X-Google-Smtp-Source: ADUXVKLUw4Z5FlGY/rz/cmfGmbLSTzr4djD9JZ4/bV8i9ON6dvBM8RpbSQzbD0SKZlts7PvQl0G4Mw== X-Received: by 2002:a19:141f:: with SMTP id k31-v6mr1011903lfi.23.1529266359989; Sun, 17 Jun 2018 13:12:39 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:51 +0200 Message-Id: <1529266325-18371-12-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 11/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callbacks for NonDiscoverable devices i.e. AHCI/XHCI/SDMMC. They dynamically allocate and fill according structures with the SoC description of the devices. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 18 ++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 48 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 92 ++++++++++++++++++++ 3 files changed, 158 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index d63c3b5..94fd6fa 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -24,12 +24,24 @@ #define MV_SOC_CP_BASE(Cp) (0xF2000000 + ((Cp) * 0x2000000)) =20 // +// Platform description of AHCI controllers +// +#define MV_SOC_AHCI_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x540000) +#define MV_SOC_AHCI_ID(Cp) ((Cp) % 2) + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE ((Cp)) #define MV_SOC_PP2_CLK_FREQ 333333333 =20 // +// Platform description of SDMMC controllers +// +#define MV_SOC_MAX_SDMMC_COUNT 2 +#define MV_SOC_SDMMC_BASE(Index) ((Index) =3D=3D 0 ? 0xF06E0000 : = 0xF2780000) + +// // Platform description of UTMI PHY's // #define MV_SOC_UTMI_PER_CP_COUNT 2 @@ -38,4 +50,10 @@ #define MV_SOC_UTMI_CFG_BASE 0x440440 #define MV_SOC_UTMI_USB_CFG_BASE 0x440420 =20 +// +// Platform description of XHCI controllers +// +#define MV_SOC_XHCI_PER_CP_COUNT 2 +#define MV_SOC_XHCI_BASE(Xhci) (0x500000 + ((Xhci) * 0x10000)) + #endif diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index cafcc0f..3b29d78 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -14,6 +14,54 @@ #ifndef __ARMADA_SOC_DESC_LIB_H__ #define __ARMADA_SOC_DESC_LIB_H__ =20 +#include + +// +// NonDiscoverable devices SoC description +// +// AHCI +typedef struct { + UINTN AhciId; + UINTN AhciBaseAddress; + UINTN AhciMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType; +} MV_SOC_AHCI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescAhciGet ( + IN OUT MV_SOC_AHCI_DESC **AhciDesc, + IN OUT UINTN *DescCount + ); + +// SDMMC +typedef struct { + UINTN SdMmcBaseAddress; + UINTN SdMmcMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE SdMmcDmaType; +} MV_SOC_SDMMC_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescSdMmcGet ( + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, + IN OUT UINTN *DescCount + ); + +// XHCI +typedef struct { + UINTN XhciBaseAddress; + UINTN XhciMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType; +} MV_SOC_XHCI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescXhciGet ( + IN OUT MV_SOC_XHCI_DESC **XhciDesc, + IN OUT UINTN *DescCount + ); + // // PP2 NIC devices SoC description // diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 61b4e30..97fe3f8 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -30,6 +30,37 @@ =20 EFI_STATUS EFIAPI +ArmadaSoCDescAhciGet ( + IN OUT MV_SOC_AHCI_DESC **AhciDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_AHCI_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_AHCI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].AhciId =3D MV_SOC_AHCI_ID (CpIndex); + Desc[CpIndex].AhciBaseAddress =3D MV_SOC_AHCI_BASE (CpIndex); + Desc[CpIndex].AhciMemSize =3D SIZE_8KB; + Desc[CpIndex].AhciDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + } + + *AhciDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescPp2Get ( IN OUT MV_SOC_PP2_DESC **Pp2Desc, IN OUT UINTN *DescCount @@ -59,6 +90,34 @@ ArmadaSoCDescPp2Get ( =20 EFI_STATUS EFIAPI +ArmadaSoCDescSdMmcGet ( + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_SDMMC_DESC *Desc; + UINTN Index; + + Desc =3D AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC= _DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) { + Desc[Index].SdMmcBaseAddress =3D MV_SOC_SDMMC_BASE (Index); + Desc[Index].SdMmcMemSize =3D SIZE_1KB; + Desc[Index].SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + } + + *SdMmcDesc =3D Desc; + *DescCount =3D MV_SOC_MAX_SDMMC_COUNT; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescUtmiGet ( IN OUT MV_SOC_UTMI_DESC **UtmiDesc, IN OUT UINTN *DescCount @@ -92,3 +151,36 @@ ArmadaSoCDescUtmiGet ( =20 return EFI_SUCCESS; } + +EFI_STATUS +EFIAPI +ArmadaSoCDescXhciGet ( + IN OUT MV_SOC_XHCI_DESC **XhciDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_XHCI_DESC *Desc; + UINTN CpCount, CpIndex, Index; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *DescCount =3D CpCount * MV_SOC_XHCI_PER_CP_COUNT; + Desc =3D AllocateZeroPool (*DescCount * sizeof (MV_SOC_XHCI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + *XhciDesc =3D Desc; + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_XHCI_PER_CP_COUNT; Index++) { + Desc->XhciBaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_XHCI_BAS= E (Index); + Desc->XhciMemSize =3D SIZE_16KB; + Desc->XhciDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + Desc++; + } + } + + return EFI_SUCCESS; +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266399512577.7825250465202; Sun, 17 Jun 2018 13:13:19 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 452AE20972149; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:40 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1RmWF7/phuJ/549gJcMb/AjgHn++E3LieCpdykCfodU=; b=MXU0U7D/ZKblD4WDFNiyZ9X5SZmx4635U4Z5YspL55j6s0xJUqfCs5FnjacOTngSZ+ NORaQ2WPSHAmMwa2GVSdf20DZgtqaw1SGRVodEP36X4SGU6vqBEI0tWuxj6ZdJVNImNE Vqx6x7ATzYzMhB1om/KVngijUt3Yv56mbjv6TlqcFWNZkVTARxZfww462I/q33T7hpMZ 8YMFbtuPsE0wBfQUd4NRFSWFJ4pI0YW0I3tlxf+Bb8OnikUYPTqxf46ki98C/oWBKIBM Qi03F3dPb7QhQun6egOcS5+sIwxuhbSRwwhKAnqGAuUR6nq9H9t2Xq7bzNlgSm856bZ/ KiDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1RmWF7/phuJ/549gJcMb/AjgHn++E3LieCpdykCfodU=; b=Ijms3Yr8sKvxVX5PNXoR+iqLvD7Q/TQMsctfZ1fH0J4gpp8A8eTdI6uKv+4Fi44hal HVrhw7DLqjc16m3t9d7mRs4mCkgOjTy4C+kFX3vi3oaWBsb5iqBmXeal9+0/HDJR+nJf WjSxrr//4YGx4gxYqe/BGHnhxazaXUM0Hed74LARpemBWFRyhbaxPrLikW+2GqF4mqk5 XuJLIRMInGvSww+FVMkUQQk9odL1LCvR2lmM7tqlvs4rOcRpNevo0CPK3faE1elF8xqC qhFjHViRW6wj/TziF+VkNKPmQCO5N39snPrjJwKO1iCqGxwT2meuhJwkUkGoQZlPyeGI bicA== X-Gm-Message-State: APt69E3u8XfVafsaTiqqkcwNZCuSaz3MOuKvzsPVaR+nt01jyJ/SdReM cxiEW03Pmd0IJJZ3CzKZu5uoAQOnzYw= X-Google-Smtp-Source: ADUXVKJ/WFc5z59Rx4Wue55Zo+AwqQkrmenO1X+PPGtu8VE/R+hY24vxiXgG23eoRBfCyB3fVdZFug== X-Received: by 2002:a2e:1092:: with SMTP id 18-v6mr6713153ljq.115.1529266361296; Sun, 17 Jun 2018 13:12:41 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:52 +0200 Message-Id: <1529266325-18371-13-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 12/25] Marvell/Drivers: MvBoardDesc: Extend protocol with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about NonDiscoverableDevices to the relevant drivers and libraries. Extend ArmadaBoardDescLib with new structures (MV_BOARD_AHCI_DESC/ MV_BOARD_SDMMC_DESC/MV_BOARD_XHCI_DESC) for holding board specific data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 2 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 28 +++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 24 +++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 192 +++++++++++++++= +++++ 4 files changed, 246 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index 6f57f06..cc0d9d4 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -57,6 +57,8 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] + gMarvellTokenSpaceGuid.PcdPciEAhci + gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdPciEXhci gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index ab94877..7e4fa4d 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,34 @@ #include =20 // +// NonDiscoverableDevices per-board description +// + +// +// AHCI devices per-board description +// +typedef struct { + MV_SOC_AHCI_DESC *SoC; + UINTN AhciDevCount; +} MV_BOARD_AHCI_DESC; + +// +// SDMMC devices per-board description +// +typedef struct { + MV_SOC_SDMMC_DESC *SoC; + UINTN SdMmcDevCount; +} MV_BOARD_SDMMC_DESC; + +// +// XHCI devices per-board description +// +typedef struct { + MV_SOC_XHCI_DESC *SoC; + UINTN XhciDevCount; +} MV_BOARD_XHCI_DESC; + +// // PP2 NIC devices per-board description // typedef struct { diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index 114a0ec..edf9491 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,27 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_AHCI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_AHCI_DESC **AhciDesc + ); + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_SDMMC_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ); + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_XHCI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_XHCI_DESC **XhciDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_PP2_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_PP2_DESC **Pp2Desc @@ -62,8 +83,11 @@ VOID ); =20 struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; + MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; + MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; MV_BOARD_DESC_FREE BoardDescFree; }; =20 diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 7c0bc39..3439017 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,195 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescAhciGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_AHCI_DESC **AhciDesc + ) +{ + UINT8 *AhciDeviceEnabled; + UINTN AhciCount, AhciDeviceTableSize, AhciIndex, Index; + MV_BOARD_AHCI_DESC *BoardDesc; + MV_SOC_AHCI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available AHCI controllers */ + Status =3D ArmadaSoCDescAhciGet (&SoCDesc, &AhciCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled AHCI controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + AhciDeviceEnabled =3D PcdGetPtr (PcdPciEAhci); + if (AhciDeviceEnabled =3D=3D NULL) { + /* No AHCI on the platform */ + return EFI_SUCCESS; + } + + AhciDeviceTableSize =3D PcdGetSize (PcdPciEAhci); + + /* Check if PCD with AHCI controllers is correctly defined */ + if (AhciDeviceTableSize > AhciCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEAhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (AhciDeviceTableSize * sizeof (MV_BOARD_A= HCI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + AhciIndex =3D 0; + for (Index =3D 0; Index < AhciDeviceTableSize; Index++) { + if (!AhciDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip Ahci controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[AhciIndex].SoC =3D &SoCDesc[Index]; + AhciIndex++; + } + + BoardDesc->AhciDevCount =3D AhciIndex; + + *AhciDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvBoardDescSdMmcGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + UINT8 *SdMmcDeviceEnabled; + UINTN SdMmcCount, SdMmcDeviceTableSize, SdMmcIndex, Index; + MV_BOARD_SDMMC_DESC *BoardDesc; + MV_SOC_SDMMC_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available SDMMC controllers */ + Status =3D ArmadaSoCDescSdMmcGet (&SoCDesc, &SdMmcCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled SDMMC controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + SdMmcDeviceEnabled =3D PcdGetPtr (PcdPciESdhci); + if (SdMmcDeviceEnabled =3D=3D NULL) { + /* No SDMMC on platform */ + return EFI_SUCCESS; + } + + SdMmcDeviceTableSize =3D PcdGetSize (PcdPciESdhci); + + /* Check if PCD with SDMMC controllers is correctly defined */ + if (SdMmcDeviceTableSize > SdMmcCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciESdhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (SdMmcDeviceTableSize * sizeof (MV_BOARD_= SDMMC_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + SdMmcIndex =3D 0; + for (Index =3D 0; Index < SdMmcDeviceTableSize; Index++) { + if (!SdMmcDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip SdMmc controller %d\n", __FUNCTION__, = Index)); + continue; + } + + BoardDesc[SdMmcIndex].SoC =3D &SoCDesc[Index]; + SdMmcIndex++; + } + + BoardDesc->SdMmcDevCount =3D SdMmcIndex; + + *SdMmcDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvBoardDescXhciGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_XHCI_DESC **XhciDesc + ) +{ + UINT8 *XhciDeviceEnabled; + UINTN XhciCount, XhciDeviceTableSize, XhciIndex, Index; + MV_BOARD_XHCI_DESC *BoardDesc; + MV_SOC_XHCI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available XHCI controllers */ + Status =3D ArmadaSoCDescXhciGet (&SoCDesc, &XhciCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled XHCI controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + XhciDeviceEnabled =3D PcdGetPtr (PcdPciEXhci); + if (XhciDeviceEnabled =3D=3D NULL) { + /* No XHCI on platform */ + return EFI_SUCCESS; + } + + XhciDeviceTableSize =3D PcdGetSize (PcdPciEXhci); + + /* Check if PCD with XHCI controllers is correctly defined */ + if (XhciDeviceTableSize > XhciCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEXhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (XhciDeviceTableSize * sizeof (MV_BOARD_X= HCI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + XhciIndex =3D 0; + for (Index =3D 0; Index < XhciDeviceTableSize; Index++) { + if (!XhciDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip Xhci controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[XhciIndex].SoC =3D &SoCDesc[Index]; + XhciIndex++; + } + + BoardDesc->XhciDevCount =3D XhciIndex; + + *XhciDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescPp2Get ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_PP2_DESC **Pp2Desc @@ -202,8 +391,11 @@ MvBoardDescInitProtocol ( IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol ) { + BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; + BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; + BoardDescProtocol->BoardDescXhciGet =3D MvBoardDescXhciGet; BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; =20 return EFI_SUCCESS; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266405234658.7562097772136; Sun, 17 Jun 2018 13:13:25 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6D10E2097214F; Sun, 17 Jun 2018 13:12:47 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8B15A2097213C for ; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:41 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mAFIKR77tuImppjWlErMCGbVG50og6G9coRlg4ZJyWw=; b=eCJATCbFYyr1hu0dpW6yF2JaryZQm2dgc64cXfmGKzDfSgzgdc+O1obhdSGwHoFunt C5OPtyAg+cITUzdjNNyiEnQtv43ElfvFib+/MSqdrMjCcbQxIZU7N2tuWYoZB0rgQFbY P5ZyXWEFk9W1YHC4OT0Nk1fTu+Jivfh4nvCkRV0zeYG/VYz3xXNsfdvcQa+/iuHOUnt2 uBEsy7ucQRsl47OTDyuEYAgWS/NfC1Ei1MkwXfqJX2gQ9sS7ohP294LhjnHc+ME3R5vc 3wGnd++GDozWKJzAG+mgOrGfFxfd6lp97YJmQ0oZB4TBqTQ/ka5pcz7El1Y0p7oPWV7Y TaXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mAFIKR77tuImppjWlErMCGbVG50og6G9coRlg4ZJyWw=; b=gsvbqYtW1tMNv4wDDl9D58SVlJUBwuRd2jqMg95ja8/8w8i2juKExWMjD5mE9wNYTw UI2hvSKmI/iQdKrU/8PJR30aMkTSh436GBWZ9KPqW6pyaDiR33YlED962T/NJSWAJ34k nFlfbFkBzmBhKKIgq88LAnITwrg1m6nJNdhgGvhedyuZsEy+sG9qYh2EFMEQw3tsfbZc MXDB97/tYUs6WZIcSCsRB7PWVFIaT4Gmha+jqSMKpvay33TfI4YlLHc2jkCOlmqW/ICJ TS+FezchtXGgQEw0j0rr41vt47ITRtnEGWl2NO5V54j9MzunOcERTgR5QNduZ6+fo3NS WiWg== X-Gm-Message-State: APt69E3hgRVVBP5RyjZw8KbcjO0naJFNJb+JFPOStFH5kbfwe/ll+kUZ z+fe/o5SM8Uam+LiTRt9xv/Vl/EWHVA= X-Google-Smtp-Source: ADUXVKJbqhlvT88l0oUe6Q3eHXKcIXLh5B2V3yoJZRLgVN79qhg/qH2ni7n99LR0fC/cZ2yh4pnCWQ== X-Received: by 2002:a2e:4811:: with SMTP id v17-v6mr6065297lja.39.1529266362658; Sun, 17 Jun 2018 13:12:42 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:53 +0200 Message-Id: <1529266325-18371-14-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 13/25] Marvell/Drivers: NonDiscoverable: Switch to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" NonDiscoverableDevices driver used to get Armada7k8k AHCI/SDMMC/XHCI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get AHCI/SDMMC/XHCI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf | 6 +- Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c | 100 ++= ++++++++---------- 2 files changed, 52 insertions(+), 54 deletions(-) diff --git a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.= inf b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf index b62b3fb..98e5b0c 100644 --- a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf +++ b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf @@ -52,10 +52,8 @@ NonDiscoverableDeviceRegistrationLib UefiDriverEntryPoint =20 -[Pcd] - gMarvellTokenSpaceGuid.PcdPciEAhci - gMarvellTokenSpaceGuid.PcdPciESdhci - gMarvellTokenSpaceGuid.PcdPciEXhci +[Protocols] + gMarvellBoardDescProtocolGuid =20 [Depex] TRUE diff --git a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.= c b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c index 6ff90a5..c5cf904 100644 --- a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c +++ b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c @@ -35,50 +35,33 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include =20 #include -#include #include #include =20 +#include #include =20 -DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; - -// -// Tables with used devices -// -STATIC UINT8 * CONST XhciDeviceTable =3D FixedPcdGetPtr (PcdPciEXhci); -STATIC UINT8 * CONST AhciDeviceTable =3D FixedPcdGetPtr (PcdPciEAhci); -STATIC UINT8 * CONST SdhciDeviceTable =3D FixedPcdGetPtr (PcdPciESdhci); - // // NonDiscoverable devices registration // STATIC EFI_STATUS NonDiscoverableInitXhci ( + IN MV_BOARD_XHCI_DESC *Desc ) { - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_STATUS Status; UINT8 i; =20 - if (PcdGetSize (PcdPciEXhci) < Desc->XhciDevCount) { - DEBUG((DEBUG_ERROR, "NonDiscoverable: Wrong PcdPciEXhci format\n")); - return EFI_INVALID_PARAMETER; - } - for (i =3D 0; i < Desc->XhciDevCount; i++) { - if (!MVHW_DEV_ENABLED (Xhci, i)) { - continue; - } - Status =3D RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeXhci, - Desc->XhciDmaType[i], + Desc[i].SoC->XhciDmaType, NULL, NULL, 1, - Desc->XhciBaseAddresses[i], Desc->XhciMemSize[i] + Desc[i].SoC->XhciBaseAddress, + Desc[i].SoC->XhciMemSize ); =20 if (EFI_ERROR(Status)) { @@ -93,29 +76,21 @@ NonDiscoverableInitXhci ( STATIC EFI_STATUS NonDiscoverableInitAhci ( + IN MV_BOARD_AHCI_DESC *Desc ) { - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_STATUS Status; UINT8 i; =20 - if (PcdGetSize (PcdPciEAhci) < Desc->AhciDevCount) { - DEBUG((DEBUG_ERROR, "NonDiscoverable: Wrong PcdPciEAhci format\n")); - return EFI_INVALID_PARAMETER; - } - for (i =3D 0; i < Desc->AhciDevCount; i++) { - if (!MVHW_DEV_ENABLED (Ahci, i)) { - continue; - } - Status =3D RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeAhci, - Desc->AhciDmaType[i], + Desc[i].SoC->AhciDmaType, NULL, NULL, 1, - Desc->AhciBaseAddresses[i], Desc->AhciMemSize[i] + Desc[i].SoC->AhciBaseAddress, + Desc[i].SoC->AhciMemSize ); =20 if (EFI_ERROR(Status)) { @@ -130,29 +105,21 @@ NonDiscoverableInitAhci ( STATIC EFI_STATUS NonDiscoverableInitSdhci ( + IN MV_BOARD_SDMMC_DESC *Desc ) { - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_STATUS Status; UINT8 i; =20 - if (PcdGetSize (PcdPciESdhci) < Desc->SdhciDevCount) { - DEBUG((DEBUG_ERROR, "NonDiscoverable: Wrong PcdPciESdhci format\n")); - return EFI_INVALID_PARAMETER; - } - - for (i =3D 0; i < Desc->SdhciDevCount; i++) { - if (!MVHW_DEV_ENABLED (Sdhci, i)) { - continue; - } - + for (i =3D 0; i < Desc->SdMmcDevCount; i++) { Status =3D RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeSdhci, - Desc->SdhciDmaType[i], + Desc[i].SoC->SdMmcDmaType, NULL, NULL, 1, - Desc->SdhciBaseAddresses[i], Desc->SdhciMemSize[i] + Desc[i].SoC->SdMmcBaseAddress, + Desc[i].SoC->SdMmcMemSize ); =20 if (EFI_ERROR(Status)) { @@ -174,22 +141,55 @@ NonDiscoverableEntryPoint ( IN EFI_SYSTEM_TABLE *SystemTable ) { + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_SDMMC_DESC *SdMmcBoardDesc; + MV_BOARD_AHCI_DESC *AhciBoardDesc; + MV_BOARD_XHCI_DESC *XhciBoardDesc; EFI_STATUS Status; =20 - Status =3D NonDiscoverableInitXhci(); + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Xhci */ + Status =3D BoardDescProtocol->BoardDescXhciGet (BoardDescProtocol, + &XhciBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D NonDiscoverableInitXhci (XhciBoardDesc); if (EFI_ERROR(Status)) { return Status; } + BoardDescProtocol->BoardDescFree (XhciBoardDesc); =20 - Status =3D NonDiscoverableInitAhci(); + /* Ahci */ + Status =3D BoardDescProtocol->BoardDescAhciGet (BoardDescProtocol, + &AhciBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D NonDiscoverableInitAhci (AhciBoardDesc); if (EFI_ERROR(Status)) { return Status; } + BoardDescProtocol->BoardDescFree (AhciBoardDesc); =20 - Status =3D NonDiscoverableInitSdhci(); + /* SdMmc */ + Status =3D BoardDescProtocol->BoardDescSdMmcGet (BoardDescProtocol, + &SdMmcBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D NonDiscoverableInitSdhci (SdMmcBoardDesc); if (EFI_ERROR(Status)) { return Status; } + BoardDescProtocol->BoardDescFree (SdMmcBoardDesc); =20 return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266410988280.596222354726; Sun, 17 Jun 2018 13:13:30 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9790720972151; Sun, 17 Jun 2018 13:12:47 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CF7A92097213B for ; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:43 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uyfKmJKN+HHIFlZerm3nnhi5/Li0h9VOpTobmaxIUWg=; b=Q/DcIRRE43d+1GAq2tLwDUPWw+HMrsrxKDb7VaKi0eQr1xYQT7J51cXQvxidDCkMEw R02JjxbbFhJfi5mOBc1iQyJOExv9bO3/O5kXFeUQjqIJldQPczXgT5XtQzlTZUaezqeJ AuitV9GRCzHkkzqjay6ZKjgQZ10tw+C+53Iwkmj4T2hh202BJ9Dw/uz9cyE4PLwRKWgZ 5B3KzpVR7nxa6dJakBG2wwwx8AHFSL/l2yKwZwBQO+Xy4CP6W+TGfDbsWs7r9cZ5vv3I k0XrZxt/GH/OZeUIMiF3UYBC/HJRuoZDiUTvA4s7bpC1LRAD54wZ6Lkp4RWh0OSZtMKr fxXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uyfKmJKN+HHIFlZerm3nnhi5/Li0h9VOpTobmaxIUWg=; b=EPiuVMAw+ZmDeIN+zH2hvViM09Z0IDKG9++ZPhJ+i96OwojPsymBw137ITUFWHGGIS NZapoM540O7JkK+bMxuqZ4LhlI+GxqZZ5hHuK5VUajrxhVrVu2NvEM8fhHVjDyIx7sML 4TDvyt9ppqIfs2KueCBHQIgY3w2PrcZSVq2nz6oH4sEc3CTvsJ65C1sCbangIpE9dJ5I xOTidjB2Ue9mrC1MJokxKw/EX9wqGSO/MmSvBDIYsCQETon580KAYErfqtmOUUTJv+9o MUklTK0YaTm5obzdG5/LxvpF5c1NX22cMIwz14OyhXG0uHV8wgM9YM77t5Zz1Zh5v8l3 3m1Q== X-Gm-Message-State: APt69E2GkMyZRwUjXBYWXQ5e29cgtWsQUYkJETed8/wdc5FipoyHsUVO OQ8AvLyPi0LswTuHk90S4Ilqm7hYB4Y= X-Google-Smtp-Source: ADUXVKKlvN23okKOiSjxaQhw8jIUcfsoa3EALLLCxmKGof7H2Iyb4mH1szzjz9Bl5VoMWYPGpgH8xw== X-Received: by 2002:a2e:9b91:: with SMTP id z17-v6mr6225461lji.121.1529266363875; Sun, 17 Jun 2018 13:12:43 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:54 +0200 Message-Id: <1529266325-18371-15-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 14/25] Marvell/Library: ComPhyLib: Get AHCI data with MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" ComPhy Library used to get Armada7k8k AHCI/SDMMC/XHCI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this library. This patch updates the driver to get AHCI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 - Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 6 +- Silicon/Marvell/Include/Library/MvHwDescLib.h | 60 --= ------------------ Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 4 ++ Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 50 ++= ++++++-------- 5 files changed, 35 insertions(+), 86 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index f2c173c..e888566 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -47,7 +47,6 @@ =20 [LibraryClasses] ArmLib - ComPhyLib DebugLib MemoryAllocationLib MppLib diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyLib.inf index ce0af54..f36c701 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -52,12 +52,16 @@ PcdLib SampleAtResetLib IoLib + UefiBootServicesTableLib =20 [Sources.common] ComPhyLib.c ComPhyCp110.c ComPhyMux.c =20 +[Protocols] + gMarvellBoardDescProtocolGuid ## CONSUMES + [FixedPcd] gMarvellTokenSpaceGuid.PcdComPhyDevices =20 @@ -80,5 +84,3 @@ gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags - - gMarvellTokenSpaceGuid.PcdPciEAhci diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 5fd514c..9f383f4 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -36,7 +36,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define __MVHWDESCLIB_H__ =20 #include -#include =20 // // Helper macros @@ -80,31 +79,6 @@ typedef struct { } MVHW_MDIO_DESC; =20 // -// NonDiscoverable devices description template definition -// -#define MVHW_MAX_XHCI_DEVS 4 -#define MVHW_MAX_AHCI_DEVS 4 -#define MVHW_MAX_SDHCI_DEVS 4 - -typedef struct { - // XHCI - UINT8 XhciDevCount; - UINTN XhciBaseAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN XhciMemSize[MVHW_MAX_XHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType[MVHW_MAX_XHCI_DEVS]; - // AHCI - UINT8 AhciDevCount; - UINTN AhciBaseAddresses[MVHW_MAX_AHCI_DEVS]; - UINTN AhciMemSize[MVHW_MAX_AHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType[MVHW_MAX_AHCI_DEVS]; - // SDHCI - UINT8 SdhciDevCount; - UINTN SdhciBaseAddresses[MVHW_MAX_SDHCI_DEVS]; - UINTN SdhciMemSize[MVHW_MAX_SDHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE SdhciDmaType[MVHW_MAX_SDHCI_DEVS]; -} MVHW_NONDISCOVERABLE_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -155,38 +129,4 @@ MVHW_MDIO_DESC mA7k8kMdioDescTemplate =3D {\ { MVHW_CP0_MDIO_BASE, MVHW_CP1_MDIO_BASE }\ } =20 -// -// Platform description of NonDiscoverable devices -// -#define MVHW_CP0_XHCI0_BASE 0xF2500000 -#define MVHW_CP0_XHCI1_BASE 0xF2510000 -#define MVHW_CP1_XHCI0_BASE 0xF4500000 -#define MVHW_CP1_XHCI1_BASE 0xF4510000 - -#define MVHW_CP0_AHCI0_BASE 0xF2540000 -#define MVHW_CP0_AHCI0_ID 0 -#define MVHW_CP1_AHCI0_BASE 0xF4540000 -#define MVHW_CP1_AHCI0_ID 1 - -#define MVHW_AP0_SDHCI0_BASE 0xF06E0000 -#define MVHW_CP0_SDHCI0_BASE 0xF2780000 - -#define DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE \ -STATIC \ -MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTemplate =3D {\ - 4, /* XHCI */\ - { MVHW_CP0_XHCI0_BASE, MVHW_CP0_XHCI1_BASE, MVHW_CP1_XHCI0_BASE, MVHW_CP= 1_XHCI1_BASE },\ - { SIZE_16KB, SIZE_16KB, SIZE_16KB, SIZE_16KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent,\ - NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent },\ - 2, /* AHCI */\ - { MVHW_CP0_AHCI0_BASE, MVHW_CP1_AHCI0_BASE },\ - { SIZE_8KB, SIZE_8KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent },\ - 2, /* SDHCI */\ - { MVHW_AP0_SDHCI0_BASE, MVHW_CP0_SDHCI0_BASE },\ - { SIZE_1KB, SIZE_1KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.h index c675d74..090116d 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -35,6 +35,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __COMPHY_H__ #define __COMPHY_H__ =20 +#include #include #include #include @@ -43,6 +44,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include + +#include =20 #define MAX_LANE_OPTIONS 10 =20 diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyCp110.c index 09994ca..5e0ebf6 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -33,7 +33,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. **************************************************************************= *****/ =20 #include "ComPhyLib.h" -#include #include =20 #define SD_LANE_ADDR_WIDTH 0x1000 @@ -46,8 +45,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CP110_PCIE_REF_CLK_TYPE0 0 #define CP110_PCIE_REF_CLK_TYPE12 1 =20 -DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; - /* * For CP-110 we have 2 Selector registers "PHY Selectors" * and " PIPE Selectors". @@ -1138,36 +1135,23 @@ ComPhySataCheckPll ( STATIC UINTN ComPhySataPowerUp ( + IN UINTN ChipId, IN UINT32 Lane, IN EFI_PHYSICAL_ADDRESS HpipeBase, IN EFI_PHYSICAL_ADDRESS ComPhyBase, - IN UINT8 SataHostId + IN MV_BOARD_AHCI_DESC *Desc ) { EFI_STATUS Status; - UINT8 *SataDeviceTable; - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); EFI_PHYSICAL_ADDRESS SdIpAddr =3D SD_ADDR(HpipeBase, Lane); EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); =20 - SataDeviceTable =3D (UINT8 *) PcdGetPtr (PcdPciEAhci); - - if (SataDeviceTable =3D=3D NULL || SataHostId >=3D PcdGetSize (PcdPciEAh= ci)) { - DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is undefined\n", SataHo= stId)); - return EFI_INVALID_PARAMETER; - } - - if (!MVHW_DEV_ENABLED (Sata, SataHostId)) { - DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is disabled\n", SataHos= tId)); - return EFI_INVALID_PARAMETER; - } - DEBUG ((DEBUG_INFO, "ComPhySata: Initialize SATA PHYs\n")); =20 DEBUG((DEBUG_INFO, "ComPhySataPowerUp: stage: MAC configuration - power = down ComPhy\n")); =20 - ComPhySataMacPowerDown (Desc->AhciBaseAddresses[SataHostId]); + ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPh= y\n")); =20 @@ -1183,7 +1167,7 @@ ComPhySataPowerUp ( =20 DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); =20 - ComPhySataPhyPowerUp (Desc->AhciBaseAddresses[SataHostId]); + ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); =20 @@ -1884,6 +1868,8 @@ ComPhyCp110Init ( EFI_STATUS Status; COMPHY_MAP *PtrComPhyMap, *SerdesMap; EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_AHCI_DESC *AhciBoardDesc; UINT32 ComPhyMaxCount, Lane; UINT32 PcieWidth =3D 0; UINT8 ChipId; @@ -1927,11 +1913,29 @@ ComPhyCp110Init ( break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: - Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP0_AHCI0_ID); - break; case COMPHY_TYPE_SATA2: case COMPHY_TYPE_SATA3: - Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP1_AHCI0_ID); + /* Obtain AHCI board description */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D BoardDescProtocol->BoardDescAhciGet (BoardDescProtocol, + &AhciBoardDesc); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D ComPhySataPowerUp (ChipId, + Lane, + HpipeBaseAddr, + ComPhyBaseAddr, + AhciBoardDesc); + + BoardDescProtocol->BoardDescFree (AhciBoardDesc); break; case COMPHY_TYPE_USB3_HOST0: case COMPHY_TYPE_USB3_HOST1: --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:44 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22e; helo=mail-lf0-x22e.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Wpwvz/nZfmMXGyInFtEIakn0VTbKo76T0DFOJa1iTwk=; b=yaoquEQcJc9Rohb2pbX+KnIclSDvpxPxLkoj5QeW8rprkZaBDPeRZhgvsNr45DltBa vwJsBUZ8nMrUMMn219r9qF4aLGEZyx6SydwZm7Tim/PAZDBdqhvVVUDd9MNLSiGsBMe+ a843MpAEFEhl1uAccG/OogAKETjSqD/+WBSeVo1diIkUOKFRDoFF2OyarS9Jh+xVbCfa vJPEf8QVa0wYlZW0aooJFRaLEXfMu8d2DWphpuiKYDxseg3hVs+Oi05rlblWRQAthwkv RmcU4Ao4JoW6dcTXrGbTwSxvEJht6Jirp08ozrvJtfFK44fc0+DjUdFGdN88eWHyUTow vvQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Wpwvz/nZfmMXGyInFtEIakn0VTbKo76T0DFOJa1iTwk=; b=n1f2IEpyn9XvaAhustXOxF9BVMGcqKEsNQdnSS06KnGaTYDcuOQ7LxUaWo2uxZV5DA OqGPQ3NksJG/X9GK31EMqeKrYtKivsJPufdFayggkLQAt+B5dXEqj+4ho5uvJQMpwYgr G/hR/e4dT/OyymapBvuWEZWxJi5akpb9tLmQGBPEOgOVVp+grJgTCQu/8IOHMwpOjZVr rBtZvYaHeJtoJW9WuqrGhCJuemx74OygjazOdLPJWqWAuTncx7kD1Ckx59ugC+J7MfKQ 4LJpKOBBec5R7lpf9QWz6H5/L61Yvmuc99usXHdo6Oj/Vofk8alfPKM4WAHbnP/9fOrX mWzg== X-Gm-Message-State: APt69E1/ONNkzMJJsuVCNeCkyD/MPJX50ZTFYzShPdncgdiBL3zD20xg ZnLtZ/Bhi95PEc7i1LcFuSOr3IN7LAg= X-Google-Smtp-Source: ADUXVKJLlvi4qmKZZjpRsHQ23NwQdL7rQi8MOBGfSpYv0d6IG87HuLki1FSzXyd2N1X3/B0CI1LoVw== X-Received: by 2002:a2e:594d:: with SMTP id n74-v6mr6632017ljb.128.1529266365059; Sun, 17 Jun 2018 13:12:45 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:55 +0200 Message-Id: <1529266325-18371-16-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 15/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with ComPhy information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescComPhyGet ()), which dynamically allocates and fills MV_SOC_COMPHY_DESC structure with the SoC description of ComPhy SerDes controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 8 +++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 20 ++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 33 ++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 94fd6fa..f372ca0 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -30,6 +30,14 @@ #define MV_SOC_AHCI_ID(Cp) ((Cp) % 2) =20 // +// Platform description of ComPhy controllers +// +#define MV_SOC_COMPHY_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x441000) +#define MV_SOC_HPIPE3_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x120000) +#define MV_SOC_COMPHY_LANE_COUNT 6 +#define MV_SOC_COMPHY_MUX_BITS 4 + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE ((Cp)) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 3b29d78..a133d1c 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -14,9 +14,29 @@ #ifndef __ARMADA_SOC_DESC_LIB_H__ #define __ARMADA_SOC_DESC_LIB_H__ =20 +#include #include =20 // +// ComPhy SoC description +// +typedef struct { + UINTN ComPhyId; + UINTN ComPhyBaseAddress; + UINTN ComPhyHpipe3BaseAddress; + UINTN ComPhyLaneCount; + UINTN ComPhyMuxBitCount; + MV_COMPHY_CHIP_TYPE ComPhyChipType; +} MV_SOC_COMPHY_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescComPhyGet ( + IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc, + IN OUT UINTN *DescCount + ); + +// // NonDiscoverable devices SoC description // // AHCI diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 97fe3f8..580c0f4 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -30,6 +30,39 @@ =20 EFI_STATUS EFIAPI +ArmadaSoCDescComPhyGet ( + IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_COMPHY_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_COMPHY_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].ComPhyBaseAddress =3D MV_SOC_COMPHY_BASE (CpIndex); + Desc[CpIndex].ComPhyHpipe3BaseAddress =3D MV_SOC_HPIPE3_BASE (CpIndex); + Desc[CpIndex].ComPhyLaneCount =3D MV_SOC_COMPHY_LANE_COUNT; + Desc[CpIndex].ComPhyMuxBitCount =3D MV_SOC_COMPHY_MUX_BITS; + Desc[CpIndex].ComPhyChipType =3D MvComPhyTypeCp110; + Desc[CpIndex].ComPhyId =3D CpIndex; + } + + *ComPhyDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescAhciGet ( IN OUT MV_SOC_AHCI_DESC **AhciDesc, IN OUT UINTN *DescCount --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266421156352.1595277796389; Sun, 17 Jun 2018 13:13:41 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 04A4A20972159; Sun, 17 Jun 2018 13:12:51 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4235D2097213E for ; Sun, 17 Jun 2018 13:12:48 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id d24-v6so21555471lfa.8 for ; Sun, 17 Jun 2018 13:12:48 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:45 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=J/VgZs1og5EnE0ONAEjuRLu7V0HLecYUbXJ1r4RIO/c=; b=hXujoCUWW0Ze2lUUiwwwWg9tuvXilWH/8bmi+zRMjK7KrvcmmARO+tEBdRSfbQHAzo kxVYnLdc8UqQRfiExFZtcXY2AVpMrwS5cnz/Fu4NhYF0vUe4n4Jzpal9OVYnhvsdkvkJ 7mQC53cZJKYVVrHgCGRX1yNU8nO6wfQbYwFH/U6Zc6JvHDE4s3xw8jOepmyEzSLkJuZk 4lxJYKvo7JGFVIsLz1k75cs9UrOxPqAN3W2Q4Y13gRA1eeeX3c0sPAJvbC7oI5L0HwN2 HqMEbAtoWtjw1AtuLND4z5bm2jXhXabNe24/4z5R5huVWJqQKhoeCQ4QECjyt2XNyuZF OY/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=J/VgZs1og5EnE0ONAEjuRLu7V0HLecYUbXJ1r4RIO/c=; b=LynPFtmV64XzVbGfaM32LMTLxbPkc5BKjg+bq6jjDs2WyBL6PRV5vGtfZN806nyR77 f7pRgJrOVpYAWrib4B3vzKDyGlfCtxtoI7C7UV6JYHECPDTBNadqS40Ozkz35OfQ3Juq cuelOztLG/hAeM2AD/FDPjjxiC2iaWIUykfHe8d/S6fAYU9BPP7mvYge5UhXxiwuItPt nr9NC9AUMdlpRrIIRO0rvIJUh4UzG9AsHGLQpVcO8kC6YquTSXS8NHfe9FM0OvE3hd8W anOmF40U8aicANOKSjI5DQY5KMvOsxLGZzuXu56ZV5pUQwHFCPcFvF0RmKRBKsxKZGmu gR6w== X-Gm-Message-State: APt69E1mZDG6fUM3trye4PiQhd4ezuPqyb6ac4vexv8pKOGcis/81WUV 6QjgABMfRihs5eAWBfROR7wNxEXw60s= X-Google-Smtp-Source: ADUXVKIuJYDbcEMJ/O+1EE3SqZ7cCWpiQ3ub1mCzCC6X3pZz9nkOPN/Byc+qU5whzTnBTrbxCzz+AQ== X-Received: by 2002:a19:6a0f:: with SMTP id u15-v6mr6029407lfu.81.1529266366368; Sun, 17 Jun 2018 13:12:46 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:56 +0200 Message-Id: <1529266325-18371-17-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 16/25] Marvell/Drivers: MvBoardDesc: Extend protocol with ComPhy support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about ComPhy controllers to the ComPhyLib. Extend ArmadaBoardDescLib with new structure MV_BOARD_COMPHY_DESC, for holding board specific data. In further steps it can be extended and replace PCD SerDes lanes' representation with the appropriate structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 8 +++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 64 ++++++++++++++++= ++++ 4 files changed, 81 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index cc0d9d4..dea99fd 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -57,6 +57,7 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] + gMarvellTokenSpaceGuid.PcdComPhyDevices gMarvellTokenSpaceGuid.PcdPciEAhci gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdPciEXhci diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 7e4fa4d..32bd915 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,14 @@ #include =20 // +// COMPHY controllers per-board description +// +typedef struct { + MV_SOC_COMPHY_DESC *SoC; + UINTN ComPhyDevCount; +} MV_BOARD_COMPHY_DESC; + +// // NonDiscoverableDevices per-board description // =20 diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index edf9491..b6dac75 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,13 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_COMPHY_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_COMPHY_DESC **ComPhyDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_AHCI_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -84,6 +91,7 @@ VOID =20 struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; + MV_BOARD_DESC_COMPHY_GET BoardDescComPhyGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 3439017..6bbe40b 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,69 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescComPhyGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_COMPHY_DESC **ComPhyDesc + ) +{ + UINT8 *ComPhyDeviceEnabled; + UINTN ComPhyCount, ComPhyDeviceTableSize, ComPhyIndex, Index; + MV_BOARD_COMPHY_DESC *BoardDesc; + MV_SOC_COMPHY_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available ComPhy controllers */ + Status =3D ArmadaSoCDescComPhyGet (&SoCDesc, &ComPhyCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled ComPhy controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + ComPhyDeviceEnabled =3D PcdGetPtr (PcdComPhyDevices); + if (ComPhyDeviceEnabled =3D=3D NULL) { + /* No ComPhy controllers declared */ + return EFI_NOT_FOUND; + } + + ComPhyDeviceTableSize =3D PcdGetSize (PcdComPhyDevices); + + /* Check if PCD with ComPhy is correctly defined */ + if (ComPhyDeviceTableSize > ComPhyCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdComPhyDevices format\n", __FUNCTION= __)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (ComPhyDeviceTableSize * sizeof (MV_BOARD= _COMPHY_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + ComPhyIndex =3D 0; + for (Index =3D 0; Index < ComPhyDeviceTableSize; Index++) { + if (!ComPhyDeviceEnabled[Index]) { + DEBUG ((DEBUG_ERROR, "%a: Skip ComPhy controller %d\n", __FUNCTION__= , Index)); + continue; + } + + BoardDesc[ComPhyIndex].SoC =3D &SoCDesc[Index]; + ComPhyIndex++; + } + + BoardDesc->ComPhyDevCount =3D ComPhyIndex; + + *ComPhyDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescAhciGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -392,6 +455,7 @@ MvBoardDescInitProtocol ( ) { BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; + BoardDescProtocol->BoardDescComPhyGet =3D MvBoardDescComPhyGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266425812776.6040617730641; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:46 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lbOgbNOJmzUnogAwGfzVR8jgxMOu+u3H5A+jLVFwFJU=; b=kPWsBKKvMR/oJn8N4z2ACnDf62iino8W2+8bxAQgKlgVxo4/69HF0rZmhKVcnYz3z8 WgeM3jn/76PGySQt1tEsGYgnBtRKZMhd1cnYggNMcSo98mWw6SYubFjmfNN8buFHlOL6 T8wdYU7MNj9gi5bK6hOyuz3pp5t+3H6QN27BoB7xPUq3+8sLAkb2UrHLLWgYzTqQdnUX cID18gf7aRmT0JfhEosM9BCXNg5L2IyOxUfGAQckrSrCNvgMVvDw36hSZXv71SKefufr BXxDcQ+6V5bJWoPTtiBJMJbBJC3gtx4Wsf+SH5MvhhVeyFQX/VAJY6l4DGEqc5Bjfvys MZRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lbOgbNOJmzUnogAwGfzVR8jgxMOu+u3H5A+jLVFwFJU=; b=UBm8/QPd+4CWdpjG4Jj7Jf2OalSsCT8xMnKUH0teXKpFbe28kRUcZadDOoL5KTlbok 6gwHb3Z4/lXdLEcLAKd+XXL+YqtOmQXT9il2w+MaD9e+BD1AJ6u0W5SftSK7eTcb2uBz 0SHkXbK/GEsmX4x0heww4yMzjlCkLqhuSTLwWZc93+w3+FF6V5wQ5aIyLIV6qLAe9+xk t0I4rR6r9tY36UL64YqvjyvvXilOMklABSVXyIcTUQRdDGlARNtS1ocgVkBJGcunypoW PaiDrNsowRvwNSl9BhihsTPm3tVqZDcc9HBiji8u2dKrmmu2m0gJ/tP6+xCRDfi1qAje Uf0w== X-Gm-Message-State: APt69E0zVW3JChsMk+bVyjIcEVTosE1IlEXIF81YqiNdE6WLiMfwTuGF iqUjIwtUEa5aFSoWvKV3m0EdZTAcZ9w= X-Google-Smtp-Source: ADUXVKLUq3vAMnFh+cGqxSiysNUoEsQaqdxm7WArnCaytFS14o27m2u5Ewl94sy1phOpagS4pOD6mw== X-Received: by 2002:a19:5c12:: with SMTP id q18-v6mr3803074lfb.145.1529266367593; Sun, 17 Jun 2018 13:12:47 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:57 +0200 Message-Id: <1529266325-18371-18-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 17/25] Marvell/Library: ComPhyLib: Switch library to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" MvComPhyLib library used to get Armada7k8k SerDes multiplexing controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this library. This patch updates the library, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Include/Library/MvHwDescLib.h | 39 ----------- Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 74 ++++++++++++-------- 2 files changed, 45 insertions(+), 68 deletions(-) diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 9f383f4..423ca17 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -35,8 +35,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MVHWDESCLIB_H__ #define __MVHWDESCLIB_H__ =20 -#include - // // Helper macros // @@ -45,20 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index]) =20 // -// CommonPhy devices description template definition -// -#define MVHW_MAX_COMPHY_DEVS 4 - -typedef struct { - UINT8 ComPhyDevCount; - UINTN ComPhyBaseAddresses[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyHpipe3BaseAddresses[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyLaneCount[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyMuxBitCount[MVHW_MAX_COMPHY_DEVS]; - MV_COMPHY_CHIP_TYPE ComPhyChipType[MVHW_MAX_COMPHY_DEVS]; -} MVHW_COMPHY_DESC; - -// // I2C devices description template definition // #define MVHW_MAX_I2C_DEVS 4 @@ -79,29 +63,6 @@ typedef struct { } MVHW_MDIO_DESC; =20 // -// Platform description of CommonPhy devices -// -#define MVHW_CP0_COMPHY_BASE 0xF2441000 -#define MVHW_CP0_HPIPE3_BASE 0xF2120000 -#define MVHW_CP0_COMPHY_LANES 6 -#define MVHW_CP0_COMPHY_MUX_BITS 4 -#define MVHW_CP1_COMPHY_BASE 0xF4441000 -#define MVHW_CP1_HPIPE3_BASE 0xF4120000 -#define MVHW_CP1_COMPHY_LANES 6 -#define MVHW_CP1_COMPHY_MUX_BITS 4 - -#define DECLARE_A7K8K_COMPHY_TEMPLATE \ -STATIC \ -MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate =3D {\ - 2,\ - { MVHW_CP0_COMPHY_BASE, MVHW_CP1_COMPHY_BASE },\ - { MVHW_CP0_HPIPE3_BASE, MVHW_CP1_HPIPE3_BASE },\ - { MVHW_CP0_COMPHY_LANES, MVHW_CP1_COMPHY_LANES },\ - { MVHW_CP0_COMPHY_MUX_BITS, MVHW_CP1_COMPHY_MUX_BITS },\ - { MvComPhyTypeCp110, MvComPhyTypeCp110 }\ -} - -// // Platform description of I2C devices // #define MVHW_CP0_I2C0_BASE 0xF2701000 diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.c index b03bc35..2ef9af4 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -34,9 +34,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "ComPhyLib.h" #include -#include - -DECLARE_A7K8K_COMPHY_TEMPLATE; =20 CHAR16 * TypeStringTable [] =3D {L"unconnected", L"PCIE0", L"PCIE1", L"PCI= E2", L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3= ", @@ -182,22 +179,20 @@ VOID InitComPhyConfig ( IN OUT CHIP_COMPHY_CONFIG *ChipConfig, IN OUT PCD_LANE_MAP *LaneData, - IN UINT8 Id + IN MV_BOARD_COMPHY_DESC *Desc ) { - MVHW_COMPHY_DESC *Desc =3D &mA7k8kComPhyDescTemplate; - - ChipConfig->ChipType =3D Desc->ComPhyChipType[Id]; - ChipConfig->ComPhyBaseAddr =3D Desc->ComPhyBaseAddresses[Id]; - ChipConfig->Hpipe3BaseAddr =3D Desc->ComPhyHpipe3BaseAddresses[Id]; - ChipConfig->LanesCount =3D Desc->ComPhyLaneCount[Id]; - ChipConfig->MuxBitCount =3D Desc->ComPhyMuxBitCount[Id]; - ChipConfig->ChipId =3D Id; + ChipConfig->ChipType =3D Desc->SoC->ComPhyChipType; + ChipConfig->ComPhyBaseAddr =3D Desc->SoC->ComPhyBaseAddress; + ChipConfig->Hpipe3BaseAddr =3D Desc->SoC->ComPhyHpipe3BaseAddress; + ChipConfig->LanesCount =3D Desc->SoC->ComPhyLaneCount; + ChipConfig->MuxBitCount =3D Desc->SoC->ComPhyMuxBitCount; + ChipConfig->ChipId =3D Desc->SoC->ComPhyId; =20 /* * Below macro contains variable name concatenation (used to form PCD's = name). */ - switch (Id) { + switch (ChipConfig->ChipId) { case 0: GetComPhyPcd (LaneData, 0); break; @@ -219,32 +214,49 @@ MvComPhyInit ( ) { EFI_STATUS Status; - CHIP_COMPHY_CONFIG ChipConfig[MVHW_MAX_COMPHY_DEVS], *PtrChipCfg; - PCD_LANE_MAP LaneData[MVHW_MAX_COMPHY_DEVS]; + CHIP_COMPHY_CONFIG *ChipConfig, *PtrChipCfg; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_COMPHY_DESC *ComPhyBoardDesc; + PCD_LANE_MAP *LaneData; UINT32 Lane, MaxComphyCount; - UINT8 *ComPhyDeviceTable, Index; + UINTN Index; =20 /* Obtain table with enabled ComPhy devices */ - ComPhyDeviceTable =3D (UINT8 *)PcdGetPtr (PcdComPhyDevices); - if (ComPhyDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdComPhyDevices\n")); - return EFI_INVALID_PARAMETER; + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D BoardDescProtocol->BoardDescComPhyGet (BoardDescProtocol, + &ComPhyBoardDesc); + if (EFI_ERROR (Status)) { + return Status; } =20 - if (PcdGetSize (PcdComPhyDevices) > MVHW_MAX_COMPHY_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdComPhyDevices format\n")); - return EFI_INVALID_PARAMETER; + ChipConfig =3D AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount * + sizeof (CHIP_COMPHY_CONFIG)); + if (ChipConfig =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + return EFI_OUT_OF_RESOURCES; + } + + LaneData =3D AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount * + sizeof (PCD_LANE_MAP)); + if (ChipConfig =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + FreePool (ChipConfig); + return EFI_OUT_OF_RESOURCES; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdComPhyDevices); Index++) { - if (!MVHW_DEV_ENABLED (ComPhy, Index)) { - DEBUG ((DEBUG_ERROR, "Skip ComPhy chip %d\n", Index)); - continue; - } + for (Index =3D 0; Index < ComPhyBoardDesc->ComPhyDevCount; Index++) { =20 PtrChipCfg =3D &ChipConfig[Index]; - InitComPhyConfig(PtrChipCfg, LaneData, Index); + InitComPhyConfig (PtrChipCfg, LaneData, &ComPhyBoardDesc[Index]); =20 /* Get the count of the SerDes of the specific chip */ MaxComphyCount =3D PtrChipCfg->LanesCount; @@ -275,5 +287,9 @@ MvComPhyInit ( PtrChipCfg->Init (PtrChipCfg); } =20 + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + FreePool (ChipConfig); + FreePool (LaneData); + return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266430136624.482227519404; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:48 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=i7np8Uh/aqBuO25Die9PfQETW8IVnK0SgHCcypy2r04=; b=gKjFVR8f9ABFvsSlk/9k6T3kXHs49U9QWRV8qEPDiNyfQw7Orgn9TyG3JOIzzGHZCO xDkxR1M1lLXMoIZlQXEibqM9s/j1qqGD4KzZoXCdCFuLuaCgCMedc8ZWpExQEFDsJQas NifeEdMdqXQ8SpzIweB6b/m0kiLT9PtUTvTjsVYHO+IN2CQpsvJjq/C2Wey1sR8e3l6X RbDiVLDiYIkbYgAOKdpABVQCRN1DuLKLRGwjCndj3X9yICslG1M3EdT687TOcTgdW1c+ BJDPCwiRIysdqyGtVh3Uz01E72KkGauXwd2SEDB6QwaDuBQm9kjs+v9uoqybJoZ87nuC gHfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=i7np8Uh/aqBuO25Die9PfQETW8IVnK0SgHCcypy2r04=; b=sHieVhiEj9ECVcUHC8xULXv9lbdy12aG+4qoPcsftdiaHmYFQrcJ3ZHjCn+5P47NBZ pT4fHB9OYmRqeOpLbGOhsbR5Jg6Le34rU3+zvkd3u7S16/NvuUi6eXwnYMznfcXb9T8o 9SmK9zCgKKMXOmyb6r/BAKTwqdZzIE3ujjJctT52HFtIRb5UdNDsP+4G8qmGXUuXa27e vgqJaAMIwkKbh5iuuBnaQxfLtJx0KI+2tqwQ7Iu/jKigLhYd86snfrxIu556fF97KB53 8oM10NwgQpuimFfN/hVhnDLxP11M6yMBzneLW7ASAhVSP4/hKMJOc5xBmgSi3LiaxXbH h4Dw== X-Gm-Message-State: APt69E3lS4sx4H1YX5NPQaNQtJkAGh9XyXviGLpP8DXva/vBce7W2Xsp 4igGJwecA/SgO8vMbPfiqyvbYM3GNA0= X-Google-Smtp-Source: ADUXVKKIp7bjo24QWJZWjV6vyjBb2bibSpV3J6Z3VwF3PYZwZmSujp272l8pp/Nd740AbkjQugOzwQ== X-Received: by 2002:a19:f71a:: with SMTP id z26-v6mr5469512lfe.137.1529266368780; Sun, 17 Jun 2018 13:12:48 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:58 +0200 Message-Id: <1529266325-18371-19-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 18/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with MDIO information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescMdioGet ()), which dynamically allocates and fills MV_SOC_MDIO_DESC structure with the SoC description of Mdio controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 6 ++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 15 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 29 ++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index f372ca0..c864f94 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -38,6 +38,12 @@ #define MV_SOC_COMPHY_MUX_BITS 4 =20 // +// Platform description of MDIO controllers +// +#define MV_SOC_MDIO_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x12A200) +#define MV_SOC_MDIO_ID(Cp) (Cp) + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE ((Cp)) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index a133d1c..304d068 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -37,6 +37,21 @@ ArmadaSoCDescComPhyGet ( ); =20 // +// MDIO +// +typedef struct { + UINTN MdioId; + UINTN MdioBaseAddress; +} MV_SOC_MDIO_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescMdioGet ( + IN OUT MV_SOC_MDIO_DESC **MdioDesc, + IN OUT UINTN *DescCount + ); + +// // NonDiscoverable devices SoC description // // AHCI diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 580c0f4..652677f 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -63,6 +63,35 @@ ArmadaSoCDescComPhyGet ( =20 EFI_STATUS EFIAPI +ArmadaSoCDescMdioGet ( + IN OUT MV_SOC_MDIO_DESC **MdioDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_MDIO_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_MDIO_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].MdioId =3D MV_SOC_MDIO_ID (CpIndex); + Desc[CpIndex].MdioBaseAddress =3D MV_SOC_MDIO_BASE (CpIndex); + } + + *MdioDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescAhciGet ( IN OUT MV_SOC_AHCI_DESC **AhciDesc, IN OUT UINTN *DescCount --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266434955299.47936504928623; Sun, 17 Jun 2018 13:13:54 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 88F3B20972832; Sun, 17 Jun 2018 13:12:54 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DB5F72097214C for ; Sun, 17 Jun 2018 13:12:51 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id d24-v6so21555618lfa.8 for ; Sun, 17 Jun 2018 13:12:51 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:49 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Vb8UocRCNRZ1bHPjM44PrKUkq9FgfhHDL/Ff7W46Za4=; b=gKPNCDQFWHxr2oqCyWVLkpm54LJf89g6J52BGV/AZRpoR47WSxlZJdRjhFq155gIiJ u1AnUi4S1o6ZFIV0/y5regT8TF6d/5Oss0gLvskB5IJh8nkPDZIWU7n3/t35Verh/nhH P0LTRZeQqqN3JL9m3T0DVTNop98ft2x6sYYt1tPLcrDz2u1mr78ugzi6V/1qn4jHS5Li RxbYz/uN7atA/h/J1XLXQUGsZ7zRax9DPfcfC6iSdIphbTWM1UkpVXgbK/pZ8mkY+mq0 7zysZg5kfkPOhw+xzaJTWVGGUqUHOd7N91mEhYc1BrqrghkBpzMfOUg77qpI6LVJpKqh ZBGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Vb8UocRCNRZ1bHPjM44PrKUkq9FgfhHDL/Ff7W46Za4=; b=XIIuFyChYkEL378WAKde6D+jtXkKVF1CmZey6+BcGXikPLlXc4g/GfwAFT1wyR6VyI P0Uf8UMw2jOKcla6tKzVATwYzkPF1SSYh32d8SR+buEyW3hVlUUehWeO01Vl8uMpQyuk GxoMxCevl/0w7yLOVb/n9JkwDuVc+PVGVS5AvW0L6bmPpMsr0z584w5332ZHXpf5jh+t +9WfnHH5jIOmy5u1tXpz+zzGGz1Ngdybf4lJCjvYTOPFGGUurzHzK61bd1DOKNU+e9tj v+zmCNuRANNxjyyLtyb9MSetSJwitosJ4/G8z+zbSzEdVmn4XNrF4YZ8CgMt4XZqJ7kG /aQQ== X-Gm-Message-State: APt69E1onnKbXZiwJxqYOr98KuAAx3MOtYtM28mh8j/J4aZxD0+sC+RQ +b/ohHJXKKEP3jFPr7NEFABE9CMv2KI= X-Google-Smtp-Source: ADUXVKIwM6tDqZnQ7XsECCqDvDeKVxzdbfcR8tec7ugJ+M1sXCbgibTvFx+vDlqFyFCr/jopKywtHw== X-Received: by 2002:a19:9f95:: with SMTP id i143-v6mr6026127lfe.125.1529266369925; Sun, 17 Jun 2018 13:12:49 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:59 +0200 Message-Id: <1529266325-18371-20-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 19/25] Marvell/Drivers: MvBoardDesc: Extend protocol with MDIO support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about MDIO controllers to the Mdio driver. Extend ArmadaBoardDescLib with new structure MV_BOARD_MDIO_DESC, for holding board specific data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 8 +++++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 36 ++++++++++++++++= ++++ 3 files changed, 52 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 32bd915..b11fa9d 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -25,6 +25,14 @@ typedef struct { } MV_BOARD_COMPHY_DESC; =20 // +// MDIO devices per-board description +// +typedef struct { + MV_SOC_MDIO_DESC *SoC; + UINTN MdioDevCount; +} MV_BOARD_MDIO_DESC; + +// // NonDiscoverableDevices per-board description // =20 diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index b6dac75..55297f5 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -50,6 +50,13 @@ EFI_STATUS =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_MDIO_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_MDIO_DESC **MdioDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_AHCI_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -92,6 +99,7 @@ VOID struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_COMPHY_GET BoardDescComPhyGet; + MV_BOARD_DESC_MDIO_GET BoardDescMdioGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 6bbe40b..5dfc559 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -100,6 +100,41 @@ MvBoardDescComPhyGet ( =20 STATIC EFI_STATUS +MvBoardDescMdioGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_MDIO_DESC **MdioDesc + ) +{ + MV_BOARD_MDIO_DESC *BoardDesc; + MV_SOC_MDIO_DESC *SoCDesc; + UINTN MdioCount, Index; + EFI_STATUS Status; + + /* Get SoC data about all available MDIO controllers */ + Status =3D ArmadaSoCDescMdioGet (&SoCDesc, &MdioCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (MdioCount * sizeof (MV_BOARD_MDIO_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < MdioCount; Index++) { + BoardDesc[Index].SoC =3D &SoCDesc[Index]; + } + + BoardDesc->MdioDevCount =3D MdioCount; + *MdioDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescAhciGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -456,6 +491,7 @@ MvBoardDescInitProtocol ( { BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescComPhyGet =3D MvBoardDescComPhyGet; + BoardDescProtocol->BoardDescMdioGet =3D MvBoardDescMdioGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 152926643975787.81430395859309; Sun, 17 Jun 2018 13:13:59 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B9ACB20972838; Sun, 17 Jun 2018 13:12:54 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 01F0420972825 for ; Sun, 17 Jun 2018 13:12:53 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id i15-v6so21569800lfc.2 for ; Sun, 17 Jun 2018 13:12:52 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:50 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8Gy3cHCMsm0ecmSBRI6IGHVj5v9VQ927WS3W+nixQpg=; b=KAPs/bsIDZjn2V/t8kRaO7tzgiCOH6oRuYI7A0d0i3HuIgOFrGcTuqePdvEZS6jjuC juzWgNIUiRpksJmjjh8QJvNC1emvOo0nvai46SafTfmV5w4wumE6RsNcduFzdG9KOjav G8S6r3qOYWLS8f+OOn/CmGMs/E3xg8XDSMdHlRc/S9ouYznS/6oZrQOdxN46cOBm4qh5 jwYn+R5igPKhwP9kojSZsE3N0he1WOGYJBEF1Yl39NcYPHKdul71CKTN48hIs1O5P5Ss Cdx8mo3znA4d848IOZoa7z9y5cxzub47J5LXrTjiCvKd7NnGgPnQcEBreov9jcfJYwFm dN4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8Gy3cHCMsm0ecmSBRI6IGHVj5v9VQ927WS3W+nixQpg=; b=Kul8OaVeCZMAkZlKawgUzN17Pjkydajsxp0JD8Tp774fvQdj2TDUXgOYiPqItexHTz OhPk/olN+Jtzr0IiaowubmCfC+z12LIcJfEa6vkmlzcSyf+FxNkNXctsqjjTj5yvKSJS t06+ABORPO1mhsGucSiTjjEvlE1a5iCjsWVivu+MD9oQDtdBLD0UCVLbHzDEXTpoFWK2 6ekwZKPCNaYj0VGhBtXnLPDyadiu4Wz8XHdzP5UoVcjbAoKUQ43FEjm4UU56tZLC4R4i Ut7RjIqg52d1hZENddK9C+3cdzQkmE+RmE2N3UfOAUpQ0yTKZ/gh8JV7VR5RaTKqrZde MJhw== X-Gm-Message-State: APt69E29STqH9YVV+3YwSUq9gNP/gNnnALum/fFfs788YkgPOLDq9W0e H2m4SzHMOu+W9Va/sQh5I9z6XK84RjU= X-Google-Smtp-Source: ADUXVKKql9kz3OYTJCnJMIqOTfB/lhtOWNc471pe0oC34NDKbmf2hfU9AttIVDHXZe0mHhPncOTAaw== X-Received: by 2002:a19:d405:: with SMTP id l5-v6mr4009732lfg.28.1529266371101; Sun, 17 Jun 2018 13:12:51 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:12:00 +0200 Message-Id: <1529266325-18371-21-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 20/25] Marvell/Drivers: MvMdioDxe: Enable 64bit addressing X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In order to be prepared for operating on registers in 64-bit address space, this patch adjusts the MDIO controllers base address array. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c b/Silicon/Ma= rvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c index 12aabad..6c0a129 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c @@ -70,7 +70,7 @@ MdioCheckParam ( STATIC EFI_STATUS MdioWaitReady ( - UINT32 MdioBase + UINTN MdioBase ) { UINT32 Timeout =3D MVEBU_SMI_TIMEOUT; @@ -92,7 +92,7 @@ MdioWaitReady ( STATIC EFI_STATUS MdioWaitValid ( - UINT32 MdioBase + UINTN MdioBase ) { UINT32 Timeout =3D MVEBU_SMI_TIMEOUT; @@ -122,7 +122,7 @@ MdioOperation ( IN OUT UINT32 *Data ) { - UINT32 MdioBase =3D This->BaseAddresses[MdioIndex]; + UINTN MdioBase =3D This->BaseAddresses[MdioIndex]; UINT32 MdioReg; EFI_STATUS Status; =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266444358457.37237491317103; Sun, 17 Jun 2018 13:14:04 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EA6382097283E; Sun, 17 Jun 2018 13:12:55 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4D70920972826 for ; Sun, 17 Jun 2018 13:12:54 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id i83-v6so21559210lfh.5 for ; Sun, 17 Jun 2018 13:12:54 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BAq84YYEkMg9IyqVTYYQYMT7uguTedJSNFEVqD4TwHE=; b=QMaPSjRle6A5oSw76k9hPhC7iA19Jn7UZDrgqRkli7olwmjevul5qWViJtNK3PDGkO xqNM3Sa6TAHi4Ixu5kLqm3c0TH1FIOjZFtTh4U/TK/SLy+5VhD3mYGRzHbRGr9Z+C3L5 5w4pfjM/FiXgV2mdFZEnnbNyFwh0fK8yrLxCQVM3K16A8gp7lzzaw6/iGJTpt8uIbdnk nX4dJ0xUOI/oSfKVUMburBDH3qs4n7JM44gNMFe4A6bd9UD54tsDAwMusfvsG6BE3mLZ VDOp7Qspfy83LLtuwXUXr1a5Yp4XFR0coM9Fjt6J5AWEbilmKm14NGsxYxYkVh7U2SKW p6VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BAq84YYEkMg9IyqVTYYQYMT7uguTedJSNFEVqD4TwHE=; b=OHDZvVdL76bqeHSvgwgvSA77js+A3NTRNrH6x1C0GeBnk6/FAPzkmePsUVdAAKMoHh t5C9RE2h+QizFUHZGF2HL5WkKM82BaTB/LJHU5lH154LG6M36Um1T2Nri2e1PVECvqyZ jhHywCtwBIACa/Xt7C/2LCcKI0uzGaFQ1LPkztNJYXf0EGyoqa3RRXX5LMzjL9ocAskR Q99/ppyNOd42lp0u/C7yU058e4BIV7Gro7Bi1pTxRFR/bd3T1kZpYBYGjkf3ZiHfpj4I 1jn/fQyV3Nhg1XRfEsIDnXMeiMytbcLGATgQZ8iJ52UmzVyylvUfNXMymC/0JX7By4Yp pt7Q== X-Gm-Message-State: APt69E0ULr9yPD6XqfHOrcUqmNYzIP3fzoEdRXffKUY5sUFYoN//i1yf XBeymVxWd0/ohAe4/oHu3OquhOuv62Y= X-Google-Smtp-Source: ADUXVKISzZquJSyO9QZ6M7nsoBGTebnK410DNZJaEaTHxg7/FRarC0Y/vNkNTlxvLyk1l2Ry1USH8w== X-Received: by 2002:a19:931a:: with SMTP id v26-v6mr3652804lfd.88.1529266372226; Sun, 17 Jun 2018 13:12:52 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:12:01 +0200 Message-Id: <1529266325-18371-22-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 21/25] Marvell/Drivers: MvMdioDxe: Switch driver to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" MvMdioDxe driver used to get Armada7k8k controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 1 + Silicon/Marvell/Include/Library/MvHwDescLib.h | 23 ------------- Silicon/Marvell/Include/Protocol/Mdio.h | 4 +-- Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c | 35 ++++++++++++++++-= --- 4 files changed, 31 insertions(+), 32 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf b/Silicon/= Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf index c070785..739576f 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf @@ -60,6 +60,7 @@ UefiLib =20 [Protocols] + gMarvellBoardDescProtocolGuid gMarvellMdioProtocolGuid =20 [Depex] diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 423ca17..0de435d 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -53,16 +53,6 @@ typedef struct { } MVHW_I2C_DESC; =20 // -// MDIO devices description template definition -// -#define MVHW_MAX_MDIO_DEVS 2 - -typedef struct { - UINT8 MdioDevCount; - UINTN MdioBaseAddresses[MVHW_MAX_MDIO_DEVS]; -} MVHW_MDIO_DESC; - -// // Platform description of I2C devices // #define MVHW_CP0_I2C0_BASE 0xF2701000 @@ -77,17 +67,4 @@ MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ { MVHW_CP0_I2C0_BASE, MVHW_CP0_I2C1_BASE, MVHW_CP1_I2C0_BASE, MVHW_CP1_I= 2C1_BASE }\ } =20 -// -// Platform description of MDIO devices -// -#define MVHW_CP0_MDIO_BASE 0xF212A200 -#define MVHW_CP1_MDIO_BASE 0xF412A200 - -#define DECLARE_A7K8K_MDIO_TEMPLATE \ -STATIC \ -MVHW_MDIO_DESC mA7k8kMdioDescTemplate =3D {\ - 2,\ - { MVHW_CP0_MDIO_BASE, MVHW_CP1_MDIO_BASE }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Include/Protocol/Mdio.h b/Silicon/Marvell/Incl= ude/Protocol/Mdio.h index d077a8f..076ea26 100644 --- a/Silicon/Marvell/Include/Protocol/Mdio.h +++ b/Silicon/Marvell/Include/Protocol/Mdio.h @@ -35,8 +35,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MDIO_H__ #define __MDIO_H__ =20 -#include - #define MARVELL_MDIO_PROTOCOL_GUID { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0= x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} =20 typedef struct _MARVELL_MDIO_PROTOCOL MARVELL_MDIO_PROTOCOL; @@ -64,7 +62,7 @@ EFI_STATUS struct _MARVELL_MDIO_PROTOCOL { MARVELL_MDIO_READ Read; MARVELL_MDIO_WRITE Write; - UINTN BaseAddresses[MVHW_MAX_MDIO_DEVS]; + UINTN *BaseAddresses; UINTN ControllerCount; }; =20 diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c b/Silicon/Ma= rvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c index 6c0a129..72e88bd 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 **************************************************************************= *****/ =20 +#include #include #include =20 @@ -46,8 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "MvMdioDxe.h" =20 -DECLARE_A7K8K_MDIO_TEMPLATE; - STATIC EFI_STATUS MdioCheckParam ( @@ -216,24 +215,46 @@ MvMdioDxeInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_MDIO_DESC *Desc =3D &mA7k8kMdioDescTemplate; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_MDIO_DESC *MdioBoardDesc; UINT8 Index; MARVELL_MDIO_PROTOCOL *Mdio; EFI_STATUS Status; EFI_HANDLE Handle =3D NULL; =20 + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D BoardDescProtocol->BoardDescMdioGet (BoardDescProtocol, + &MdioBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Mdio =3D AllocateZeroPool (sizeof (MARVELL_MDIO_PROTOCOL)); if (Mdio =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "MdioDxe: Protocol allocation failed\n")); return EFI_OUT_OF_RESOURCES; } =20 + Mdio->BaseAddresses =3D AllocateZeroPool (MdioBoardDesc->MdioDevCount * + sizeof (UINTN)); + if (Mdio->BaseAddresses =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "MdioDxe: Protocol allocation failed\n")); + return EFI_OUT_OF_RESOURCES; + } + /* Obtain base addresses of all possible controllers */ - for (Index =3D 0; Index < Desc->MdioDevCount; Index++) { - Mdio->BaseAddresses[Index] =3D Desc->MdioBaseAddresses[Index]; + for (Index =3D 0; Index < MdioBoardDesc->MdioDevCount; Index++) { + Mdio->BaseAddresses[Index] =3D MdioBoardDesc[Index].SoC->MdioBaseAddre= ss; } =20 - Mdio->ControllerCount =3D Desc->MdioDevCount; + Mdio->ControllerCount =3D MdioBoardDesc->MdioDevCount; Mdio->Read =3D MvMdioRead; Mdio->Write =3D MvMdioWrite; =20 @@ -248,5 +269,7 @@ MvMdioDxeInitialise ( return Status; } =20 + BoardDescProtocol->BoardDescFree (MdioBoardDesc); + return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266449161241.5486867958282; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:52 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sgBVFVTgcMww4+7geSEcoKcXvIc2Zsu8/N9GeyB7Ma8=; b=oQBXm97Cx8AJknkJTUf/hguy3OgDVi+gTKiwXQuU8CQ+0HDXAXj3jjzUseYNQHEPcB /0CQh6yJQKL1dp1LuYf3AKrfvucX+0GhWJGxfGXIa42IJhvZIv6IhGkqktPRx3iaQocv VeOjTqTfqblH9Af93wsL2C35nmJ3LNOfERBAGJXGjLdG8MPZsRC7exAmJLeRRBaFr6Yn a3uIeEGSwWOKU7u1XzuwSpr+pYmPEXmlKFVDh1Xee+S1wqr7+w7/vOLPov7IGaJdjUl9 8eT5pFVWhyKlyxLMJMd9TMygdfDurRIuz8ubSaBGsR9RR9JXgEBYDMlOpHaOp5s64385 MUYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sgBVFVTgcMww4+7geSEcoKcXvIc2Zsu8/N9GeyB7Ma8=; b=BhrFlv7ZTMCNi5PIy1rrYeks4IZr0+2h5GlT1EuR/WCo5YyIXy1fs4XkFiEQGs/JOu Ek/WQ9QbalMq5i4fUdy76U6wEIdI32Yzj+mgbXTQZk2YdyjJx+6CDBdaca/fqzYbFXZF rYooRVgHuLg4u3ZmpyIDnFxyCWVlEyYeI59BNx+O13MSdTxOFRXkNsQpMtVmIIkyefO/ Hoz/+W20e3e5KBg3LoVuC+0kb8RVAzhI8LY82RI6iEqZZPsQVlIqD5PL+EZ6m/prK9i8 qU3N+Kf/V2ewYDoe9uC23zL+XVHrEt23ZTIEV7oeBfObtmIUXWFedr7YsMMsk20l4ILR tIJg== X-Gm-Message-State: APt69E0s8TO8jDHtNPP4RiJju1TH/YW2DJjauxU1z1sel5q1auaiY0us MCwePYqFeXShGpJsEyF/S05+zY4jT6E= X-Google-Smtp-Source: ADUXVKLr503AR9QZyPosAMf9iqLD4+bb+5g3y5ghKL35Dhsna18qSnTOkqf1cdrtjAPLD7xJzewtIw== X-Received: by 2002:a19:4b52:: with SMTP id y79-v6mr5549536lfa.49.1529266373470; Sun, 17 Jun 2018 13:12:53 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:12:02 +0200 Message-Id: <1529266325-18371-23-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 22/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with I2C information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescI2cGet ()), which dynamically allocates and fills MV_SOC_I2C_DESC structure with the SoC description of I2c controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 6 ++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 15 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 31 ++++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index c864f94..b1219c4 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -38,6 +38,12 @@ #define MV_SOC_COMPHY_MUX_BITS 4 =20 // +// Platform description of I2C controllers +// +#define MV_SOC_I2C_PER_CP_COUNT 2 +#define MV_SOC_I2C_BASE(I2c) (0x701000 + ((I2c) * 0x100)) + +// // Platform description of MDIO controllers // #define MV_SOC_MDIO_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x12A200) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 304d068..d2bcf2a 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -37,6 +37,21 @@ ArmadaSoCDescComPhyGet ( ); =20 // +// I2C +// +typedef struct { + UINTN I2cId; + UINTN I2cBaseAddress; +} MV_SOC_I2C_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescI2cGet ( + IN OUT MV_SOC_I2C_DESC **I2cDesc, + IN OUT UINTN *DescCount + ); + +// // MDIO // typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 652677f..6ce6bad 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -63,6 +63,37 @@ ArmadaSoCDescComPhyGet ( =20 EFI_STATUS EFIAPI +ArmadaSoCDescI2cGet ( + IN OUT MV_SOC_I2C_DESC **I2cDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_I2C_DESC *Desc; + UINTN CpCount, CpIndex, Index; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *DescCount =3D CpCount * MV_SOC_I2C_PER_CP_COUNT; + Desc =3D AllocateZeroPool (*DescCount * sizeof (MV_SOC_I2C_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + *I2cDesc =3D Desc; + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_I2C_PER_CP_COUNT; Index++) { + Desc->I2cBaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_I2C_BASE = (Index); + Desc++; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescMdioGet ( IN OUT MV_SOC_MDIO_DESC **MdioDesc, IN OUT UINTN *DescCount --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266454505738.05903400741; Sun, 17 Jun 2018 13:14:14 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 51CF520972845; Sun, 17 Jun 2018 13:12:58 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 00EEC209605C7 for ; Sun, 17 Jun 2018 13:12:57 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id z207-v6so182089lff.9 for ; Sun, 17 Jun 2018 13:12:56 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:54 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E3ADd7/6CYtFehsWEnKDKT0lI9A1ZB4Dr49pJ+S7gRs=; b=gPVndmPnYmx8JV8s4dA7sZATdHaELs5agwMimUWEVsO/4TqgjTGVYv3BLAR7PvilyX RfLhw7Pt0OhqE0f4cwvbypR5FVBMVbejRaI9VN2AIAm9MyVkV6gjnh3lt3Juhrr41EKP cWcivFC247Bmlto8wCkew57mhnBBNGavKu/PTDRUA6tWtidFgcwi+7I5UpEPWRlY7pBg CMeK4xEmgm7iOOlS0ufOQ06APzih7RmrILRHVubG5KrczuHI6GWTCoVbCeIBZ2fYuE8s y/yiP2RHLf8vWfCSG/eGRoCVfOGma8ggZ2gBx7rl+VBx+TRNPUprVj+ku4/4nsEXyXn5 cPkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E3ADd7/6CYtFehsWEnKDKT0lI9A1ZB4Dr49pJ+S7gRs=; b=WCmU/pfn/o4uVF/OKQFZpgLkPHNmncyX9V15ztOagILzVE81+9c73wePzy3AGKbPmh kB37Csf+3JlGxVlzEtUBvZmwF2RSxFZxT8H+J6VNAwEo+KHsfXS+qKEKtLWDsm2mMHcd pODHHujE7ysX71RV8/H8X02T4Wenwrg9QBz0LmYWLcOX6ctHTRtwGYb6RpX0VUtr6xAM LD8Haz5PU4q/Ol9rWsE29dxO7oowrVI+LDbAaZGhBPCbhjXv/7I/JNgxYXtAhyWwc99u BLJGPCYfTxOaNnk2Gb0nAZ8PREEUJViOkGAIChRPevm9SqhR6FG2aTya6n0zyd0WzXJI p/PQ== X-Gm-Message-State: APt69E36k/cPi47Hok2CsJXabNLnzY5AsbLltFatZI4hvw8BLH88Jp1i kAMCuqJNpuG4rZiE75NiCIcZ/FIc86o= X-Google-Smtp-Source: ADUXVKKgEULXH96NCeAEPpHCeleW0n5M0gc1gDuAJEiXei/J7wVFb5ul68O3s6WhD+5JcS3d20RO3A== X-Received: by 2002:a19:e497:: with SMTP id x23-v6mr5570783lfi.40.1529266375043; Sun, 17 Jun 2018 13:12:55 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:12:03 +0200 Message-Id: <1529266325-18371-24-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 23/25] Marvell/Drivers: MvBoardDesc: Extend protocol with I2C support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about I2C controllers to the I2c driver. Extend ArmadaBoardDescLib with new structure MV_BOARD_I2C_DESC, for holding board specific data. In further steps it should be extended and replace PCD I2C devices' representation with the appropriate structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 8 +++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 66 ++++++++++++++++= ++++ 4 files changed, 83 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index dea99fd..41f72d6 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -58,6 +58,7 @@ =20 [Pcd] gMarvellTokenSpaceGuid.PcdComPhyDevices + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled gMarvellTokenSpaceGuid.PcdPciEAhci gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdPciEXhci diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index b11fa9d..ee8e06e 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -25,6 +25,14 @@ typedef struct { } MV_BOARD_COMPHY_DESC; =20 // +// I2C devices per-board description +// +typedef struct { + MV_SOC_I2C_DESC *SoC; + UINTN I2cDevCount; +} MV_BOARD_I2C_DESC; + +// // MDIO devices per-board description // typedef struct { diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index 55297f5..1d57a16 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -50,6 +50,13 @@ EFI_STATUS =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_I2C_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_I2C_DESC **I2cDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_MDIO_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_MDIO_DESC **MdioDesc @@ -99,6 +106,7 @@ VOID struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_COMPHY_GET BoardDescComPhyGet; + MV_BOARD_DESC_I2C_GET BoardDescI2cGet; MV_BOARD_DESC_MDIO_GET BoardDescMdioGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 5dfc559..39dc06c 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -100,6 +100,71 @@ MvBoardDescComPhyGet ( =20 STATIC EFI_STATUS +MvBoardDescI2cGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_I2C_DESC **I2cDesc + ) +{ + UINT8 *I2cDeviceEnabled; + UINTN I2cCount, I2cDeviceEnabledSize, I2cIndex, Index; + MV_BOARD_I2C_DESC *BoardDesc; + MV_SOC_I2C_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available I2C controllers */ + Status =3D ArmadaSoCDescI2cGet (&SoCDesc, &I2cCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled I2C controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + I2cDeviceEnabled =3D PcdGetPtr (PcdI2cControllersEnabled); + if (I2cDeviceEnabled =3D=3D NULL) { + /* No I2C on platform */ + return EFI_SUCCESS; + } + + I2cDeviceEnabledSize =3D PcdGetSize (PcdI2cControllersEnabled); + + /* Check if PCD with I2C controllers is correctly defined */ + if (I2cDeviceEnabledSize > I2cCount) { + DEBUG ((DEBUG_ERROR, + "%a: Wrong PcdI2cControllersEnabled format\n", + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (I2cDeviceEnabledSize * sizeof (MV_BOARD_= I2C_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + I2cIndex =3D 0; + for (Index =3D 0; Index < I2cDeviceEnabledSize; Index++) { + if (!I2cDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip I2c controller %d\n", __FUNCTION__, In= dex)); + continue; + } + + BoardDesc[I2cIndex].SoC =3D &SoCDesc[Index]; + I2cIndex++; + } + + BoardDesc->I2cDevCount =3D I2cIndex; + + *I2cDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescMdioGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_MDIO_DESC **MdioDesc @@ -491,6 +556,7 @@ MvBoardDescInitProtocol ( { BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescComPhyGet =3D MvBoardDescComPhyGet; + BoardDescProtocol->BoardDescI2cGet =3D MvBoardDescI2cGet; BoardDescProtocol->BoardDescMdioGet =3D MvBoardDescMdioGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266460431185.07292234176384; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:55 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=txjmPRBCWDECdYrUOWxvSUnyTROVyn7Mkw4rN44bmo8=; b=OglvTktCY7aL+w7U6/dykaqkY2YYyWE5rRbRH+kYHCINPzHqkz98pqxhQYeLxZoI3F gvbJ7aqfMmXvwuv08JK7eMX+WfKiV7To2cyzivHZIxiCJKQ2pWN+wpWKRP3KFfGp5Jvf x3lq0dAbdI4ljLPIKceN66qWiO3Z7tQOyk6f8UDWtL7o1cfhrfnoqGIpZo1ff1MhzVPP BsBj8Db2jKzKQygcMpI+0LkWZo6/bswEmqGsf2XiEVLU1pjvIg/F+5NHy6e8OkHBTQHI b/U7yj6p4uBWvmSXt37IA58WKpIfos2Nz3B0KLcKXo9mVLxOaHFJZ48eM0wE6QBNeEL0 96mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=txjmPRBCWDECdYrUOWxvSUnyTROVyn7Mkw4rN44bmo8=; b=KpbiE1aY/jbdnVdUk7Y5JPDxH3+2BAtVd4R1k8+sKuaUm/Y3USY/5tasWdkdkWu3jC USl4RQoMrtLvmbaITfW34S0WiJTqsJBXWQpGaWx0EG3AVmvd5vt7E2mJLPkAAj7zvAgx sh0KaWlSjvtAkVbZj+gwrSaxR5UWSiuU3tNeI26hGcPGUlhGxEm+AIR51/29zRQ7Ce6p YkF4j0LyqH324bYOZqPckxGe5CKVCx85Msn+hZzS/z0/ayQKFKKPZBfChv7RULStUtUv 7Rf/sJ2vba9+2Nuq6dSeWqIPsDRNW+aN+woVOTBIVNEHB81ZzBlP32wR0teLmIdZ77YD nfWw== X-Gm-Message-State: APt69E12I8w6i8+txHAPZvyP+os7Svxj39+nuLxKu9uln1jyEtnpDyUn mCbPi7pR4UkXvluQ9KWhgGBvSUTySOY= X-Google-Smtp-Source: ADUXVKJ1CdFYDSOLrrPCvpGbKtSRvOJNYEyPN3bJcg0w/MZnYGXBV4hFyjTNcaAAk2JbOyY7Qoo2wg== X-Received: by 2002:a2e:1dd9:: with SMTP id w86-v6mr6145252lje.110.1529266376303; Sun, 17 Jun 2018 13:12:56 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:12:04 +0200 Message-Id: <1529266325-18371-25-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 24/25] Marvell/Drivers: MvI2cDxe: Switch driver to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" MvI2cDxe driver used to get Armada7k8k controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 1 + Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 37 +++++++++----------- 2 files changed, 18 insertions(+), 20 deletions(-) diff --git a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf b/Silicon/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf index a7cf52e..0eef350 100755 --- a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf +++ b/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf @@ -61,6 +61,7 @@ gEfiDevicePathProtocolGuid gEfiI2cEnumerateProtocolGuid gEfiI2cBusConfigurationManagementProtocolGuid + gMarvellBoardDescProtocolGuid =20 [Pcd] gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses diff --git a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Silicon/Marv= ell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index d6f590d..9ec4929 100755 --- a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 **************************************************************************= *****/ =20 +#include #include #include #include @@ -43,13 +44,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include #include #include -#include #include =20 #include "MvI2cDxe.h" =20 -DECLARE_A7K8K_I2C_TEMPLATE; - STATIC MV_I2C_BAUD_RATE baud_rate; =20 STATIC MV_I2C_DEVICE_PATH MvI2cDevicePathProtocol =3D { @@ -174,38 +172,37 @@ MvI2cInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_I2C_DESC *Desc =3D &mA7k8kI2cDescTemplate; - UINT8 *I2cDeviceTable, Index; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_I2C_DESC *Desc; EFI_STATUS Status; + UINTN Index; =20 - /* Obtain table with enabled I2c devices */ - I2cDeviceTable =3D (UINT8 *)PcdGetPtr (PcdI2cControllersEnabled); - if (I2cDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdI2cControllersEnabled\n")); - return EFI_INVALID_PARAMETER; + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } =20 - if (PcdGetSize (PcdI2cControllersEnabled) > MVHW_MAX_I2C_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdI2cControllersEnabled format\n")); - return EFI_INVALID_PARAMETER; + Status =3D BoardDescProtocol->BoardDescI2cGet (BoardDescProtocol, &Desc); + if (EFI_ERROR (Status)) { + return Status; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdI2cControllersEnabled); Index++= ) { - if (!MVHW_DEV_ENABLED (I2c, Index)) { - DEBUG ((DEBUG_ERROR, "Skip I2c chip %d\n", Index)); - continue; - } - + for (Index =3D 0; Index < Desc->I2cDevCount; Index++) { Status =3D MvI2cInitialiseController( ImageHandle, SystemTable, - Desc->I2cBaseAddresses[Index] + Desc[Index].SoC->I2cBaseAddress ); if (EFI_ERROR(Status)) return Status; } =20 + BoardDescProtocol->BoardDescFree (Desc); + return EFI_SUCCESS; } =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 12:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529266465836585.1540651550114; Sun, 17 Jun 2018 13:14:25 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B5C592097284A; Sun, 17 Jun 2018 13:13:01 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6262120972840 for ; Sun, 17 Jun 2018 13:12:59 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id n24-v6so5818185lfh.3 for ; Sun, 17 Jun 2018 13:12:59 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:56 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0feOdrq7dn5ZqdPT5VLE+R+2QganUy0gyXPohr/KRPA=; b=RFB56RVgzeB13ONV5EZ2ytRBjubhBTq94GXOSwpaAVn7NZdaAWbguvhwztCP2nxI7R 82WzF1N7fGX3WDo7T6LNxH5oSEnn/LXDDTJ8wn1GzJ1qFVyBeQ7PY9H2eT5KFzdH74h2 JlNh4DosMIlPpIOwDSRRXRc+5K4TUUnD7utfWKLKn/5AIiTBO3GUpoCImegfYAL5g3iP A7cxawTyrzgHnQA1T9b+aKxX5tBMKuEBnva4w1HpPYuAqjsLpIjLg4lQyOkrYphuf+vK gT6jsyX5qP5HOqNEBL+jqGFnna9hjJrdTfJnvL0Y+HYAUqtuyNXM1YkR851/ENmbHFz1 q8lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0feOdrq7dn5ZqdPT5VLE+R+2QganUy0gyXPohr/KRPA=; b=DaePOQBn4qIqjctqKF1NsyUQ33bUPHOqQ2ICuz4Tu3lNenv6/H2fiOgaEeaZAHh20Z Omeb5YLHir/N6naHAJKI/1XeHx9w0upalO6jiRhXqyCJTUHvd4d7ugER2jypkXFBUJvQ 4o2vSe1pvkujyDtb5vn/v4FNTJ4BS8WnwL9zpjGoAScnCKt7mdiczQJvEcs7mgAZ77OW +e+oueJkrQQZ7PCy9vERVjrvpG0NFNFQ8pl02dFAyMQyvb4KEDYPlNO5HqKHi75A5REx TQ39M5QrexGMeBKL5pM3yaDbLH15dnM9MOmxx13Jnmhy8DL0pP4kN1T2J5bWFVx9RrkJ 1Smg== X-Gm-Message-State: APt69E2eKeBDNasJL51xX86uQ5yaUiP73ddRHbS5R1LmFN+OrYT3Qlzs KMz41bx+cRxumKFqShS8DFCGz3/1hbc= X-Google-Smtp-Source: ADUXVKLFjWzmxsOqKzRBgGdrpAv3r1RMHigJD6RCPNCxgdVj+0XSOZacJpmu7Jl2DkcFLeyQ1K2J9A== X-Received: by 2002:a2e:7a0f:: with SMTP id v15-v6mr6609954ljc.68.1529266377480; Sun, 17 Jun 2018 13:12:57 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:12:05 +0200 Message-Id: <1529266325-18371-26-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 25/25] Marvell/Drivers: MvPhyDxe: Remove MvHwDescLib.h dependency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Finally, after switching to new MV_BOARD_DESC solution in all drivers, stop using MvHwDescLib.h by its last user and safely remove this header. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Include/Library/MvHwDescLib.h | 70 -------------------- Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c | 4 +- 2 files changed, 2 insertions(+), 72 deletions(-) delete mode 100644 Silicon/Marvell/Include/Library/MvHwDescLib.h diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h deleted file mode 100644 index 0de435d..0000000 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ /dev/null @@ -1,70 +0,0 @@ -/*************************************************************************= ******* -Copyright (C) 2017 Marvell International Ltd. - -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute a= nd/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modific= ation, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -* Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -**************************************************************************= *****/ - -#ifndef __MVHWDESCLIB_H__ -#define __MVHWDESCLIB_H__ - -// -// Helper macros -// - -// Check if device is enabled - it expects PCD to be read to 'Device= Table' array -#define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index]) - -// -// I2C devices description template definition -// -#define MVHW_MAX_I2C_DEVS 4 - -typedef struct { - UINT8 I2cDevCount; - UINTN I2cBaseAddresses[MVHW_MAX_I2C_DEVS]; -} MVHW_I2C_DESC; - -// -// Platform description of I2C devices -// -#define MVHW_CP0_I2C0_BASE 0xF2701000 -#define MVHW_CP0_I2C1_BASE 0xF2701100 -#define MVHW_CP1_I2C0_BASE 0xF4701000 -#define MVHW_CP1_I2C1_BASE 0xF4701100 - -#define DECLARE_A7K8K_I2C_TEMPLATE \ -STATIC \ -MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ - 4,\ - { MVHW_CP0_I2C0_BASE, MVHW_CP0_I2C1_BASE, MVHW_CP1_I2C0_BASE, MVHW_CP1_I= 2C1_BASE }\ -} - -#endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c b/Silicon/Marv= ell/Drivers/Net/MvPhyDxe/MvPhyDxe.c index dd2edae..9be0489 100644 --- a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c +++ b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c @@ -41,7 +41,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include #include #include #include @@ -380,7 +379,8 @@ MvPhyInit ( MdioIndex =3D Phy2MdioController[PhyIndex]; =20 /* Verify correctness of PHY <-> MDIO assignment */ - if (!MVHW_DEV_ENABLED (Mdio, MdioIndex) || MdioIndex >=3D Mdio->Controll= erCount) { + if ((MdioDeviceTable[MdioIndex] =3D=3D 0) || + (MdioIndex >=3D Mdio->ControllerCount)) { DEBUG ((DEBUG_ERROR, "MvPhyDxe: Incorrect Mdio controller assignment f= or PHY#%d", PhyIndex)); return EFI_INVALID_PARAMETER; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel