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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:38 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mTGLnXpyErt35R2Uws/yu/dRtBA1QNCvH2TeebRNxh8=; b=I2WA+l10nnHIq+Sv0AtkQ9/vOJ1bqV+A8dhX/m4XU3JANLkOyGOo/HucCZsdMXXHUs WSTcqE+Q1ZKLmUgIXFDUai2g8+fbjaBw4hnyPK4ffqxylM7etTC4W0tzqXHmKjlUIXtY dgcGQGO0pfffbKzI8nRB2HNSa8WO/ikTcIjNFigcLdKrI9xpVjOQ40tr/1dWZSSD2cQY 0aShallYbAbKf8X5xxHNoeh2XhAmT7I36yYZF6nwZtHeKDeN8JOMlpol4GgRYBeyhY09 CluQbWC74XQFe/Nxu8mk24rLJu/jpsbzR7j9AvK/t1avCJ55TAqfpOohhp1bekKDD6TN lS4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mTGLnXpyErt35R2Uws/yu/dRtBA1QNCvH2TeebRNxh8=; b=SU0Ld1sI1U3E1iGU3wmcgxk9H9JYZF8SLl++1i00HXrtwOv40yP1+pzeumtAo8ew+i TOHLTIpyoJEjsv7d0/F/UeS+nv+k/9wmRzBz2yeDBbJJwibmu8JoX4IENw5h856Lqr2S GjwQ2UgnO7CowAwGnNXBtjys5lx6iWcG7oboKo3PJAJrhc1PDpsX+b6a5TAlHgBMQcXx HayEC8PkABbq7DFfiXP9znEiRtmhH8CEI5SjAhgtk1jMtRWj9zxG/IWE6n74UdHO4x0c m2IAXsXLuPrvae0mU667koFxRqJTZcPUzIneFgrvIleo0G9B1+UixjQR3lxW6Jn1zXAu O5QA== X-Gm-Message-State: APt69E1K67Bp7DZrCYQT2P14VlvNByiCv/O8GgH+jqsdkLlgpn41Qage pFU4w5IIzT0koY51O38Et9BR64mx+eI= X-Google-Smtp-Source: ADUXVKKjAuOJ7uHS8bydK6Mf08GGHUVQAwL68dbIQSMi1/uNAk713srx7fJXmVxU2pXRKfAXwjNHaQ== X-Received: by 2002:a19:c30b:: with SMTP id t11-v6mr3572435lff.127.1529266358728; Sun, 17 Jun 2018 13:12:38 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:50 +0200 Message-Id: <1529266325-18371-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 10/25] Marvell/Drivers: Pp2Dxe: Switch to use MARVELL_BOARD_DESC protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Pp2Dxe driver used to get Armada7k8k PP2 controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get PP2 controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 2 +- Silicon/Marvell/Include/Library/MvHwDescLib.h | 26 ------------ Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 43 ++++++++------------ 3 files changed, 19 insertions(+), 52 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Silicon/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index fcd0611..be536ab 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -67,11 +67,11 @@ gEfiSimpleNetworkProtocolGuid gEfiDevicePathProtocolGuid gEfiCpuArchProtocolGuid + gMarvellBoardDescProtocolGuid gMarvellMdioProtocolGuid gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 34d03d4..5fd514c 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -105,17 +105,6 @@ typedef struct { } MVHW_NONDISCOVERABLE_DESC; =20 // -// PP2 NIC devices description template definition -// -#define MVHW_MAX_PP2_DEVS 4 - -typedef struct { - UINT8 Pp2DevCount; - UINTN Pp2BaseAddresses[MVHW_MAX_PP2_DEVS]; - UINTN Pp2ClockFrequency[MVHW_MAX_PP2_DEVS]; -} MVHW_PP2_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -200,19 +189,4 @@ MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTem= plate =3D {\ { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent }\ } =20 -// -// Platform description of Pp2 NIC devices -// -#define MVHW_CP0_PP2_BASE 0xF2000000 -#define MVHW_CP1_PP2_BASE 0xF4000000 -#define MVHW_PP2_CLK_FREQ 333333333 - -#define DECLARE_A7K8K_PP2_TEMPLATE \ -STATIC \ -MVHW_PP2_DESC mA7k8kPp2DescTemplate =3D {\ - 2,\ - { MVHW_CP0_PP2_BASE, MVHW_CP1_PP2_BASE },\ - { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Silicon/Marvell/= Drivers/Net/Pp2Dxe/Pp2Dxe.c index 3ed10f6..02b2798 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 **************************************************************************= *****/ =20 +#include #include #include #include @@ -42,7 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include #include #include #include @@ -54,8 +54,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #define ReturnUnlock(tpl, status) do { gBS->RestoreTPL (tpl); return (stat= us); } while(0) =20 -DECLARE_A7K8K_PP2_TEMPLATE; - STATIC PP2_DEVICE_PATH Pp2DevicePathTemplate =3D { { { @@ -1343,35 +1341,28 @@ Pp2DxeInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_PP2_DESC *Desc =3D &mA7k8kPp2DescTemplate; - UINT8 *Pp2DeviceTable, Index; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_PP2_DESC *Pp2BoardDesc; MVPP2_SHARED *Mvpp2Shared; EFI_STATUS Status; + UINTN Index; =20 /* Obtain table with enabled Pp2 devices */ - Pp2DeviceTable =3D (UINT8 *)PcdGetPtr (PcdPp2Controllers); - if (Pp2DeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdPp2Controllers\n")); - return EFI_INVALID_PARAMETER; - } - - if (PcdGetSize (PcdPp2Controllers) > MVHW_MAX_PP2_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdPp2Controllers format\n")); - return EFI_INVALID_PARAMETER; + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } =20 - /* Check amount of declared ports */ - if (PcdGetSize (PcdPp2Port2Controller) > Desc->Pp2DevCount * MVPP2_MAX_P= ORT) { - DEBUG ((DEBUG_ERROR, "Pp2Dxe: Wrong too many ports declared\n")); - return EFI_INVALID_PARAMETER; + Status =3D BoardDescProtocol->BoardDescPp2Get (BoardDescProtocol, + &Pp2BoardDesc); + if (EFI_ERROR (Status)) { + return Status; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdPp2Controllers); Index++) { - if (!MVHW_DEV_ENABLED (Pp2, Index)) { - DEBUG ((DEBUG_ERROR, "Skip Pp2 controller %d\n", Index)); - continue; - } + for (Index =3D 0; Index < Pp2BoardDesc->Pp2DevCount; Index++) { =20 /* Initialize private data */ Mvpp2Shared =3D AllocateZeroPool (sizeof (MVPP2_SHARED)); @@ -1383,8 +1374,8 @@ Pp2DxeInitialise ( Status =3D Pp2DxeInitialiseController ( Index, Mvpp2Shared, - Desc->Pp2BaseAddresses[Index], - Desc->Pp2ClockFrequency[Index] + Pp2BoardDesc[Index].SoC->Pp2BaseAddress, + Pp2BoardDesc[Index].SoC->Pp2ClockFrequency ); if (EFI_ERROR(Status)) { FreePool (Mvpp2Shared); @@ -1393,5 +1384,7 @@ Pp2DxeInitialise ( } } =20 + BoardDescProtocol->BoardDescFree (Pp2BoardDesc); + return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel