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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:40 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1RmWF7/phuJ/549gJcMb/AjgHn++E3LieCpdykCfodU=; b=MXU0U7D/ZKblD4WDFNiyZ9X5SZmx4635U4Z5YspL55j6s0xJUqfCs5FnjacOTngSZ+ NORaQ2WPSHAmMwa2GVSdf20DZgtqaw1SGRVodEP36X4SGU6vqBEI0tWuxj6ZdJVNImNE Vqx6x7ATzYzMhB1om/KVngijUt3Yv56mbjv6TlqcFWNZkVTARxZfww462I/q33T7hpMZ 8YMFbtuPsE0wBfQUd4NRFSWFJ4pI0YW0I3tlxf+Bb8OnikUYPTqxf46ki98C/oWBKIBM Qi03F3dPb7QhQun6egOcS5+sIwxuhbSRwwhKAnqGAuUR6nq9H9t2Xq7bzNlgSm856bZ/ KiDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1RmWF7/phuJ/549gJcMb/AjgHn++E3LieCpdykCfodU=; b=Ijms3Yr8sKvxVX5PNXoR+iqLvD7Q/TQMsctfZ1fH0J4gpp8A8eTdI6uKv+4Fi44hal HVrhw7DLqjc16m3t9d7mRs4mCkgOjTy4C+kFX3vi3oaWBsb5iqBmXeal9+0/HDJR+nJf WjSxrr//4YGx4gxYqe/BGHnhxazaXUM0Hed74LARpemBWFRyhbaxPrLikW+2GqF4mqk5 XuJLIRMInGvSww+FVMkUQQk9odL1LCvR2lmM7tqlvs4rOcRpNevo0CPK3faE1elF8xqC qhFjHViRW6wj/TziF+VkNKPmQCO5N39snPrjJwKO1iCqGxwT2meuhJwkUkGoQZlPyeGI bicA== X-Gm-Message-State: APt69E3u8XfVafsaTiqqkcwNZCuSaz3MOuKvzsPVaR+nt01jyJ/SdReM cxiEW03Pmd0IJJZ3CzKZu5uoAQOnzYw= X-Google-Smtp-Source: ADUXVKJ/WFc5z59Rx4Wue55Zo+AwqQkrmenO1X+PPGtu8VE/R+hY24vxiXgG23eoRBfCyB3fVdZFug== X-Received: by 2002:a2e:1092:: with SMTP id 18-v6mr6713153ljq.115.1529266361296; Sun, 17 Jun 2018 13:12:41 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:52 +0200 Message-Id: <1529266325-18371-13-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 12/25] Marvell/Drivers: MvBoardDesc: Extend protocol with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about NonDiscoverableDevices to the relevant drivers and libraries. Extend ArmadaBoardDescLib with new structures (MV_BOARD_AHCI_DESC/ MV_BOARD_SDMMC_DESC/MV_BOARD_XHCI_DESC) for holding board specific data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 2 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 28 +++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 24 +++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 192 +++++++++++++++= +++++ 4 files changed, 246 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index 6f57f06..cc0d9d4 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -57,6 +57,8 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] + gMarvellTokenSpaceGuid.PcdPciEAhci + gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdPciEXhci gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index ab94877..7e4fa4d 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,34 @@ #include =20 // +// NonDiscoverableDevices per-board description +// + +// +// AHCI devices per-board description +// +typedef struct { + MV_SOC_AHCI_DESC *SoC; + UINTN AhciDevCount; +} MV_BOARD_AHCI_DESC; + +// +// SDMMC devices per-board description +// +typedef struct { + MV_SOC_SDMMC_DESC *SoC; + UINTN SdMmcDevCount; +} MV_BOARD_SDMMC_DESC; + +// +// XHCI devices per-board description +// +typedef struct { + MV_SOC_XHCI_DESC *SoC; + UINTN XhciDevCount; +} MV_BOARD_XHCI_DESC; + +// // PP2 NIC devices per-board description // typedef struct { diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index 114a0ec..edf9491 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,27 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_AHCI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_AHCI_DESC **AhciDesc + ); + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_SDMMC_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ); + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_XHCI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_XHCI_DESC **XhciDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_PP2_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_PP2_DESC **Pp2Desc @@ -62,8 +83,11 @@ VOID ); =20 struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; + MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; + MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; MV_BOARD_DESC_FREE BoardDescFree; }; =20 diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 7c0bc39..3439017 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,195 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescAhciGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_AHCI_DESC **AhciDesc + ) +{ + UINT8 *AhciDeviceEnabled; + UINTN AhciCount, AhciDeviceTableSize, AhciIndex, Index; + MV_BOARD_AHCI_DESC *BoardDesc; + MV_SOC_AHCI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available AHCI controllers */ + Status =3D ArmadaSoCDescAhciGet (&SoCDesc, &AhciCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled AHCI controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + AhciDeviceEnabled =3D PcdGetPtr (PcdPciEAhci); + if (AhciDeviceEnabled =3D=3D NULL) { + /* No AHCI on the platform */ + return EFI_SUCCESS; + } + + AhciDeviceTableSize =3D PcdGetSize (PcdPciEAhci); + + /* Check if PCD with AHCI controllers is correctly defined */ + if (AhciDeviceTableSize > AhciCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEAhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (AhciDeviceTableSize * sizeof (MV_BOARD_A= HCI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + AhciIndex =3D 0; + for (Index =3D 0; Index < AhciDeviceTableSize; Index++) { + if (!AhciDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip Ahci controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[AhciIndex].SoC =3D &SoCDesc[Index]; + AhciIndex++; + } + + BoardDesc->AhciDevCount =3D AhciIndex; + + *AhciDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvBoardDescSdMmcGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + UINT8 *SdMmcDeviceEnabled; + UINTN SdMmcCount, SdMmcDeviceTableSize, SdMmcIndex, Index; + MV_BOARD_SDMMC_DESC *BoardDesc; + MV_SOC_SDMMC_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available SDMMC controllers */ + Status =3D ArmadaSoCDescSdMmcGet (&SoCDesc, &SdMmcCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled SDMMC controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + SdMmcDeviceEnabled =3D PcdGetPtr (PcdPciESdhci); + if (SdMmcDeviceEnabled =3D=3D NULL) { + /* No SDMMC on platform */ + return EFI_SUCCESS; + } + + SdMmcDeviceTableSize =3D PcdGetSize (PcdPciESdhci); + + /* Check if PCD with SDMMC controllers is correctly defined */ + if (SdMmcDeviceTableSize > SdMmcCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciESdhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (SdMmcDeviceTableSize * sizeof (MV_BOARD_= SDMMC_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + SdMmcIndex =3D 0; + for (Index =3D 0; Index < SdMmcDeviceTableSize; Index++) { + if (!SdMmcDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip SdMmc controller %d\n", __FUNCTION__, = Index)); + continue; + } + + BoardDesc[SdMmcIndex].SoC =3D &SoCDesc[Index]; + SdMmcIndex++; + } + + BoardDesc->SdMmcDevCount =3D SdMmcIndex; + + *SdMmcDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvBoardDescXhciGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_XHCI_DESC **XhciDesc + ) +{ + UINT8 *XhciDeviceEnabled; + UINTN XhciCount, XhciDeviceTableSize, XhciIndex, Index; + MV_BOARD_XHCI_DESC *BoardDesc; + MV_SOC_XHCI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available XHCI controllers */ + Status =3D ArmadaSoCDescXhciGet (&SoCDesc, &XhciCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled XHCI controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + XhciDeviceEnabled =3D PcdGetPtr (PcdPciEXhci); + if (XhciDeviceEnabled =3D=3D NULL) { + /* No XHCI on platform */ + return EFI_SUCCESS; + } + + XhciDeviceTableSize =3D PcdGetSize (PcdPciEXhci); + + /* Check if PCD with XHCI controllers is correctly defined */ + if (XhciDeviceTableSize > XhciCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEXhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (XhciDeviceTableSize * sizeof (MV_BOARD_X= HCI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + XhciIndex =3D 0; + for (Index =3D 0; Index < XhciDeviceTableSize; Index++) { + if (!XhciDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip Xhci controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[XhciIndex].SoC =3D &SoCDesc[Index]; + XhciIndex++; + } + + BoardDesc->XhciDevCount =3D XhciIndex; + + *XhciDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescPp2Get ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_PP2_DESC **Pp2Desc @@ -202,8 +391,11 @@ MvBoardDescInitProtocol ( IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol ) { + BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; + BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; + BoardDescProtocol->BoardDescXhciGet =3D MvBoardDescXhciGet; BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; =20 return EFI_SUCCESS; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel